// SPDX-License-Identifier: GPL-2.0-or-later/* * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com> */ #include <stdio.h>#include <stdlib.h> #define unlikely(cond) (cond)#include <asm/insn.h>#include "../../../arch/x86/lib/inat.c"#include "../../../arch/x86/lib/insn.c" #define CONFIG_64BIT 1#include <asm/nops.h> #include <asm/orc_types.h>#include <objtool/check.h>#include <objtool/disas.h>#include <objtool/elf.h>#include <objtool/arch.h>#include <objtool/warn.h>#include <objtool/builtin.h>#include <arch/elf.h> const char *arch_reg_name[CFI_NUM_REGS] = {	"rax", "rcx", "rdx", "rbx",	"rsp", "rbp", "rsi", "rdi",	"r8",  "r9",  "r10", "r11",	"r12", "r13", "r14", "r15",	"ra"}; int arch_ftrace_match(const char *name){	return !strcmp(name, "__fentry__");} static int is_x86_64(const struct elf *elf){	switch (elf->ehdr.e_machine) {	case EM_X86_64:		return 1;	case EM_386:		return 0;	default:		ERROR("unexpected ELF machine type %d", elf->ehdr.e_machine);		return -1;	}} bool arch_callee_saved_reg(unsigned char reg){	switch (reg) {	case CFI_BP:	case CFI_BX:	case CFI_R12:	case CFI_R13:	case CFI_R14:	case CFI_R15:		return true; 	case CFI_AX:	case CFI_CX:	case CFI_DX:	case CFI_SI:	case CFI_DI:	case CFI_SP:	case CFI_R8:	case CFI_R9:	case CFI_R10:	case CFI_R11:	case CFI_RA:	default:		return false;	}} /* Undo the effects of __pa_symbol() if necessary */static unsigned long phys_to_virt(unsigned long pa){	s64 va = pa; 	if (va > 0)		va &= ~(0x80000000); 	return va;} s64 arch_insn_adjusted_addend(struct instruction *insn, struct reloc *reloc){	s64 addend = reloc_addend(reloc); 	if (arch_pc_relative_reloc(reloc))		addend += insn->offset + insn->len - reloc_offset(reloc); 	return phys_to_virt(addend);} static void scan_for_insn(struct section *sec, unsigned long offset,			  unsigned long *insn_off, unsigned int *insn_len){	unsigned long o = 0;	struct insn insn; 	while (1) { 		insn_decode(&insn, sec->data->d_buf + o, sec_size(sec) - o,			    INSN_MODE_64); 		if (o + insn.length > offset) {			*insn_off = o;			*insn_len = insn.length;			return;		} 		o += insn.length;	}} u64 arch_adjusted_addend(struct reloc *reloc){	unsigned int type = reloc_type(reloc);	s64 addend = reloc_addend(reloc);	unsigned long insn_off;	unsigned int insn_len; 	if (type == R_X86_64_PLT32)		return addend + 4; 	if (type != R_X86_64_PC32 || !is_text_sec(reloc->sec->base))		return addend; 	scan_for_insn(reloc->sec->base, reloc_offset(reloc),		      &insn_off, &insn_len); 	return addend + insn_off + insn_len - reloc_offset(reloc);} unsigned long arch_jump_destination(struct instruction *insn){	return insn->offset + insn->len + insn->immediate;} bool arch_pc_relative_reloc(struct reloc *reloc){	/*	 * All relocation types where P (the address of the target)	 * is included in the computation.	 */	switch (reloc_type(reloc)) {	case R_X86_64_PC8:	case R_X86_64_PC16:	case R_X86_64_PC32:	case R_X86_64_PC64: 	case R_X86_64_PLT32:	case R_X86_64_GOTPC32:	case R_X86_64_GOTPCREL:		return true; 	default:		break;	} 	return false;} #define ADD_OP(op) \	if (!(op = calloc(1, sizeof(*op)))) \		return -1; \	else for (*ops_list = op, ops_list = &op->next; op; op = NULL) /* * Helpers to decode ModRM/SIB: * * r/m| AX  CX  DX  BX |  SP |  BP |  SI  DI | *    | R8  R9 R10 R11 | R12 | R13 | R14 R15 | * Mod+----------------+-----+-----+---------+ * 00 |    [r/m]       |[SIB]|[IP+]|  [r/m]  | * 01 |  [r/m + d8]    |[S+d]|   [r/m + d8]  | * 10 |  [r/m + d32]   |[S+D]|   [r/m + d32] | * 11 |                   r/ m               | */ #define mod_is_mem()	(modrm_mod != 3)#define mod_is_reg()	(modrm_mod == 3) #define is_RIP()   ((modrm_rm & 7) == CFI_BP && modrm_mod == 0)#define have_SIB() ((modrm_rm & 7) == CFI_SP && mod_is_mem()) /* * Check the ModRM register. If there is a SIB byte then check with * the SIB base register. But if the SIB base is 5 (i.e. CFI_BP) and * ModRM mod is 0 then there is no base register. */#define rm_is(reg) (have_SIB() ? \		    sib_base == (reg) && sib_index == CFI_SP && \		    (sib_base != CFI_BP || modrm_mod != 0) :	\		    modrm_rm == (reg)) #define rm_is_mem(reg)	(mod_is_mem() && !is_RIP() && rm_is(reg))#define rm_is_reg(reg)	(mod_is_reg() && modrm_rm == (reg)) static bool has_notrack_prefix(struct insn *insn){	int i; 	for (i = 0; i < insn->prefixes.nbytes; i++) {		if (insn->prefixes.bytes[i] == 0x3e)			return true;	} 	return false;} int arch_decode_instruction(struct objtool_file *file, const struct section *sec,			    unsigned long offset, unsigned int maxlen,			    struct instruction *insn){	struct stack_op **ops_list = &insn->stack_ops;	const struct elf *elf = file->elf;	struct insn ins;	int x86_64, ret;	unsigned char op1, op2, op3, prefix,		      rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,		      modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,		      sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0;	struct stack_op *op = NULL;	struct symbol *sym;	u64 imm; 	x86_64 = is_x86_64(elf);	if (x86_64 == -1)		return -1; 	ret = insn_decode(&ins, sec->data->d_buf + offset, maxlen,			  x86_64 ? INSN_MODE_64 : INSN_MODE_32);	if (ret < 0) {		ERROR("can't decode instruction at %s:0x%lx", sec->name, offset);		return -1;	} 	insn->len = ins.length;	insn->type = INSN_OTHER; 	if (ins.vex_prefix.nbytes)		return 0; 	prefix = ins.prefixes.bytes[0]; 	op1 = ins.opcode.bytes[0];	op2 = ins.opcode.bytes[1];	op3 = ins.opcode.bytes[2]; 	if (ins.rex_prefix.nbytes) {		rex = ins.rex_prefix.bytes[0];		rex_w = X86_REX_W(rex) >> 3;		rex_r = X86_REX_R(rex) >> 2;		rex_x = X86_REX_X(rex) >> 1;		rex_b = X86_REX_B(rex);	} 	if (ins.modrm.nbytes) {		modrm = ins.modrm.bytes[0];		modrm_mod = X86_MODRM_MOD(modrm);		modrm_reg = X86_MODRM_REG(modrm) + 8*rex_r;		modrm_rm  = X86_MODRM_RM(modrm)  + 8*rex_b;	} 	if (ins.sib.nbytes) {		sib = ins.sib.bytes[0];		/* sib_scale = X86_SIB_SCALE(sib); */		sib_index = X86_SIB_INDEX(sib) + 8*rex_x;		sib_base  = X86_SIB_BASE(sib)  + 8*rex_b;	} 	switch (op1) { 	case 0x1:	case 0x29:		if (rex_w && rm_is_reg(CFI_SP)) { 			/* add/sub reg, %rsp */			ADD_OP(op) {				op->src.type = OP_SRC_ADD;				op->src.reg = modrm_reg;				op->dest.type = OP_DEST_REG;				op->dest.reg = CFI_SP;			}		}		break; 	case 0x50 ... 0x57: 		/* push reg */		ADD_OP(op) {			op->src.type = OP_SRC_REG;			op->src.reg = (op1 & 0x7) + 8*rex_b;			op->dest.type = OP_DEST_PUSH;		} 		break; 	case 0x58 ... 0x5f: 		/* pop reg */		ADD_OP(op) {			op->src.type = OP_SRC_POP;			op->dest.type = OP_DEST_REG;			op->dest.reg = (op1 & 0x7) + 8*rex_b;		} 		break; 	case 0x68:	case 0x6a:		/* push immediate */		ADD_OP(op) {			op->src.type = OP_SRC_CONST;			op->dest.type = OP_DEST_PUSH;		}		break; 	case 0x70 ... 0x7f:		insn->type = INSN_JUMP_CONDITIONAL;		break; 	case 0x80 ... 0x83:		/*		 * 1000 00sw : mod OP r/m : immediate		 *		 * s - sign extend immediate		 * w - imm8 / imm32		 *		 * OP: 000 ADD    100 AND		 *     001 OR     101 SUB		 *     010 ADC    110 XOR		 *     011 SBB    111 CMP		 */ 		/* 64bit only */		if (!rex_w)			break; 		/* %rsp target only */		if (!rm_is_reg(CFI_SP))			break; 		imm = ins.immediate.value;		if (op1 & 2) { /* sign extend */			if (op1 & 1) { /* imm32 */				imm <<= 32;				imm = (s64)imm >> 32;			} else { /* imm8 */				imm <<= 56;				imm = (s64)imm >> 56;			}		} 		switch (modrm_reg & 7) {		case 5:			imm = -imm;			fallthrough;		case 0:			/* add/sub imm, %rsp */			ADD_OP(op) {				op->src.type = OP_SRC_ADD;				op->src.reg = CFI_SP;				op->src.offset = imm;				op->dest.type = OP_DEST_REG;				op->dest.reg = CFI_SP;			}			break; 		case 4:			/* and imm, %rsp */			ADD_OP(op) {				op->src.type = OP_SRC_AND;				op->src.reg = CFI_SP;				op->src.offset = ins.immediate.value;				op->dest.type = OP_DEST_REG;				op->dest.reg = CFI_SP;			}			break; 		default:			/* ERROR ? */			break;		} 		break; 	case 0x89:		if (!rex_w)			break; 		if (mod_is_reg()) {			/* mov reg, reg */			ADD_OP(op) {				op->src.type = OP_SRC_REG;				op->src.reg = modrm_reg;				op->dest.type = OP_DEST_REG;				op->dest.reg = modrm_rm;			}			break;		} 		/* skip RIP relative displacement */		if (is_RIP())			break; 		/* skip nontrivial SIB */		if (have_SIB()) {			modrm_rm = sib_base;			if (sib_index != CFI_SP)				break;		} 		/* mov %rsp, disp(%reg) */		if (modrm_reg == CFI_SP) {			ADD_OP(op) {				op->src.type = OP_SRC_REG;				op->src.reg = CFI_SP;				op->dest.type = OP_DEST_REG_INDIRECT;				op->dest.reg = modrm_rm;				op->dest.offset = ins.displacement.value;			}			break;		} 		fallthrough;	case 0x88:		if (!rex_w)			break; 		if (rm_is_mem(CFI_BP)) { 			/* mov reg, disp(%rbp) */			ADD_OP(op) {				op->src.type = OP_SRC_REG;				op->src.reg = modrm_reg;				op->dest.type = OP_DEST_REG_INDIRECT;				op->dest.reg = CFI_BP;				op->dest.offset = ins.displacement.value;			}			break;		} 		if (rm_is_mem(CFI_SP)) { 			/* mov reg, disp(%rsp) */			ADD_OP(op) {				op->src.type = OP_SRC_REG;				op->src.reg = modrm_reg;				op->dest.type = OP_DEST_REG_INDIRECT;				op->dest.reg = CFI_SP;				op->dest.offset = ins.displacement.value;			}			break;		} 		break; 	case 0x8b:		if (!rex_w)			break; 		if (rm_is_mem(CFI_BP)) { 			/* mov disp(%rbp), reg */			ADD_OP(op) {				op->src.type = OP_SRC_REG_INDIRECT;				op->src.reg = CFI_BP;				op->src.offset = ins.displacement.value;				op->dest.type = OP_DEST_REG;				op->dest.reg = modrm_reg;			}			break;		} 		if (rm_is_mem(CFI_SP)) { 			/* mov disp(%rsp), reg */			ADD_OP(op) {				op->src.type = OP_SRC_REG_INDIRECT;				op->src.reg = CFI_SP;				op->src.offset = ins.displacement.value;				op->dest.type = OP_DEST_REG;				op->dest.reg = modrm_reg;			}			break;		} 		break; 	case 0x8d:		if (mod_is_reg()) {			WARN("invalid LEA encoding at %s:0x%lx", sec->name, offset);			break;

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