// SPDX-License-Identifier: GPL-2.0/* * AArch64 code * * Copyright (C) 2018, Red Hat, Inc. */ #include <linux/compiler.h>#include <assert.h> #include "guest_modes.h"#include "kvm_util.h"#include "processor.h"#include "ucall_common.h"#include "vgic.h" #include <linux/bitfield.h>#include <linux/sizes.h> #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN 0xac0000 static gva_t exception_handlers; static u64 pgd_index(struct kvm_vm *vm, gva_t gva){ unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; u64 mask = (1UL << (vm->va_bits - shift)) - 1; return (gva >> shift) & mask;} static u64 pud_index(struct kvm_vm *vm, gva_t gva){ unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift; u64 mask = (1UL << (vm->page_shift - 3)) - 1; TEST_ASSERT(vm->mmu.pgtable_levels == 4, "Mode %d does not have 4 page table levels", vm->mode); return (gva >> shift) & mask;} static u64 pmd_index(struct kvm_vm *vm, gva_t gva){ unsigned int shift = (vm->page_shift - 3) + vm->page_shift; u64 mask = (1UL << (vm->page_shift - 3)) - 1; TEST_ASSERT(vm->mmu.pgtable_levels >= 3, "Mode %d does not have >= 3 page table levels", vm->mode); return (gva >> shift) & mask;} static u64 pte_index(struct kvm_vm *vm, gva_t gva){ u64 mask = (1UL << (vm->page_shift - 3)) - 1; return (gva >> vm->page_shift) & mask;} static inline bool use_lpa2_pte_format(struct kvm_vm *vm){ return (vm->page_size == SZ_4K || vm->page_size == SZ_16K) && (vm->pa_bits > 48 || vm->va_bits > 48);} static u64 addr_pte(struct kvm_vm *vm, u64 pa, u64 attrs){ u64 pte; if (use_lpa2_pte_format(vm)) { pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift); pte |= FIELD_GET(GENMASK(51, 50), pa) << PTE_ADDR_51_50_LPA2_SHIFT; attrs &= ~PTE_ADDR_51_50_LPA2; } else { pte = pa & PTE_ADDR_MASK(vm->page_shift); if (vm->page_shift == 16) pte |= FIELD_GET(GENMASK(51, 48), pa) << PTE_ADDR_51_48_SHIFT; } pte |= attrs; return pte;} static u64 pte_addr(struct kvm_vm *vm, u64 pte){ u64 pa; if (use_lpa2_pte_format(vm)) { pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift); pa |= FIELD_GET(PTE_ADDR_51_50_LPA2, pte) << 50; } else { pa = pte & PTE_ADDR_MASK(vm->page_shift); if (vm->page_shift == 16) pa |= FIELD_GET(PTE_ADDR_51_48, pte) << 48; } return pa;} static u64 ptrs_per_pgd(struct kvm_vm *vm){ unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; return 1 << (vm->va_bits - shift);} static u64 __maybe_unused ptrs_per_pte(struct kvm_vm *vm){ return 1 << (vm->page_shift - 3);} void virt_arch_pgd_alloc(struct kvm_vm *vm){ size_t nr_pages = vm_page_align(vm, ptrs_per_pgd(vm) * 8) / vm->page_size; if (vm->mmu.pgd_created) return; vm->mmu.pgd = vm_phy_pages_alloc(vm, nr_pages, KVM_GUEST_PAGE_TABLE_MIN_PADDR, vm->memslots[MEM_REGION_PT]); vm->mmu.pgd_created = true;} static void _virt_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa, u64 flags){ u8 attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT); u64 pg_attr; u64 *ptep; TEST_ASSERT((gva % vm->page_size) == 0, "Virtual address not on page boundary,\n" " gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size); TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), "Invalid virtual address, gva: 0x%lx", gva); TEST_ASSERT((gpa % vm->page_size) == 0, "Physical address not on page boundary,\n" " gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size); TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, "Physical address beyond beyond maximum supported,\n" " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", gpa, vm->max_gfn, vm->page_size); ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PGD_TYPE_TABLE | PTE_VALID); switch (vm->mmu.pgtable_levels) { case 4: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PUD_TYPE_TABLE | PTE_VALID); /* fall through */ case 3: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PMD_TYPE_TABLE | PTE_VALID); /* fall through */ case 2: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; break; default: TEST_FAIL("Page table levels must be 2, 3, or 4"); } pg_attr = PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID; if (!use_lpa2_pte_format(vm)) pg_attr |= PTE_SHARED; *ptep = addr_pte(vm, gpa, pg_attr);} void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa){ u64 attr_idx = MT_NORMAL; _virt_pg_map(vm, gva, gpa, attr_idx);} u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level){ u64 *ptep; if (!vm->mmu.pgd_created) goto unmapped_gva; ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; if (level == 0) return ptep; switch (vm->mmu.pgtable_levels) { case 4: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; if (level == 1) break; /* fall through */ case 3: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; if (level == 2) break; /* fall through */ case 2: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; break; default: TEST_FAIL("Page table levels must be 2, 3, or 4"); } return ptep; unmapped_gva: TEST_FAIL("No mapping for vm virtual address, gva: 0x%lx", gva); exit(EXIT_FAILURE);} u64 *virt_get_pte_hva(struct kvm_vm *vm, gva_t gva){ return virt_get_pte_hva_at_level(vm, gva, 3);} gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva){ u64 *ptep = virt_get_pte_hva(vm, gva); return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));} static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, u64 page, int level){#ifdef DEBUG static const char * const type[] = { "", "pud", "pmd", "pte" }; u64 pte, *ptep; if (level == 4) return; for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { ptep = addr_gpa2hva(vm, pte); if (!*ptep) continue; fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", type[level], pte, *ptep, ptep); pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level + 1); }#endif} void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent){ int level = 4 - (vm->mmu.pgtable_levels - 1); u64 pgd, *ptep; if (!vm->mmu.pgd_created) return; for (pgd = vm->mmu.pgd; pgd < vm->mmu.pgd + ptrs_per_pgd(vm) * 8; pgd += 8) { ptep = addr_gpa2hva(vm, pgd); if (!*ptep) continue; fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", pgd, *ptep, ptep); pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level); }} bool vm_supports_el2(struct kvm_vm *vm){ const char *value = getenv("NV"); if (value && *value == '0') return false; return vm_check_cap(vm, KVM_CAP_ARM_EL2) && vm->arch.has_gic;} void kvm_get_default_vcpu_target(struct kvm_vm *vm, struct kvm_vcpu_init *init){ struct kvm_vcpu_init preferred = {}; vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred); if (vm_supports_el2(vm)) preferred.features[0] |= BIT(KVM_ARM_VCPU_HAS_EL2); *init = preferred;} void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init){ struct kvm_vcpu_init default_init = { .target = -1, }; struct kvm_vm *vm = vcpu->vm; u64 sctlr_el1, tcr_el1, ttbr0_el1; if (!init) { kvm_get_default_vcpu_target(vm, &default_init); init = &default_init; } vcpu_ioctl(vcpu, KVM_ARM_VCPU_INIT, init); vcpu->init = *init; /* * Enable FP/ASIMD to avoid trapping when accessing Q0-Q15 * registers, which the variable argument list macros do. */ vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_CPACR_EL1), 3 << 20); sctlr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1)); tcr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1)); /* Configure base granule size */ switch (vm->mode) { case VM_MODE_PXXVYY_4K: TEST_FAIL("AArch64 does not support 4K sized pages " "with ANY-bit physical address ranges"); case VM_MODE_P52V48_64K: case VM_MODE_P48V48_64K: case VM_MODE_P40V48_64K: case VM_MODE_P36V48_64K: tcr_el1 |= TCR_TG0_64K; break; case VM_MODE_P52V48_16K: case VM_MODE_P48V48_16K: case VM_MODE_P40V48_16K: case VM_MODE_P36V48_16K: case VM_MODE_P36V47_16K: tcr_el1 |= TCR_TG0_16K; break; case VM_MODE_P52V48_4K: case VM_MODE_P48V48_4K: case VM_MODE_P40V48_4K: case VM_MODE_P36V48_4K: tcr_el1 |= TCR_TG0_4K; break; default: TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); } ttbr0_el1 = vm->mmu.pgd & GENMASK(47, vm->page_shift); /* Configure output size */ switch (vm->mode) { case VM_MODE_P52V48_4K: case VM_MODE_P52V48_16K: case VM_MODE_P52V48_64K: tcr_el1 |= TCR_IPS_52_BITS; ttbr0_el1 |= FIELD_GET(GENMASK(51, 48), vm->mmu.pgd) << 2; break; case VM_MODE_P48V48_4K: case VM_MODE_P48V48_16K: case VM_MODE_P48V48_64K: tcr_el1 |= TCR_IPS_48_BITS; break; case VM_MODE_P40V48_4K: case VM_MODE_P40V48_16K: case VM_MODE_P40V48_64K: tcr_el1 |= TCR_IPS_40_BITS; break; case VM_MODE_P36V48_4K: case VM_MODE_P36V48_16K: case VM_MODE_P36V48_64K: case VM_MODE_P36V47_16K: tcr_el1 |= TCR_IPS_36_BITS; break; default: TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); } sctlr_el1 |= SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I; tcr_el1 |= TCR_IRGN0_WBWA | TCR_ORGN0_WBWA | TCR_SH0_INNER; tcr_el1 |= TCR_T0SZ(vm->va_bits); tcr_el1 |= TCR_TBI1; tcr_el1 |= TCR_EPD1_MASK; if (use_lpa2_pte_format(vm)) tcr_el1 |= TCR_DS; vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1), sctlr_el1); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1), tcr_el1); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_MAIR_EL1), DEFAULT_MAIR_EL1); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TTBR0_EL1), ttbr0_el1); vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL1), vcpu->id); if (!vcpu_has_el2(vcpu)) return; vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2), HCR_EL2_RW | HCR_EL2_TGE | HCR_EL2_E2H);} void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent){ u64 pstate, pc; pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n", indent, "", pstate, pc);} void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code){ vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code);} static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init){ size_t stack_size; gva_t stack_gva; struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : vm->page_size; stack_gva = __vm_alloc(vm, stack_size, DEFAULT_ARM64_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); aarch64_vcpu_setup(vcpu, init); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_gva + stack_size); return vcpu;} struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init, void *guest_code){ struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init); vcpu_arch_set_entry_point(vcpu, guest_code); return vcpu;} struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id){ return __aarch64_vcpu_add(vm, vcpu_id, NULL);} void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...){ va_list ap; int i; TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" " num: %u", num); va_start(ap, num); for (i = 0; i < num; i++) { vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]), va_arg(ap, u64)); } va_end(ap);} void kvm_exit_unexpected_exception(int vector, u64 ec, bool valid_ec){ ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec); while (1) ;} void assert_on_unhandled_exception(struct kvm_vcpu *vcpu){ struct ucall uc; if (get_ucall(vcpu, &uc) != UCALL_UNHANDLED) return; if (uc.args[2]) /* valid_ec */ { assert(VECTOR_IS_SYNC(uc.args[0])); TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)", uc.args[0], uc.args[1]); } else { assert(!VECTOR_IS_SYNC(uc.args[0])); TEST_FAIL("Unexpected exception (vector:0x%lx)", uc.args[0]); }} struct handlers { handler_fn exception_handlers[VECTOR_NUM][ESR_ELx_EC_MAX + 1];}; void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu){ extern char vectors; vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (u64)&vectors);Lines 1–500 of 728. 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// SPDX-License-Identifier: GPL-2.0 /* * AArch64 code * * Copyright (C) 2018, Red Hat, Inc. */ #include <linux/compiler.h> #include <assert.h> #include "guest_modes.h" #include "kvm_util.h" #include "processor.h" #include "ucall_common.h" #include "vgic.h" #include <linux/bitfield.h> #include <linux/sizes.h> #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN 0xac0000 static gva_t exception_handlers; static u64 pgd_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; u64 mask = (1UL << (vm->va_bits - shift)) - 1; return (gva >> shift) & mask; } static u64 pud_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift; u64 mask = (1UL << (vm->page_shift - 3)) - 1; TEST_ASSERT(vm->mmu.pgtable_levels == 4, "Mode %d does not have 4 page table levels", vm->mode); return (gva >> shift) & mask; } static u64 pmd_index(struct kvm_vm *vm, gva_t gva) { unsigned int shift = (vm->page_shift - 3) + vm->page_shift; u64 mask = (1UL << (vm->page_shift - 3)) - 1; TEST_ASSERT(vm->mmu.pgtable_levels >= 3, "Mode %d does not have >= 3 page table levels", vm->mode); return (gva >> shift) & mask; } static u64 pte_index(struct kvm_vm *vm, gva_t gva) { u64 mask = (1UL << (vm->page_shift - 3)) - 1; return (gva >> vm->page_shift) & mask; } static inline bool use_lpa2_pte_format(struct kvm_vm *vm) { return (vm->page_size == SZ_4K || vm->page_size == SZ_16K) && (vm->pa_bits > 48 || vm->va_bits > 48); } static u64 addr_pte(struct kvm_vm *vm, u64 pa, u64 attrs) { u64 pte; if (use_lpa2_pte_format(vm)) { pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift); pte |= FIELD_GET(GENMASK(51, 50), pa) << PTE_ADDR_51_50_LPA2_SHIFT; attrs &= ~PTE_ADDR_51_50_LPA2; } else { pte = pa & PTE_ADDR_MASK(vm->page_shift); if (vm->page_shift == 16) pte |= FIELD_GET(GENMASK(51, 48), pa) << PTE_ADDR_51_48_SHIFT; } pte |= attrs; return pte; } static u64 pte_addr(struct kvm_vm *vm, u64 pte) { u64 pa; if (use_lpa2_pte_format(vm)) { pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift); pa |= FIELD_GET(PTE_ADDR_51_50_LPA2, pte) << 50; } else { pa = pte & PTE_ADDR_MASK(vm->page_shift); if (vm->page_shift == 16) pa |= FIELD_GET(PTE_ADDR_51_48, pte) << 48; } return pa; } static u64 ptrs_per_pgd(struct kvm_vm *vm) { unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift; return 1 << (vm->va_bits - shift); } static u64 __maybe_unused ptrs_per_pte(struct kvm_vm *vm) { return 1 << (vm->page_shift - 3); } void virt_arch_pgd_alloc(struct kvm_vm *vm) { size_t nr_pages = vm_page_align(vm, ptrs_per_pgd(vm) * 8) / vm->page_size; if (vm->mmu.pgd_created) return; vm->mmu.pgd = vm_phy_pages_alloc(vm, nr_pages, KVM_GUEST_PAGE_TABLE_MIN_PADDR, vm->memslots[MEM_REGION_PT]); vm->mmu.pgd_created = true; } static void _virt_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa, u64 flags) { u8 attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT); u64 pg_attr; u64 *ptep; TEST_ASSERT((gva % vm->page_size) == 0, "Virtual address not on page boundary,\n" " gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size); TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)), "Invalid virtual address, gva: 0x%lx", gva); TEST_ASSERT((gpa % vm->page_size) == 0, "Physical address not on page boundary,\n" " gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size); TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn, "Physical address beyond beyond maximum supported,\n" " gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x", gpa, vm->max_gfn, vm->page_size); ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PGD_TYPE_TABLE | PTE_VALID); switch (vm->mmu.pgtable_levels) { case 4: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PUD_TYPE_TABLE | PTE_VALID); /* fall through */ case 3: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; if (!*ptep) *ptep = addr_pte(vm, vm_alloc_page_table(vm), PMD_TYPE_TABLE | PTE_VALID); /* fall through */ case 2: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; break; default: TEST_FAIL("Page table levels must be 2, 3, or 4"); } pg_attr = PTE_AF | PTE_ATTRINDX(attr_idx) | PTE_TYPE_PAGE | PTE_VALID; if (!use_lpa2_pte_format(vm)) pg_attr |= PTE_SHARED; *ptep = addr_pte(vm, gpa, pg_attr); } void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa) { u64 attr_idx = MT_NORMAL; _virt_pg_map(vm, gva, gpa, attr_idx); } u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level) { u64 *ptep; if (!vm->mmu.pgd_created) goto unmapped_gva; ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; if (level == 0) return ptep; switch (vm->mmu.pgtable_levels) { case 4: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; if (level == 1) break; /* fall through */ case 3: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; if (level == 2) break; /* fall through */ case 2: ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8; if (!ptep) goto unmapped_gva; break; default: TEST_FAIL("Page table levels must be 2, 3, or 4"); } return ptep; unmapped_gva: TEST_FAIL("No mapping for vm virtual address, gva: 0x%lx", gva); exit(EXIT_FAILURE); } u64 *virt_get_pte_hva(struct kvm_vm *vm, gva_t gva) { return virt_get_pte_hva_at_level(vm, gva, 3); } gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva) { u64 *ptep = virt_get_pte_hva(vm, gva); return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1)); } static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, u64 page, int level) { #ifdef DEBUG static const char * const type[] = { "", "pud", "pmd", "pte" }; u64 pte, *ptep; if (level == 4) return; for (pte = page; pte < page + ptrs_per_pte(vm) * 8; pte += 8) { ptep = addr_gpa2hva(vm, pte); if (!*ptep) continue; fprintf(stream, "%*s%s: %lx: %lx at %p\n", indent, "", type[level], pte, *ptep, ptep); pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level + 1); } #endif } void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent) { int level = 4 - (vm->mmu.pgtable_levels - 1); u64 pgd, *ptep; if (!vm->mmu.pgd_created) return; for (pgd = vm->mmu.pgd; pgd < vm->mmu.pgd + ptrs_per_pgd(vm) * 8; pgd += 8) { ptep = addr_gpa2hva(vm, pgd); if (!*ptep) continue; fprintf(stream, "%*spgd: %lx: %lx at %p\n", indent, "", pgd, *ptep, ptep); pte_dump(stream, vm, indent + 1, pte_addr(vm, *ptep), level); } } bool vm_supports_el2(struct kvm_vm *vm) { const char *value = getenv("NV"); if (value && *value == '0') return false; return vm_check_cap(vm, KVM_CAP_ARM_EL2) && vm->arch.has_gic; } void kvm_get_default_vcpu_target(struct kvm_vm *vm, struct kvm_vcpu_init *init) { struct kvm_vcpu_init preferred = {}; vm_ioctl(vm, KVM_ARM_PREFERRED_TARGET, &preferred); if (vm_supports_el2(vm)) preferred.features[0] |= BIT(KVM_ARM_VCPU_HAS_EL2); *init = preferred; } void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init) { struct kvm_vcpu_init default_init = { .target = -1, }; struct kvm_vm *vm = vcpu->vm; u64 sctlr_el1, tcr_el1, ttbr0_el1; if (!init) { kvm_get_default_vcpu_target(vm, &default_init); init = &default_init; } vcpu_ioctl(vcpu, KVM_ARM_VCPU_INIT, init); vcpu->init = *init; /* * Enable FP/ASIMD to avoid trapping when accessing Q0-Q15 * registers, which the variable argument list macros do. */ vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_CPACR_EL1), 3 << 20); sctlr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1)); tcr_el1 = vcpu_get_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1)); /* Configure base granule size */ switch (vm->mode) { case VM_MODE_PXXVYY_4K: TEST_FAIL("AArch64 does not support 4K sized pages " "with ANY-bit physical address ranges"); case VM_MODE_P52V48_64K: case VM_MODE_P48V48_64K: case VM_MODE_P40V48_64K: case VM_MODE_P36V48_64K: tcr_el1 |= TCR_TG0_64K; break; case VM_MODE_P52V48_16K: case VM_MODE_P48V48_16K: case VM_MODE_P40V48_16K: case VM_MODE_P36V48_16K: case VM_MODE_P36V47_16K: tcr_el1 |= TCR_TG0_16K; break; case VM_MODE_P52V48_4K: case VM_MODE_P48V48_4K: case VM_MODE_P40V48_4K: case VM_MODE_P36V48_4K: tcr_el1 |= TCR_TG0_4K; break; default: TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); } ttbr0_el1 = vm->mmu.pgd & GENMASK(47, vm->page_shift); /* Configure output size */ switch (vm->mode) { case VM_MODE_P52V48_4K: case VM_MODE_P52V48_16K: case VM_MODE_P52V48_64K: tcr_el1 |= TCR_IPS_52_BITS; ttbr0_el1 |= FIELD_GET(GENMASK(51, 48), vm->mmu.pgd) << 2; break; case VM_MODE_P48V48_4K: case VM_MODE_P48V48_16K: case VM_MODE_P48V48_64K: tcr_el1 |= TCR_IPS_48_BITS; break; case VM_MODE_P40V48_4K: case VM_MODE_P40V48_16K: case VM_MODE_P40V48_64K: tcr_el1 |= TCR_IPS_40_BITS; break; case VM_MODE_P36V48_4K: case VM_MODE_P36V48_16K: case VM_MODE_P36V48_64K: case VM_MODE_P36V47_16K: tcr_el1 |= TCR_IPS_36_BITS; break; default: TEST_FAIL("Unknown guest mode, mode: 0x%x", vm->mode); } sctlr_el1 |= SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_I; tcr_el1 |= TCR_IRGN0_WBWA | TCR_ORGN0_WBWA | TCR_SH0_INNER; tcr_el1 |= TCR_T0SZ(vm->va_bits); tcr_el1 |= TCR_TBI1; tcr_el1 |= TCR_EPD1_MASK; if (use_lpa2_pte_format(vm)) tcr_el1 |= TCR_DS; vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SCTLR_EL1), sctlr_el1); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TCR_EL1), tcr_el1); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_MAIR_EL1), DEFAULT_MAIR_EL1); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_TTBR0_EL1), ttbr0_el1); vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TPIDR_EL1), vcpu->id); if (!vcpu_has_el2(vcpu)) return; vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_HCR_EL2), HCR_EL2_RW | HCR_EL2_TGE | HCR_EL2_E2H); } void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent) { u64 pstate, pc; pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate)); pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc)); fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n", indent, "", pstate, pc); } void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code) { vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code); } static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init) { size_t stack_size; gva_t stack_gva; struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id); stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size : vm->page_size; stack_gva = __vm_alloc(vm, stack_size, DEFAULT_ARM64_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA); aarch64_vcpu_setup(vcpu, init); vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_gva + stack_size); return vcpu; } struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id, struct kvm_vcpu_init *init, void *guest_code) { struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init); vcpu_arch_set_entry_point(vcpu, guest_code); return vcpu; } struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id) { return __aarch64_vcpu_add(vm, vcpu_id, NULL); } void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...) { va_list ap; int i; TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n" " num: %u", num); va_start(ap, num); for (i = 0; i < num; i++) { vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]), va_arg(ap, u64)); } va_end(ap); } void kvm_exit_unexpected_exception(int vector, u64 ec, bool valid_ec) { ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec); while (1) ; } void assert_on_unhandled_exception(struct kvm_vcpu *vcpu) { struct ucall uc; if (get_ucall(vcpu, &uc) != UCALL_UNHANDLED) return; if (uc.args[2]) /* valid_ec */ { assert(VECTOR_IS_SYNC(uc.args[0])); TEST_FAIL("Unexpected exception (vector:0x%lx, ec:0x%lx)", uc.args[0], uc.args[1]); } else { assert(!VECTOR_IS_SYNC(uc.args[0])); TEST_FAIL("Unexpected exception (vector:0x%lx)", uc.args[0]); } } struct handlers { handler_fn exception_handlers[VECTOR_NUM][ESR_ELx_EC_MAX + 1]; }; void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu) { extern char vectors; vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (u64)&vectors);