// SPDX-License-Identifier: GPL-2.0-only/* * Contains CPU specific errata definitions * * Copyright (C) 2014 ARM Ltd. */ #include <linux/arm-smccc.h>#include <linux/types.h>#include <linux/cpu.h>#include <asm/cpu.h>#include <asm/cputype.h>#include <asm/cpufeature.h>#include <asm/fpsimd.h>#include <asm/kvm_asm.h>#include <asm/smp_plat.h> static u64 target_impl_cpu_num;static struct target_impl_cpu *target_impl_cpus; bool cpu_errata_set_target_impl(u64 num, void *impl_cpus){	if (target_impl_cpu_num || !num || !impl_cpus)		return false; 	target_impl_cpu_num = num;	target_impl_cpus = impl_cpus;	return true;} static inline bool is_midr_in_range(struct midr_range const *range){	int i; 	if (!target_impl_cpu_num)		return midr_is_cpu_model_range(read_cpuid_id(), range->model,					       range->rv_min, range->rv_max); 	for (i = 0; i < target_impl_cpu_num; i++) {		if (midr_is_cpu_model_range(target_impl_cpus[i].midr,					    range->model,					    range->rv_min, range->rv_max))			return true;	}	return false;} bool is_midr_in_range_list(struct midr_range const *ranges){	while (ranges->model)		if (is_midr_in_range(ranges++))			return true;	return false;}EXPORT_SYMBOL_GPL(is_midr_in_range_list); static bool __maybe_unused__is_affected_midr_range(const struct arm64_cpu_capabilities *entry,			 u32 midr, u32 revidr){	const struct arm64_midr_revidr *fix;	if (!is_midr_in_range(&entry->midr_range))		return false; 	midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))			return false;	return true;} static bool __maybe_unusedis_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope){	int i; 	if (!target_impl_cpu_num) {		WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());		return __is_affected_midr_range(entry, read_cpuid_id(),						read_cpuid(REVIDR_EL1));	} 	for (i = 0; i < target_impl_cpu_num; i++) {		if (__is_affected_midr_range(entry, target_impl_cpus[i].midr,					     target_impl_cpus[i].revidr))			return true;	}	return false;} static bool __maybe_unusedis_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,			    int scope){	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());	return is_midr_in_range_list(entry->midr_range_list);} static bool __maybe_unusedis_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope){	u32 model; 	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 	model = read_cpuid_id();	model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |		 MIDR_ARCHITECTURE_MASK; 	return model == entry->midr_range.model;} static boolhas_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,			  int scope){	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;	u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;	u64 ctr_raw, ctr_real; 	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 	/*	 * We want to make sure that all the CPUs in the system expose	 * a consistent CTR_EL0 to make sure that applications behaves	 * correctly with migration.	 *	 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :	 *	 * 1) It is safe if the system doesn't support IDC, as CPU anyway	 *    reports IDC = 0, consistent with the rest.	 *	 * 2) If the system has IDC, it is still safe as we trap CTR_EL0	 *    access on this CPU via the ARM64_HAS_CACHE_IDC capability.	 *	 * So, we need to make sure either the raw CTR_EL0 or the effective	 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.	 */	ctr_raw = read_cpuid_cachetype() & mask;	ctr_real = read_cpuid_effective_cachetype() & mask; 	return (ctr_real != sys) && (ctr_raw != sys);} #ifdef CONFIG_ARM64_ERRATUM_4311569static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569);static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg){	static_branch_enable(&arm_si_l1_workaround_4311569);	pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n"); 	return 0;}early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg); /* * We have some earlier use cases to call cache maintenance operation functions, for example, * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its * safe to have the workaround off by default. */static boolneed_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope){	return static_branch_unlikely(&arm_si_l1_workaround_4311569);}#endif static voidcpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap){	u64 mask = arm64_ftr_reg_ctrel0.strict_mask;	bool enable_uct_trap = false; 	/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */	if ((read_cpuid_cachetype() & mask) !=	    (arm64_ftr_reg_ctrel0.sys_val & mask))		enable_uct_trap = true; 	/* ... or if the system is affected by an erratum */	if (cap->capability == ARM64_WORKAROUND_1542419)		enable_uct_trap = true; 	if (enable_uct_trap)		sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);} #ifdef CONFIG_ARM64_ERRATUM_1463225static boolhas_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,			       int scope){	return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();}#endif static void __maybe_unusedcpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused){	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);} #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)	\	.matches = is_affected_midr_range,			\	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) #define CAP_MIDR_ALL_VERSIONS(model)					\	.matches = is_affected_midr_range,				\	.midr_range = MIDR_ALL_VERSIONS(model) #define MIDR_FIXED(rev, revidr_mask) \	.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)		\	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,				\	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) #define CAP_MIDR_RANGE_LIST(list)				\	.matches = is_affected_midr_range_list,			\	.midr_range_list = list /* Errata affecting a range of revisions of  given model variant */#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)	 \	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) /* Errata affecting a single variant/revision of a model */#define ERRATA_MIDR_REV(model, var, rev)	\	ERRATA_MIDR_RANGE(model, var, rev, var, rev) /* Errata affecting all variants/revisions of a given a model */#define ERRATA_MIDR_ALL_VERSIONS(model)				\	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\	CAP_MIDR_ALL_VERSIONS(model) /* Errata affecting a list of midr ranges, with same work around */#define ERRATA_MIDR_RANGE_LIST(midr_list)			\	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\	CAP_MIDR_RANGE_LIST(midr_list) static const __maybe_unused struct midr_range tx2_family_cpus[] = {	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),	{},}; static bool __maybe_unusedneeds_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,			 int scope){	int i; 	if (!is_affected_midr_range_list(entry, scope) ||	    !is_hyp_mode_available())		return false; 	for_each_possible_cpu(i) {		if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)			return true;	} 	return false;} static bool __maybe_unusedhas_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,				int scope){	bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT);	const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());	return is_midr_in_range(&range) && has_dic;} static const struct midr_range apple_cpus[] = {	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM),	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM),	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO),	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO),	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX),	MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX),	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD),	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE),	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO),	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO),	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX),	MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX),	{},}; static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope){	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);	unsigned int pmuver; 	if (!is_kernel_in_hyp_mode())		return false; 	pmuver = cpuid_feature_extract_unsigned_field(dfr0,						      ID_AA64DFR0_EL1_PMUVer_SHIFT);	if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF)		return false; 	return is_midr_in_range_list(apple_cpus);} static bool has_broken_gic_v3_seis(const struct arm64_cpu_capabilities *entry, int scope){	return (is_kernel_in_hyp_mode() &&		is_midr_in_range_list(apple_cpus) &&		(read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS));} static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused){	sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56));} #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNCstatic const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009	{		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)	},	{		.midr_range.model = MIDR_QCOM_KRYO,		.matches = is_kryo_midr,	},#endif#ifdef CONFIG_ARM64_ERRATUM_1286807	{		ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),	},	{		/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */		ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),	},#endif#ifdef CONFIG_ARM64_ERRATUM_2441007	{		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),	},#endif#ifdef CONFIG_ARM64_ERRATUM_2441009	{		/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */		ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),	},#endif#ifdef CONFIG_ARM64_ERRATUM_4118414	{		ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) {			MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM),			MIDR_ALL_VERSIONS(MIDR_C1_ULTRA),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),			MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),			MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),			MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),			MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),			MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),			MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),			MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),			MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),			MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),			MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),			{}		})),	},#endif	{}};#endif #ifdef CONFIG_CAVIUM_ERRATUM_23154static const struct midr_range cavium_erratum_23154_cpus[] = {	MIDR_ALL_VERSIONS(MIDR_THUNDERX),	MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX),	MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX),	MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX),	MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX),	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX),	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN),	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM),	MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO),	{},};#endif #ifdef CONFIG_CAVIUM_ERRATUM_27456static const struct midr_range cavium_erratum_27456_cpus[] = {	/* Cavium ThunderX, T88 pass 1.x - 2.1 */	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),	/* Cavium ThunderX, T81 pass 1.0 */	MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),	{},};#endif #ifdef CONFIG_CAVIUM_ERRATUM_30115static const struct midr_range cavium_erratum_30115_cpus[] = {	/* Cavium ThunderX, T88 pass 1.x - 2.2 */	MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */	MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),	/* Cavium ThunderX, T83 pass 1.0 */	MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),	{},};#endif #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {	{		ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),	},	{		.midr_range.model = MIDR_QCOM_KRYO,		.matches = is_kryo_midr,	},	{},};#endif #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHEstatic const struct midr_range workaround_clean_cache[] = {#if	defined(CONFIG_ARM64_ERRATUM_826319) || \	defined(CONFIG_ARM64_ERRATUM_827319) || \	defined(CONFIG_ARM64_ERRATUM_824069)	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),#endif#ifdef	CONFIG_ARM64_ERRATUM_819472	/* Cortex-A53 r0p[01] : ARM errata 819472 */	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),#endif	{},};#endif #ifdef CONFIG_ARM64_ERRATUM_1418040/* * - 1188873 affects r0p0 to r2p0 * - 1418040 affects r0p0 to r3p1 */static const struct midr_range erratum_1418040_list[] = {	/* Cortex-A76 r0p0 to r3p1 */	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),	/* Neoverse-N1 r0p0 to r3p1 */	MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),	/* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */	MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),	{},};#endif #ifdef CONFIG_ARM64_ERRATUM_845719static const struct midr_range erratum_845719_list[] = {	/* Cortex-A53 r0p[01234] */	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),	/* Brahma-B53 r0p[0] */	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),	/* Kryo2XX Silver rAp4 */	MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),	{},};#endif #ifdef CONFIG_ARM64_ERRATUM_843419static const struct arm64_cpu_capabilities erratum_843419_list[] = {	{		/* Cortex-A53 r0p[01234] */		.matches = is_affected_midr_range,		ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),		MIDR_FIXED(0x4, BIT(8)),	},	{		/* Brahma-B53 r0p[0] */		.matches = is_affected_midr_range,		ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),	},	{},};#endif #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_ATstatic const struct midr_range erratum_speculative_at_list[] = {#ifdef CONFIG_ARM64_ERRATUM_1165522	/* Cortex A76 r0p0 to r2p0 */	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),#endif

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