// SPDX-License-Identifier: GPL-2.0-only/* * EMIF driver * * Copyright (C) 2012 Texas Instruments, Inc. * * Aneesh V <aneesh@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com> */#include <linux/cleanup.h>#include <linux/err.h>#include <linux/kernel.h>#include <linux/reboot.h>#include <linux/platform_data/emif_plat.h>#include <linux/io.h>#include <linux/device.h>#include <linux/platform_device.h>#include <linux/interrupt.h>#include <linux/slab.h>#include <linux/of.h>#include <linux/debugfs.h>#include <linux/seq_file.h>#include <linux/module.h>#include <linux/list.h>#include <linux/spinlock.h>#include <linux/pm.h> #include "emif.h"#include "jedec_ddr.h"#include "of_memory.h" /** * struct emif_data - Per device static data for driver's use * @duplicate:			Whether the DDR devices attached to this EMIF *				instance are exactly same as that on EMIF1. In *				this case we can save some memory and processing * @temperature_level:		Maximum temperature of LPDDR2 devices attached *				to this EMIF - read from MR4 register. If there *				are two devices attached to this EMIF, this *				value is the maximum of the two temperature *				levels. * @lpmode:			Chosen low power mode * @node:			node in the device list * @base:			base address of memory-mapped IO registers. * @dev:			device pointer. * @regs_cache:			An array of 'struct emif_regs' that stores *				calculated register values for different *				frequencies, to avoid re-calculating them on *				each DVFS transition. * @curr_regs:			The set of register values used in the last *				frequency change (i.e. corresponding to the *				frequency in effect at the moment) * @plat_data:			Pointer to saved platform data. * @debugfs_root:		dentry to the root folder for EMIF in debugfs * @np_ddr:			Pointer to ddr device tree node */struct emif_data {	u8				duplicate;	u8				temperature_level;	u8				lpmode;	struct list_head		node;	void __iomem			*base;	struct device			*dev;	struct emif_regs		*regs_cache[EMIF_MAX_NUM_FREQUENCIES];	struct emif_regs		*curr_regs;	struct emif_platform_data	*plat_data;	struct dentry			*debugfs_root;	struct device_node		*np_ddr;}; static struct emif_data *emif1;static DEFINE_SPINLOCK(emif_lock);static LIST_HEAD(device_list); static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,	struct emif_regs *regs){	u32 type = emif->plat_data->device_info->type;	u32 ip_rev = emif->plat_data->ip_rev; 	seq_printf(s, "EMIF register cache dump for %dMHz\n",		regs->freq/1000000); 	seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);	seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);	seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);	seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw); 	if (ip_rev == EMIF_4D) {		seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",			regs->read_idle_ctrl_shdw_normal);		seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",			regs->read_idle_ctrl_shdw_volt_ramp);	} else if (ip_rev == EMIF_4D5) {		seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",			regs->dll_calib_ctrl_shdw_normal);		seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",			regs->dll_calib_ctrl_shdw_volt_ramp);	} 	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {		seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",			regs->ref_ctrl_shdw_derated);		seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",			regs->sdram_tim1_shdw_derated);		seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",			regs->sdram_tim3_shdw_derated);	}} static int emif_regdump_show(struct seq_file *s, void *unused){	struct emif_data	*emif	= s->private;	struct emif_regs	**regs_cache;	int			i; 	if (emif->duplicate)		regs_cache = emif1->regs_cache;	else		regs_cache = emif->regs_cache; 	for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {		do_emif_regdump_show(s, emif, regs_cache[i]);		seq_putc(s, '\n');	} 	return 0;} DEFINE_SHOW_ATTRIBUTE(emif_regdump); static int emif_mr4_show(struct seq_file *s, void *unused){	struct emif_data *emif = s->private; 	seq_printf(s, "MR4=%d\n", emif->temperature_level);	return 0;} DEFINE_SHOW_ATTRIBUTE(emif_mr4); static void emif_debugfs_init(struct emif_data *emif){	if (IS_ENABLED(CONFIG_DEBUG_FS)) {		emif->debugfs_root = debugfs_create_dir(dev_name(emif->dev), NULL);		debugfs_create_file("regcache_dump", S_IRUGO, emif->debugfs_root, emif,				    &emif_regdump_fops);		debugfs_create_file("mr4", S_IRUGO, emif->debugfs_root, emif,				    &emif_mr4_fops);	}} static void emif_debugfs_exit(struct emif_data *emif){	if (IS_ENABLED(CONFIG_DEBUG_FS)) {		debugfs_remove_recursive(emif->debugfs_root);		emif->debugfs_root = NULL;	}} /* * Get bus width used by EMIF. Note that this may be different from the * bus width of the DDR devices used. For instance two 16-bit DDR devices * may be connected to a given CS of EMIF. In this case bus width as far * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. */static u32 get_emif_bus_width(struct emif_data *emif){	u32		width;	void __iomem	*base = emif->base; 	width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)			>> NARROW_MODE_SHIFT;	width = width == 0 ? 32 : 16; 	return width;} static void set_lpmode(struct emif_data *emif, u8 lpmode){	u32 temp;	void __iomem *base = emif->base; 	/*	 * Workaround for errata i743 - LPDDR2 Power-Down State is Not	 * Efficient	 *	 * i743 DESCRIPTION:	 * The EMIF supports power-down state for low power. The EMIF	 * automatically puts the SDRAM into power-down after the memory is	 * not accessed for a defined number of cycles and the	 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.	 * As the EMIF supports automatic output impedance calibration, a ZQ	 * calibration long command is issued every time it exits active	 * power-down and precharge power-down modes. The EMIF waits and	 * blocks any other command during this calibration.	 * The EMIF does not allow selective disabling of ZQ calibration upon	 * exit of power-down mode. Due to very short periods of power-down	 * cycles, ZQ calibration overhead creates bandwidth issues and	 * increases overall system power consumption. On the other hand,	 * issuing ZQ calibration long commands when exiting self-refresh is	 * still required.	 *	 * WORKAROUND	 * Because there is no power consumption benefit of the power-down due	 * to the calibration and there is a performance risk, the guideline	 * is to not allow power-down state and, therefore, to not have set	 * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.	 */	if ((emif->plat_data->ip_rev == EMIF_4D) &&	    (lpmode == EMIF_LP_MODE_PWR_DN)) {		WARN_ONCE(1,			  "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");		/* rollback LP_MODE to Self-refresh mode */		lpmode = EMIF_LP_MODE_SELF_REFRESH;	} 	temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);	temp &= ~LP_MODE_MASK;	temp |= (lpmode << LP_MODE_SHIFT);	writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);} static void do_freq_update(void){	struct emif_data *emif; 	/*	 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE	 *	 * i728 DESCRIPTION:	 * The EMIF automatically puts the SDRAM into self-refresh mode	 * after the EMIF has not performed accesses during	 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles	 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set	 * to 0x2. If during a small window the following three events	 * occur:	 * - The SR_TIMING counter expires	 * - And frequency change is requested	 * - And OCP access is requested	 * Then it causes instable clock on the DDR interface.	 *	 * WORKAROUND	 * To avoid the occurrence of the three events, the workaround	 * is to disable the self-refresh when requesting a frequency	 * change. Before requesting a frequency change the software must	 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the	 * frequency change has been done, the software can reprogram	 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2	 */	list_for_each_entry(emif, &device_list, node) {		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)			set_lpmode(emif, EMIF_LP_MODE_DISABLE);	} 	/*	 * TODO: Do FREQ_UPDATE here when an API	 * is available for this as part of the new	 * clock framework	 */ 	list_for_each_entry(emif, &device_list, node) {		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)			set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);	}} /* Find addressing table entry based on the device's type and density */static const struct lpddr2_addressing *get_addressing_table(	const struct ddr_device_info *device_info){	u32		index, type, density; 	type = device_info->type;	density = device_info->density; 	switch (type) {	case DDR_TYPE_LPDDR2_S4:		index = density - 1;		break;	case DDR_TYPE_LPDDR2_S2:		switch (density) {		case DDR_DENSITY_1Gb:		case DDR_DENSITY_2Gb:			index = density + 3;			break;		default:			index = density - 1;		}		break;	default:		return NULL;	} 	return &lpddr2_jedec_addressing_table[index];} static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,		bool cs1_used, bool cal_resistors_per_cs){	u32 zq = 0, val = 0; 	val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;	zq |= val << ZQ_REFINTERVAL_SHIFT; 	val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;	zq |= val << ZQ_ZQCL_MULT_SHIFT; 	val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;	zq |= val << ZQ_ZQINIT_MULT_SHIFT; 	zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; 	if (cal_resistors_per_cs)		zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;	else		zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; 	zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ 	val = cs1_used ? 1 : 0;	zq |= val << ZQ_CS1EN_SHIFT; 	return zq;} static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,		const struct emif_custom_configs *custom_configs, bool cs1_used,		u32 sdram_io_width, u32 emif_bus_width){	u32 alert = 0, interval, devcnt; 	if (custom_configs && (custom_configs->mask &				EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))		interval = custom_configs->temp_alert_poll_interval_ms;	else		interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS; 	interval *= 1000000;			/* Convert to ns */	interval /= addressing->tREFI_ns;	/* Convert to refresh cycles */	alert |= (interval << TA_REFINTERVAL_SHIFT); 	/*	 * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width	 * also to this form and subtract to get TA_DEVCNT, which is	 * in log2(x) form.	 */	emif_bus_width = __fls(emif_bus_width) - 1;	devcnt = emif_bus_width - sdram_io_width;	alert |= devcnt << TA_DEVCNT_SHIFT; 	/* DEVWDT is in 'log2(x) - 3' form */	alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT; 	alert |= 1 << TA_SFEXITEN_SHIFT;	alert |= 1 << TA_CS0EN_SHIFT;	alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT; 	return alert;} static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev){	u32 pwr_mgmt_ctrl	= 0, timeout;	u32 lpmode		= EMIF_LP_MODE_SELF_REFRESH;	u32 timeout_perf	= EMIF_LP_MODE_TIMEOUT_PERFORMANCE;	u32 timeout_pwr		= EMIF_LP_MODE_TIMEOUT_POWER;	u32 freq_threshold	= EMIF_LP_MODE_FREQ_THRESHOLD;	u32 mask;	u8 shift; 	struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs; 	if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {		lpmode		= cust_cfgs->lpmode;		timeout_perf	= cust_cfgs->lpmode_timeout_performance;		timeout_pwr	= cust_cfgs->lpmode_timeout_power;		freq_threshold  = cust_cfgs->lpmode_freq_threshold;	} 	/* Timeout based on DDR frequency */	timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr; 	/*	 * The value to be set in register is "log2(timeout) - 3"	 * if timeout < 16 load 0 in register	 * if timeout is not a power of 2, round to next highest power of 2	 */	if (timeout < 16) {		timeout = 0;	} else {		if (timeout & (timeout - 1))			timeout <<= 1;		timeout = __fls(timeout) - 3;	} 	switch (lpmode) {	case EMIF_LP_MODE_CLOCK_STOP:		shift = CS_TIM_SHIFT;		mask = CS_TIM_MASK;		break;	case EMIF_LP_MODE_SELF_REFRESH:		/* Workaround for errata i735 */		if (timeout < 6)			timeout = 6; 		shift = SR_TIM_SHIFT;		mask = SR_TIM_MASK;		break;	case EMIF_LP_MODE_PWR_DN:		shift = PD_TIM_SHIFT;		mask = PD_TIM_MASK;		break;	case EMIF_LP_MODE_DISABLE:	default:		mask = 0;		shift = 0;		break;	}	/* Round to maximum in case of overflow, BUT warn! */	if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {		pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",		       lpmode,		       timeout_perf,		       timeout_pwr,		       freq_threshold);		WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",		     timeout, mask >> shift);		timeout = mask >> shift;	} 	/* Setup required timing */	pwr_mgmt_ctrl = (timeout << shift) & mask;	/* setup a default mask for rest of the modes */	pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &			  ~mask; 	/* No CS_TIM in EMIF_4D5 */	if (ip_rev == EMIF_4D5)		pwr_mgmt_ctrl &= ~CS_TIM_MASK; 	pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT; 	return pwr_mgmt_ctrl;} /* * Get the temperature level of the EMIF instance: * Reads the MR4 register of attached SDRAM parts to find out the temperature * level. If there are two parts attached(one on each CS), then the temperature * level for the EMIF instance is the higher of the two temperatures. */static void get_temperature_level(struct emif_data *emif){	u32		temp, temperature_level;	void __iomem	*base; 	base = emif->base; 	/* Read mode register 4 */	writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);	temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);	temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>				MR4_SDRAM_REF_RATE_SHIFT; 	if (emif->plat_data->device_info->cs1_used) {		writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);		temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);		temp = (temp & MR4_SDRAM_REF_RATE_MASK)				>> MR4_SDRAM_REF_RATE_SHIFT;		temperature_level = max(temp, temperature_level);	} 	/* treat everything less than nominal(3) in MR4 as nominal */	if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))		temperature_level = SDRAM_TEMP_NOMINAL; 	/* if we get reserved value in MR4 persist with the existing value */	if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))		emif->temperature_level = temperature_level;} /* * setup_temperature_sensitive_regs() - set the timings for temperature * sensitive registers. This happens once at initialisation time based * on the temperature at boot time and subsequently based on the temperature * alert interrupt. Temperature alert can happen when the temperature * increases or drops. So this function can have the effect of either * derating the timings or going back to nominal values. */static void setup_temperature_sensitive_regs(struct emif_data *emif,		struct emif_regs *regs){	u32		tim1, tim3, ref_ctrl, type;	void __iomem	*base = emif->base;	u32		temperature; 	type = emif->plat_data->device_info->type; 	tim1 = regs->sdram_tim1_shdw;

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