/* SPDX-License-Identifier: GPL-2.0 */// Copyright (C) 2025 Arm Ltd. #ifndef MPAM_INTERNAL_H#define MPAM_INTERNAL_H #include <linux/arm_mpam.h>#include <linux/atomic.h>#include <linux/bitmap.h>#include <linux/cpumask.h>#include <linux/io.h>#include <linux/jump_label.h>#include <linux/llist.h>#include <linux/mutex.h>#include <linux/resctrl.h>#include <linux/spinlock.h>#include <linux/srcu.h>#include <linux/types.h> #include <asm/mpam.h> #define MPAM_MSC_MAX_NUM_RIS 16 struct platform_device; #ifdef CONFIG_MPAM_KUNIT_TEST#define PACKED_FOR_KUNIT __packed#else#define PACKED_FOR_KUNIT#endif /* * This 'mon' values must not alias an actual monitor, so must be larger than * U16_MAX, but not be confused with an errno value, so smaller than * (u32)-SZ_4K. * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor. */#define USE_PRE_ALLOCATED (U16_MAX + 1) static inline bool mpam_is_enabled(void){ return static_branch_likely(&mpam_enabled);} /* * Structures protected by SRCU may not be freed for a surprising amount of * time (especially if perf is running). To ensure the MPAM error interrupt can * tear down all the structures, build a list of objects that can be garbage * collected once synchronize_srcu() has returned. * If pdev is non-NULL, use devm_kfree(). */struct mpam_garbage { /* member of mpam_garbage */ struct llist_node llist; void *to_free; struct platform_device *pdev;}; struct mpam_msc { /* member of mpam_all_msc */ struct list_head all_msc_list; int id; struct platform_device *pdev; /* Not modified after mpam_is_enabled() becomes true */ enum mpam_msc_iface iface; u32 nrdy_usec; cpumask_t accessibility; bool has_extd_esr; int reenable_error_ppi; struct mpam_msc * __percpu *error_dev_id; atomic_t online_refs; /* * probe_lock is only taken during discovery. After discovery these * properties become read-only and the lists are protected by SRCU. */ struct mutex probe_lock; bool probed; u16 partid_max; u8 pmg_max; unsigned long ris_idxs; u32 ris_max; u32 iidr; u16 quirks; /* * error_irq_lock is taken when registering/unregistering the error * interrupt and maniupulating the below flags. */ struct mutex error_irq_lock; bool error_irq_req; bool error_irq_hw_enabled; /* mpam_msc_ris of this component */ struct list_head ris; /* * part_sel_lock protects access to the MSC hardware registers that are * affected by MPAMCFG_PART_SEL. (including the ID registers that vary * by RIS). * If needed, take msc->probe_lock first. */ struct mutex part_sel_lock; /* * cfg_lock protects the msc configuration and guards against mbwu_state * save and restore racing. */ struct mutex cfg_lock; /* * mon_sel_lock protects access to the MSC hardware registers that are * affected by MPAMCFG_MON_SEL, and the mbwu_state. * Access to mon_sel is needed from both process and interrupt contexts, * but is complicated by firmware-backed platforms that can't make any * access unless they can sleep. * Always use the mpam_mon_sel_lock() helpers. * Accesses to mon_sel need to be able to fail if they occur in the wrong * context. * If needed, take msc->probe_lock first. */ raw_spinlock_t _mon_sel_lock; unsigned long _mon_sel_flags; void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; /* Values only used on some platforms for quirks */ u32 t241_id; struct mpam_garbage garbage;}; /* Returning false here means accesses to mon_sel must fail and report an error. */static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc){ /* Locking will require updating to support a firmware backed interface */ if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) return false; raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); return true;} static inline void mpam_mon_sel_unlock(struct mpam_msc *msc){ raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags);} static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc){ lockdep_assert_held_once(&msc->_mon_sel_lock);} static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc){ raw_spin_lock_init(&msc->_mon_sel_lock);} /* Bits for mpam features bitmaps */enum mpam_device_features { mpam_feat_cpor_part, mpam_feat_cmax_softlim, mpam_feat_cmax_cmax, mpam_feat_cmax_cmin, mpam_feat_cmax_cassoc, mpam_feat_mbw_part, mpam_feat_mbw_min, mpam_feat_mbw_max, mpam_feat_mbw_prop, mpam_feat_intpri_part, mpam_feat_intpri_part_0_low, mpam_feat_dspri_part, mpam_feat_dspri_part_0_low, mpam_feat_msmon, mpam_feat_msmon_csu, mpam_feat_msmon_csu_capture, mpam_feat_msmon_csu_xcl, mpam_feat_msmon_mbwu, mpam_feat_msmon_mbwu_31counter, mpam_feat_msmon_mbwu_44counter, mpam_feat_msmon_mbwu_63counter, mpam_feat_msmon_mbwu_capture, mpam_feat_msmon_mbwu_rwbw, mpam_feat_partid_nrw, MPAM_FEATURE_LAST}; struct mpam_props { DECLARE_BITMAP(features, MPAM_FEATURE_LAST); u16 cpbm_wd; u16 mbw_pbm_bits; u16 bwa_wd; u16 cmax_wd; u16 cassoc_wd; u16 intpri_wd; u16 dspri_wd; u16 num_csu_mon; u16 num_mbwu_mon; /* * Kunit tests use memset() to set up feature combinations that should be * removed, and will false-positive if the compiler introduces padding that * isn't cleared during sanitisation. */} PACKED_FOR_KUNIT; #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features)/* * The non-atomic get/set operations are used because if struct mpam_props is * packed, the alignment requirements for atomics aren't met. */#define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features)#define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features) /* Workaround bits for msc->quirks */enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, T241_FORCE_MBW_MIN_TO_ONE, T241_MBW_COUNTER_SCALE_64, IGNORE_CSU_NRDY, MPAM_QUIRK_LAST}; #define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks))#define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk))) struct mpam_quirk { int (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk); u32 iidr; u32 iidr_mask; enum mpam_device_quirks workaround;}; #define MPAM_IIDR_MATCH_ONE (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff) | \ FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf) | \ FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff)) #define MPAM_IIDR_NVIDIA_T241 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0x241) | \ FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b)) #define MPAM_IIDR_ARM_CMN_650 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b)) /* The values for MSMON_CFG_MBWU_FLT.RWBW */enum mon_filter_options { COUNT_BOTH = 0, COUNT_WRITE = 1, COUNT_READ = 2,}; struct mon_cfg { /* * mon must be large enough to hold out of range values like * USE_PRE_ALLOCATED */ u32 mon; u8 pmg; bool match_pmg; bool csu_exclude_clean; u32 partid; enum mon_filter_options opts;}; /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */struct msmon_mbwu_state { bool enabled; bool reset_on_next_read; struct mon_cfg cfg; /* * The value to add to the new reading to account for power management, * and overflow. */ u64 correction; struct mpam_garbage garbage;}; struct mpam_class { /* mpam_components in this class */ struct list_head components; cpumask_t affinity; struct mpam_props props; u32 nrdy_usec; u16 quirks; u8 level; enum mpam_class_types type; /* member of mpam_classes */ struct list_head classes_list; struct ida ida_csu_mon; struct ida ida_mbwu_mon; struct mpam_garbage garbage;}; struct mpam_config { /* Which configuration values are valid. */ DECLARE_BITMAP(features, MPAM_FEATURE_LAST); u32 cpbm; u32 mbw_pbm; u16 mbw_max; struct mpam_garbage garbage;}; struct mpam_component { u32 comp_id; /* mpam_vmsc in this component */ struct list_head vmsc; cpumask_t affinity; /* * Array of configuration values, indexed by partid. * Read from cpuhp callbacks, hold the cpuhp lock when writing. */ struct mpam_config *cfg; /* member of mpam_class:components */ struct list_head class_list; /* parent: */ struct mpam_class *class; struct mpam_garbage garbage;}; struct mpam_vmsc { /* member of mpam_component:vmsc_list */ struct list_head comp_list; /* mpam_msc_ris in this vmsc */ struct list_head ris; struct mpam_props props; /* All RIS in this vMSC are members of this MSC */ struct mpam_msc *msc; /* parent: */ struct mpam_component *comp; struct mpam_garbage garbage;}; struct mpam_msc_ris { u8 ris_idx; u64 idr; struct mpam_props props; bool in_reset_state; cpumask_t affinity; /* member of mpam_vmsc:ris */ struct list_head vmsc_list; /* member of mpam_msc:ris */ struct list_head msc_list; /* parent: */ struct mpam_vmsc *vmsc; /* msmon mbwu configuration is preserved over reset */ struct msmon_mbwu_state *mbwu_state; struct mpam_garbage garbage;}; struct mpam_resctrl_dom { struct mpam_component *ctrl_comp; /* * There is no single mon_comp because different events may be backed * by different class/components. mon_comp is indexed by the event * number. */ struct mpam_component *mon_comp[QOS_NUM_EVENTS]; struct rdt_ctrl_domain resctrl_ctrl_dom; struct rdt_l3_mon_domain resctrl_mon_dom;}; struct mpam_resctrl_res { struct mpam_class *class; struct rdt_resource resctrl_res; bool cdp_enabled;}; struct mpam_resctrl_mon { struct mpam_class *class; /* Array of allocated MBWU monitors, indexed by (closid, rmid). */ int *mbwu_idx_to_mon; /* Array of assigned MBWU monitors, indexed by resctrl's cntr_id. */ int *assigned_counters;}; static inline int mpam_alloc_csu_mon(struct mpam_class *class){ struct mpam_props *cprops = &class->props; if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) return -EOPNOTSUPP; return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, GFP_KERNEL);} static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon){ ida_free(&class->ida_csu_mon, csu_mon);} static inline int mpam_alloc_mbwu_mon(struct mpam_class *class){ struct mpam_props *cprops = &class->props; if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) return -EOPNOTSUPP; return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, GFP_KERNEL);} static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon){ ida_free(&class->ida_mbwu_mon, mbwu_mon);} /* List of all classes - protected by srcu*/extern struct srcu_struct mpam_srcu;extern struct list_head mpam_classes; /* System wide partid/pmg values */extern u16 mpam_partid_max;extern u8 mpam_pmg_max; /* Scheduled work callback to enable mpam once all MSC have been probed */void mpam_enable(struct work_struct *work);void mpam_disable(struct work_struct *work); /* Reset all the RIS in a class under cpus_read_lock() */void mpam_reset_class_locked(struct mpam_class *class); int mpam_apply_config(struct mpam_component *comp, u16 partid, struct mpam_config *cfg); int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, enum mpam_device_features, u64 *val);void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx); int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); #ifdef CONFIG_RESCTRL_FSint mpam_resctrl_setup(void);void mpam_resctrl_exit(void);int mpam_resctrl_online_cpu(unsigned int cpu);void mpam_resctrl_offline_cpu(unsigned int cpu);void mpam_resctrl_teardown_class(struct mpam_class *class);#elsestatic inline int mpam_resctrl_setup(void) { return 0; }static inline void mpam_resctrl_exit(void) { }static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; }static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { }static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { }#endif /* CONFIG_RESCTRL_FS */ /* * MPAM MSCs have the following register layout. See: * Arm Memory System Resource Partitioning and Monitoring (MPAM) System * Component Specification. * https://developer.arm.com/documentation/ihi0099/aa/ */#define MPAM_ARCHITECTURE_V1 0x10 /* Memory mapped control pages *//* ID Register offsets in the memory mapped page */#define MPAMF_IDR 0x0000 /* features id register */Lines 1–500 of 757. Load more
/* SPDX-License-Identifier: GPL-2.0 */ // Copyright (C) 2025 Arm Ltd. #ifndef MPAM_INTERNAL_H #define MPAM_INTERNAL_H #include <linux/arm_mpam.h> #include <linux/atomic.h> #include <linux/bitmap.h> #include <linux/cpumask.h> #include <linux/io.h> #include <linux/jump_label.h> #include <linux/llist.h> #include <linux/mutex.h> #include <linux/resctrl.h> #include <linux/spinlock.h> #include <linux/srcu.h> #include <linux/types.h> #include <asm/mpam.h> #define MPAM_MSC_MAX_NUM_RIS 16 struct platform_device; #ifdef CONFIG_MPAM_KUNIT_TEST #define PACKED_FOR_KUNIT __packed #else #define PACKED_FOR_KUNIT #endif /* * This 'mon' values must not alias an actual monitor, so must be larger than * U16_MAX, but not be confused with an errno value, so smaller than * (u32)-SZ_4K. * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor. */ #define USE_PRE_ALLOCATED (U16_MAX + 1) static inline bool mpam_is_enabled(void) { return static_branch_likely(&mpam_enabled); } /* * Structures protected by SRCU may not be freed for a surprising amount of * time (especially if perf is running). To ensure the MPAM error interrupt can * tear down all the structures, build a list of objects that can be garbage * collected once synchronize_srcu() has returned. * If pdev is non-NULL, use devm_kfree(). */ struct mpam_garbage { /* member of mpam_garbage */ struct llist_node llist; void *to_free; struct platform_device *pdev; }; struct mpam_msc { /* member of mpam_all_msc */ struct list_head all_msc_list; int id; struct platform_device *pdev; /* Not modified after mpam_is_enabled() becomes true */ enum mpam_msc_iface iface; u32 nrdy_usec; cpumask_t accessibility; bool has_extd_esr; int reenable_error_ppi; struct mpam_msc * __percpu *error_dev_id; atomic_t online_refs; /* * probe_lock is only taken during discovery. After discovery these * properties become read-only and the lists are protected by SRCU. */ struct mutex probe_lock; bool probed; u16 partid_max; u8 pmg_max; unsigned long ris_idxs; u32 ris_max; u32 iidr; u16 quirks; /* * error_irq_lock is taken when registering/unregistering the error * interrupt and maniupulating the below flags. */ struct mutex error_irq_lock; bool error_irq_req; bool error_irq_hw_enabled; /* mpam_msc_ris of this component */ struct list_head ris; /* * part_sel_lock protects access to the MSC hardware registers that are * affected by MPAMCFG_PART_SEL. (including the ID registers that vary * by RIS). * If needed, take msc->probe_lock first. */ struct mutex part_sel_lock; /* * cfg_lock protects the msc configuration and guards against mbwu_state * save and restore racing. */ struct mutex cfg_lock; /* * mon_sel_lock protects access to the MSC hardware registers that are * affected by MPAMCFG_MON_SEL, and the mbwu_state. * Access to mon_sel is needed from both process and interrupt contexts, * but is complicated by firmware-backed platforms that can't make any * access unless they can sleep. * Always use the mpam_mon_sel_lock() helpers. * Accesses to mon_sel need to be able to fail if they occur in the wrong * context. * If needed, take msc->probe_lock first. */ raw_spinlock_t _mon_sel_lock; unsigned long _mon_sel_flags; void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; /* Values only used on some platforms for quirks */ u32 t241_id; struct mpam_garbage garbage; }; /* Returning false here means accesses to mon_sel must fail and report an error. */ static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) { /* Locking will require updating to support a firmware backed interface */ if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO)) return false; raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); return true; } static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) { raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); } static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) { lockdep_assert_held_once(&msc->_mon_sel_lock); } static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) { raw_spin_lock_init(&msc->_mon_sel_lock); } /* Bits for mpam features bitmaps */ enum mpam_device_features { mpam_feat_cpor_part, mpam_feat_cmax_softlim, mpam_feat_cmax_cmax, mpam_feat_cmax_cmin, mpam_feat_cmax_cassoc, mpam_feat_mbw_part, mpam_feat_mbw_min, mpam_feat_mbw_max, mpam_feat_mbw_prop, mpam_feat_intpri_part, mpam_feat_intpri_part_0_low, mpam_feat_dspri_part, mpam_feat_dspri_part_0_low, mpam_feat_msmon, mpam_feat_msmon_csu, mpam_feat_msmon_csu_capture, mpam_feat_msmon_csu_xcl, mpam_feat_msmon_mbwu, mpam_feat_msmon_mbwu_31counter, mpam_feat_msmon_mbwu_44counter, mpam_feat_msmon_mbwu_63counter, mpam_feat_msmon_mbwu_capture, mpam_feat_msmon_mbwu_rwbw, mpam_feat_partid_nrw, MPAM_FEATURE_LAST }; struct mpam_props { DECLARE_BITMAP(features, MPAM_FEATURE_LAST); u16 cpbm_wd; u16 mbw_pbm_bits; u16 bwa_wd; u16 cmax_wd; u16 cassoc_wd; u16 intpri_wd; u16 dspri_wd; u16 num_csu_mon; u16 num_mbwu_mon; /* * Kunit tests use memset() to set up feature combinations that should be * removed, and will false-positive if the compiler introduces padding that * isn't cleared during sanitisation. */ } PACKED_FOR_KUNIT; #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features) /* * The non-atomic get/set operations are used because if struct mpam_props is * packed, the alignment requirements for atomics aren't met. */ #define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features) #define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features) /* Workaround bits for msc->quirks */ enum mpam_device_quirks { T241_SCRUB_SHADOW_REGS, T241_FORCE_MBW_MIN_TO_ONE, T241_MBW_COUNTER_SCALE_64, IGNORE_CSU_NRDY, MPAM_QUIRK_LAST }; #define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks)) #define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk))) struct mpam_quirk { int (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk); u32 iidr; u32 iidr_mask; enum mpam_device_quirks workaround; }; #define MPAM_IIDR_MATCH_ONE (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff) | \ FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf) | \ FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff)) #define MPAM_IIDR_NVIDIA_T241 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0x241) | \ FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b)) #define MPAM_IIDR_ARM_CMN_650 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \ FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b)) /* The values for MSMON_CFG_MBWU_FLT.RWBW */ enum mon_filter_options { COUNT_BOTH = 0, COUNT_WRITE = 1, COUNT_READ = 2, }; struct mon_cfg { /* * mon must be large enough to hold out of range values like * USE_PRE_ALLOCATED */ u32 mon; u8 pmg; bool match_pmg; bool csu_exclude_clean; u32 partid; enum mon_filter_options opts; }; /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */ struct msmon_mbwu_state { bool enabled; bool reset_on_next_read; struct mon_cfg cfg; /* * The value to add to the new reading to account for power management, * and overflow. */ u64 correction; struct mpam_garbage garbage; }; struct mpam_class { /* mpam_components in this class */ struct list_head components; cpumask_t affinity; struct mpam_props props; u32 nrdy_usec; u16 quirks; u8 level; enum mpam_class_types type; /* member of mpam_classes */ struct list_head classes_list; struct ida ida_csu_mon; struct ida ida_mbwu_mon; struct mpam_garbage garbage; }; struct mpam_config { /* Which configuration values are valid. */ DECLARE_BITMAP(features, MPAM_FEATURE_LAST); u32 cpbm; u32 mbw_pbm; u16 mbw_max; struct mpam_garbage garbage; }; struct mpam_component { u32 comp_id; /* mpam_vmsc in this component */ struct list_head vmsc; cpumask_t affinity; /* * Array of configuration values, indexed by partid. * Read from cpuhp callbacks, hold the cpuhp lock when writing. */ struct mpam_config *cfg; /* member of mpam_class:components */ struct list_head class_list; /* parent: */ struct mpam_class *class; struct mpam_garbage garbage; }; struct mpam_vmsc { /* member of mpam_component:vmsc_list */ struct list_head comp_list; /* mpam_msc_ris in this vmsc */ struct list_head ris; struct mpam_props props; /* All RIS in this vMSC are members of this MSC */ struct mpam_msc *msc; /* parent: */ struct mpam_component *comp; struct mpam_garbage garbage; }; struct mpam_msc_ris { u8 ris_idx; u64 idr; struct mpam_props props; bool in_reset_state; cpumask_t affinity; /* member of mpam_vmsc:ris */ struct list_head vmsc_list; /* member of mpam_msc:ris */ struct list_head msc_list; /* parent: */ struct mpam_vmsc *vmsc; /* msmon mbwu configuration is preserved over reset */ struct msmon_mbwu_state *mbwu_state; struct mpam_garbage garbage; }; struct mpam_resctrl_dom { struct mpam_component *ctrl_comp; /* * There is no single mon_comp because different events may be backed * by different class/components. mon_comp is indexed by the event * number. */ struct mpam_component *mon_comp[QOS_NUM_EVENTS]; struct rdt_ctrl_domain resctrl_ctrl_dom; struct rdt_l3_mon_domain resctrl_mon_dom; }; struct mpam_resctrl_res { struct mpam_class *class; struct rdt_resource resctrl_res; bool cdp_enabled; }; struct mpam_resctrl_mon { struct mpam_class *class; /* Array of allocated MBWU monitors, indexed by (closid, rmid). */ int *mbwu_idx_to_mon; /* Array of assigned MBWU monitors, indexed by resctrl's cntr_id. */ int *assigned_counters; }; static inline int mpam_alloc_csu_mon(struct mpam_class *class) { struct mpam_props *cprops = &class->props; if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) return -EOPNOTSUPP; return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1, GFP_KERNEL); } static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) { ida_free(&class->ida_csu_mon, csu_mon); } static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) { struct mpam_props *cprops = &class->props; if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) return -EOPNOTSUPP; return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1, GFP_KERNEL); } static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon) { ida_free(&class->ida_mbwu_mon, mbwu_mon); } /* List of all classes - protected by srcu*/ extern struct srcu_struct mpam_srcu; extern struct list_head mpam_classes; /* System wide partid/pmg values */ extern u16 mpam_partid_max; extern u8 mpam_pmg_max; /* Scheduled work callback to enable mpam once all MSC have been probed */ void mpam_enable(struct work_struct *work); void mpam_disable(struct work_struct *work); /* Reset all the RIS in a class under cpus_read_lock() */ void mpam_reset_class_locked(struct mpam_class *class); int mpam_apply_config(struct mpam_component *comp, u16 partid, struct mpam_config *cfg); int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, enum mpam_device_features, u64 *val); void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx); int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); #ifdef CONFIG_RESCTRL_FS int mpam_resctrl_setup(void); void mpam_resctrl_exit(void); int mpam_resctrl_online_cpu(unsigned int cpu); void mpam_resctrl_offline_cpu(unsigned int cpu); void mpam_resctrl_teardown_class(struct mpam_class *class); #else static inline int mpam_resctrl_setup(void) { return 0; } static inline void mpam_resctrl_exit(void) { } static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; } static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { } static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { } #endif /* CONFIG_RESCTRL_FS */ /* * MPAM MSCs have the following register layout. See: * Arm Memory System Resource Partitioning and Monitoring (MPAM) System * Component Specification. * https://developer.arm.com/documentation/ihi0099/aa/ */ #define MPAM_ARCHITECTURE_V1 0x10 /* Memory mapped control pages */ /* ID Register offsets in the memory mapped page */ #define MPAMF_IDR 0x0000 /* features id register */