/* * This file contains miscellaneous low-level functions. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) * and Paul Mackerras. * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com) * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * */ #include <linux/sys.h>#include <asm/unistd.h>#include <asm/errno.h>#include <asm/processor.h>#include <asm/page.h>#include <asm/cache.h>#include <asm/ppc_asm.h>#include <asm/asm-offsets.h>#include <asm/cputable.h>#include <asm/thread_info.h> .text _GLOBAL(get_msr) mfmsr r3 blr _GLOBAL(get_srr0) mfsrr0 r3 blr _GLOBAL(get_srr1) mfsrr1 r3 blr #ifdef CONFIG_IRQSTACKS_GLOBAL(call_do_softirq) mflr r0 std r0,16(r1) stdu r1,THREAD_SIZE-112(r3) mr r1,r3 bl .__do_softirq ld r1,0(r1) ld r0,16(r1) mtlr r0 blr _GLOBAL(call_handle_irq) ld r8,0(r6) mflr r0 std r0,16(r1) mtctr r8 stdu r1,THREAD_SIZE-112(r5) mr r1,r5 bctrl ld r1,0(r1) ld r0,16(r1) mtlr r0 blr#endif /* CONFIG_IRQSTACKS */ .section ".toc","aw"PPC64_CACHES: .tc ppc64_caches[TC],ppc64_caches .section ".text" /* * Write any modified data cache blocks out to memory * and invalidate the corresponding instruction cache blocks. * * flush_icache_range(unsigned long start, unsigned long stop) * * flush all bytes from start through stop-1 inclusive */ _KPROBE(__flush_icache_range) /* * Flush the data cache to memory * * Different systems have different cache line sizes * and in some cases i-cache and d-cache line sizes differ from * each other. */ ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r81: dcbst 0,r6 add r6,r6,r7 bdnz 1b sync /* Now invalidate the instruction cache */ lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r82: icbi 0,r6 add r6,r6,r7 bdnz 2b isync blr .previous .text/* * Like above, but only do the D-cache. * * flush_dcache_range(unsigned long start, unsigned long stop) * * flush all bytes from start to stop-1 inclusive */_GLOBAL(flush_dcache_range) /* * Flush the data cache to memory * * Different systems have different cache line sizes */ ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r80: dcbst 0,r6 add r6,r6,r7 bdnz 0b sync blr /* * Like above, but works on non-mapped physical addresses. * Use only for non-LPAR setups ! It also assumes real mode * is cacheable. Used for flushing out the DART before using * it as uncacheable memory * * flush_dcache_phys_range(unsigned long start, unsigned long stop) * * flush all bytes from start to stop-1 inclusive */_GLOBAL(flush_dcache_phys_range) ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mfmsr r5 /* Disable MMU Data Relocation */ ori r0,r5,MSR_DR xori r0,r0,MSR_DR sync mtmsr r0 sync isync mtctr r80: dcbst 0,r6 add r6,r6,r7 bdnz 0b sync isync mtmsr r5 /* Re-enable MMU Data Relocation */ sync isync blr _GLOBAL(flush_inval_dcache_range) ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ sync isync mtctr r80: dcbf 0,r6 add r6,r6,r7 bdnz 0b sync isync blr /* * Flush a particular page from the data cache to RAM. * Note: this is necessary because the instruction cache does *not* * snoop from the data cache. * * void __flush_dcache_icache(void *page) */_GLOBAL(__flush_dcache_icache)/* * Flush the data cache to memory * * Different systems have different cache line sizes */ /* Flush the dcache */ ld r7,PPC64_CACHES@toc(r2) clrrdi r3,r3,PAGE_SHIFT /* Page align */ lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */ lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */ mr r6,r3 mtctr r40: dcbst 0,r6 add r6,r6,r5 bdnz 0b sync /* Now invalidate the icache */ lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */ lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */ mtctr r41: icbi 0,r3 add r3,r3,r5 bdnz 1b isync blr #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)/* * Do an IO access in real mode */_GLOBAL(real_readb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync mfspr r6,SPRN_HID4 rldicl r5,r6,32,0 ori r5,r5,0x100 rldicl r5,r5,32,0 sync mtspr SPRN_HID4,r5 isync slbia isync lbz r3,0(r3) sync mtspr SPRN_HID4,r6 isync slbia isync mtmsrd r7 sync isync blr /* * Do an IO access in real mode */_GLOBAL(real_writeb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync mfspr r6,SPRN_HID4 rldicl r5,r6,32,0 ori r5,r5,0x100 rldicl r5,r5,32,0 sync mtspr SPRN_HID4,r5 isync slbia isync stb r3,0(r4) sync mtspr SPRN_HID4,r6 isync slbia isync mtmsrd r7 sync isync blr#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */ #ifdef CONFIG_PPC_PASEMI /* No support in all binutils for these yet, so use defines */#define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))#define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11)) _GLOBAL(real_205_readb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync LBZCIX(r3,0,r3) isync mtmsrd r7 sync isync blr _GLOBAL(real_205_writeb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync STBCIX(r3,0,r4) isync mtmsrd r7 sync isync blr #endif /* CONFIG_PPC_PASEMI */ #ifdef CONFIG_CPU_FREQ_PMAC64/* * SCOM access functions for 970 (FX only for now) * * unsigned long scom970_read(unsigned int address); * void scom970_write(unsigned int address, unsigned long value); * * The address passed in is the 24 bits register address. This code * is 970 specific and will not check the status bits, so you should * know what you are doing. */_GLOBAL(scom970_read) /* interrupts off */ mfmsr r4 ori r0,r4,MSR_EE xori r0,r0,MSR_EE mtmsrd r0,1 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits * (including parity). On current CPUs they must be 0'd, * and finally or in RW bit */ rlwinm r3,r3,8,0,15 ori r3,r3,0x8000 /* do the actual scom read */ sync mtspr SPRN_SCOMC,r3 isync mfspr r3,SPRN_SCOMD isync mfspr r0,SPRN_SCOMC isync /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah * that's the best we can do). Not implemented yet as we don't use * the scom on any of the bogus CPUs yet, but may have to be done * ultimately */ /* restore interrupts */ mtmsrd r4,1 blr _GLOBAL(scom970_write) /* interrupts off */ mfmsr r5 ori r0,r5,MSR_EE xori r0,r0,MSR_EE mtmsrd r0,1 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits * (including parity). On current CPUs they must be 0'd. */ rlwinm r3,r3,8,0,15 sync mtspr SPRN_SCOMD,r4 /* write data */ isync mtspr SPRN_SCOMC,r3 /* write command */ isync mfspr 3,SPRN_SCOMC isync /* restore interrupts */ mtmsrd r5,1 blr#endif /* CONFIG_CPU_FREQ_PMAC64 */ /* * Create a kernel thread * kernel_thread(fn, arg, flags) */_GLOBAL(kernel_thread) std r29,-24(r1) std r30,-16(r1) stdu r1,-STACK_FRAME_OVERHEAD(r1) mr r29,r3 mr r30,r4 ori r3,r5,CLONE_VM /* flags */ oris r3,r3,(CLONE_UNTRACED>>16) li r4,0 /* new sp (unused) */ li r0,__NR_clone sc cmpdi 0,r3,0 /* parent or child? */ bne 1f /* return if parent */ li r0,0 stdu r0,-STACK_FRAME_OVERHEAD(r1) ld r2,8(r29) ld r29,0(r29) mtlr r29 /* fn addr in lr */ mr r3,r30 /* load arg and call fn */ blrl li r0,__NR_exit /* exit after child exits */ li r3,0 sc1: addi r1,r1,STACK_FRAME_OVERHEAD ld r29,-24(r1) ld r30,-16(r1) blr /* * disable_kernel_fp() * Disable the FPU. */_GLOBAL(disable_kernel_fp) mfmsr r3 rldicl r0,r3,(63-MSR_FP_LG),1 rldicl r3,r0,(MSR_FP_LG+1),0 mtmsrd r3 /* disable use of fpu now */ isync blr #ifdef CONFIG_ALTIVEC #if 0 /* this has no callers for now *//* * disable_kernel_altivec() * Disable the VMX. */_GLOBAL(disable_kernel_altivec) mfmsr r3 rldicl r0,r3,(63-MSR_VEC_LG),1 rldicl r3,r0,(MSR_VEC_LG+1),0 mtmsrd r3 /* disable use of VMX now */ isync blr#endif /* 0 */ /* * giveup_altivec(tsk) * Disable VMX for the task given as the argument, * and save the vector registers in its thread_struct. * Enables the VMX for use in the kernel on return. */_GLOBAL(giveup_altivec) mfmsr r5 oris r5,r5,MSR_VEC@h mtmsrd r5 /* enable use of VMX now */ isync cmpdi 0,r3,0 beqlr- /* if no previous owner, done */ addi r3,r3,THREAD /* want THREAD of task */ ld r5,PT_REGS(r3)Lines 1–500 of 697. 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/* * This file contains miscellaneous low-level functions. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) * and Paul Mackerras. * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com) * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * */ #include <linux/sys.h> #include <asm/unistd.h> #include <asm/errno.h> #include <asm/processor.h> #include <asm/page.h> #include <asm/cache.h> #include <asm/ppc_asm.h> #include <asm/asm-offsets.h> #include <asm/cputable.h> #include <asm/thread_info.h> .text _GLOBAL(get_msr) mfmsr r3 blr _GLOBAL(get_srr0) mfsrr0 r3 blr _GLOBAL(get_srr1) mfsrr1 r3 blr #ifdef CONFIG_IRQSTACKS _GLOBAL(call_do_softirq) mflr r0 std r0,16(r1) stdu r1,THREAD_SIZE-112(r3) mr r1,r3 bl .__do_softirq ld r1,0(r1) ld r0,16(r1) mtlr r0 blr _GLOBAL(call_handle_irq) ld r8,0(r6) mflr r0 std r0,16(r1) mtctr r8 stdu r1,THREAD_SIZE-112(r5) mr r1,r5 bctrl ld r1,0(r1) ld r0,16(r1) mtlr r0 blr #endif /* CONFIG_IRQSTACKS */ .section ".toc","aw" PPC64_CACHES: .tc ppc64_caches[TC],ppc64_caches .section ".text" /* * Write any modified data cache blocks out to memory * and invalidate the corresponding instruction cache blocks. * * flush_icache_range(unsigned long start, unsigned long stop) * * flush all bytes from start through stop-1 inclusive */ _KPROBE(__flush_icache_range) /* * Flush the data cache to memory * * Different systems have different cache line sizes * and in some cases i-cache and d-cache line sizes differ from * each other. */ ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 1: dcbst 0,r6 add r6,r6,r7 bdnz 1b sync /* Now invalidate the instruction cache */ lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 2: icbi 0,r6 add r6,r6,r7 bdnz 2b isync blr .previous .text /* * Like above, but only do the D-cache. * * flush_dcache_range(unsigned long start, unsigned long stop) * * flush all bytes from start to stop-1 inclusive */ _GLOBAL(flush_dcache_range) /* * Flush the data cache to memory * * Different systems have different cache line sizes */ ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mtctr r8 0: dcbst 0,r6 add r6,r6,r7 bdnz 0b sync blr /* * Like above, but works on non-mapped physical addresses. * Use only for non-LPAR setups ! It also assumes real mode * is cacheable. Used for flushing out the DART before using * it as uncacheable memory * * flush_dcache_phys_range(unsigned long start, unsigned long stop) * * flush all bytes from start to stop-1 inclusive */ _GLOBAL(flush_dcache_phys_range) ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ mfmsr r5 /* Disable MMU Data Relocation */ ori r0,r5,MSR_DR xori r0,r0,MSR_DR sync mtmsr r0 sync isync mtctr r8 0: dcbst 0,r6 add r6,r6,r7 bdnz 0b sync isync mtmsr r5 /* Re-enable MMU Data Relocation */ sync isync blr _GLOBAL(flush_inval_dcache_range) ld r10,PPC64_CACHES@toc(r2) lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */ addi r5,r7,-1 andc r6,r3,r5 /* round low to line bdy */ subf r8,r6,r4 /* compute length */ add r8,r8,r5 /* ensure we get enough */ lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */ srw. r8,r8,r9 /* compute line count */ beqlr /* nothing to do? */ sync isync mtctr r8 0: dcbf 0,r6 add r6,r6,r7 bdnz 0b sync isync blr /* * Flush a particular page from the data cache to RAM. * Note: this is necessary because the instruction cache does *not* * snoop from the data cache. * * void __flush_dcache_icache(void *page) */ _GLOBAL(__flush_dcache_icache) /* * Flush the data cache to memory * * Different systems have different cache line sizes */ /* Flush the dcache */ ld r7,PPC64_CACHES@toc(r2) clrrdi r3,r3,PAGE_SHIFT /* Page align */ lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */ lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */ mr r6,r3 mtctr r4 0: dcbst 0,r6 add r6,r6,r5 bdnz 0b sync /* Now invalidate the icache */ lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */ lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */ mtctr r4 1: icbi 0,r3 add r3,r3,r5 bdnz 1b isync blr #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) /* * Do an IO access in real mode */ _GLOBAL(real_readb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync mfspr r6,SPRN_HID4 rldicl r5,r6,32,0 ori r5,r5,0x100 rldicl r5,r5,32,0 sync mtspr SPRN_HID4,r5 isync slbia isync lbz r3,0(r3) sync mtspr SPRN_HID4,r6 isync slbia isync mtmsrd r7 sync isync blr /* * Do an IO access in real mode */ _GLOBAL(real_writeb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync mfspr r6,SPRN_HID4 rldicl r5,r6,32,0 ori r5,r5,0x100 rldicl r5,r5,32,0 sync mtspr SPRN_HID4,r5 isync slbia isync stb r3,0(r4) sync mtspr SPRN_HID4,r6 isync slbia isync mtmsrd r7 sync isync blr #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */ #ifdef CONFIG_PPC_PASEMI /* No support in all binutils for these yet, so use defines */ #define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11)) #define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11)) _GLOBAL(real_205_readb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync LBZCIX(r3,0,r3) isync mtmsrd r7 sync isync blr _GLOBAL(real_205_writeb) mfmsr r7 ori r0,r7,MSR_DR xori r0,r0,MSR_DR sync mtmsrd r0 sync isync STBCIX(r3,0,r4) isync mtmsrd r7 sync isync blr #endif /* CONFIG_PPC_PASEMI */ #ifdef CONFIG_CPU_FREQ_PMAC64 /* * SCOM access functions for 970 (FX only for now) * * unsigned long scom970_read(unsigned int address); * void scom970_write(unsigned int address, unsigned long value); * * The address passed in is the 24 bits register address. This code * is 970 specific and will not check the status bits, so you should * know what you are doing. */ _GLOBAL(scom970_read) /* interrupts off */ mfmsr r4 ori r0,r4,MSR_EE xori r0,r0,MSR_EE mtmsrd r0,1 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits * (including parity). On current CPUs they must be 0'd, * and finally or in RW bit */ rlwinm r3,r3,8,0,15 ori r3,r3,0x8000 /* do the actual scom read */ sync mtspr SPRN_SCOMC,r3 isync mfspr r3,SPRN_SCOMD isync mfspr r0,SPRN_SCOMC isync /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah * that's the best we can do). Not implemented yet as we don't use * the scom on any of the bogus CPUs yet, but may have to be done * ultimately */ /* restore interrupts */ mtmsrd r4,1 blr _GLOBAL(scom970_write) /* interrupts off */ mfmsr r5 ori r0,r5,MSR_EE xori r0,r0,MSR_EE mtmsrd r0,1 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits * (including parity). On current CPUs they must be 0'd. */ rlwinm r3,r3,8,0,15 sync mtspr SPRN_SCOMD,r4 /* write data */ isync mtspr SPRN_SCOMC,r3 /* write command */ isync mfspr 3,SPRN_SCOMC isync /* restore interrupts */ mtmsrd r5,1 blr #endif /* CONFIG_CPU_FREQ_PMAC64 */ /* * Create a kernel thread * kernel_thread(fn, arg, flags) */ _GLOBAL(kernel_thread) std r29,-24(r1) std r30,-16(r1) stdu r1,-STACK_FRAME_OVERHEAD(r1) mr r29,r3 mr r30,r4 ori r3,r5,CLONE_VM /* flags */ oris r3,r3,(CLONE_UNTRACED>>16) li r4,0 /* new sp (unused) */ li r0,__NR_clone sc cmpdi 0,r3,0 /* parent or child? */ bne 1f /* return if parent */ li r0,0 stdu r0,-STACK_FRAME_OVERHEAD(r1) ld r2,8(r29) ld r29,0(r29) mtlr r29 /* fn addr in lr */ mr r3,r30 /* load arg and call fn */ blrl li r0,__NR_exit /* exit after child exits */ li r3,0 sc 1: addi r1,r1,STACK_FRAME_OVERHEAD ld r29,-24(r1) ld r30,-16(r1) blr /* * disable_kernel_fp() * Disable the FPU. */ _GLOBAL(disable_kernel_fp) mfmsr r3 rldicl r0,r3,(63-MSR_FP_LG),1 rldicl r3,r0,(MSR_FP_LG+1),0 mtmsrd r3 /* disable use of fpu now */ isync blr #ifdef CONFIG_ALTIVEC #if 0 /* this has no callers for now */ /* * disable_kernel_altivec() * Disable the VMX. */ _GLOBAL(disable_kernel_altivec) mfmsr r3 rldicl r0,r3,(63-MSR_VEC_LG),1 rldicl r3,r0,(MSR_VEC_LG+1),0 mtmsrd r3 /* disable use of VMX now */ isync blr #endif /* 0 */ /* * giveup_altivec(tsk) * Disable VMX for the task given as the argument, * and save the vector registers in its thread_struct. * Enables the VMX for use in the kernel on return. */ _GLOBAL(giveup_altivec) mfmsr r5 oris r5,r5,MSR_VEC@h mtmsrd r5 /* enable use of VMX now */ isync cmpdi 0,r3,0 beqlr- /* if no previous owner, done */ addi r3,r3,THREAD /* want THREAD of task */ ld r5,PT_REGS(r3)