/* *  Copyright (C) 1997 Geert Uytterhoeven * *  This file is subject to the terms and conditions of the GNU General Public *  License.  See the file COPYING in the main directory of this archive *  for more details. */ #include <linux/types.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/sysdev.h>#include <linux/errno.h>#include <asm/ptrace.h>#include <asm/signal.h>#include <asm/io.h>#include <asm/irq.h>#include <asm/sections.h>#include <asm/open_pic.h>#include <asm/i8259.h>#include <asm/machdep.h> #include "open_pic_defs.h" #if defined(CONFIG_PRPMC800) || defined(CONFIG_85xx)#define OPENPIC_BIG_ENDIAN#endif void __iomem *OpenPIC_Addr;static volatile struct OpenPIC __iomem *OpenPIC = NULL; /* * We define OpenPIC_InitSenses table thusly: * bit 0x1: sense, 0 for edge and 1 for level. * bit 0x2: polarity, 0 for negative, 1 for positive. */u_int OpenPIC_NumInitSenses __initdata = 0;u_char *OpenPIC_InitSenses __initdata = NULL;extern int use_of_interrupt_tree; static u_int NumProcessors;static u_int NumSources;static int open_pic_irq_offset;static volatile OpenPIC_Source __iomem *ISR[NR_IRQS];static int openpic_cascade_irq = -1;static int (*openpic_cascade_fn)(void); /* Global Operations */static void openpic_disable_8259_pass_through(void);static void openpic_set_spurious(u_int vector); #ifdef CONFIG_SMP/* Interprocessor Interrupts */static void openpic_initipi(u_int ipi, u_int pri, u_int vector);static irqreturn_t openpic_ipi_action(int cpl, void *dev_id);#endif /* Timer Interrupts */static void openpic_inittimer(u_int timer, u_int pri, u_int vector);static void openpic_maptimer(u_int timer, cpumask_t cpumask); /* Interrupt Sources */static void openpic_enable_irq(u_int irq);static void openpic_disable_irq(u_int irq);static void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,			    int is_level);static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask); /* * These functions are not used but the code is kept here * for completeness and future reference. */#ifdef notusedstatic void openpic_enable_8259_pass_through(void);static u_int openpic_get_spurious(void);static void openpic_set_sense(u_int irq, int sense);#endif /* notused */ /* * Description of the openpic for the higher-level irq code */static void openpic_end_irq(unsigned int irq_nr);static void openpic_ack_irq(unsigned int irq_nr);static void openpic_set_affinity(unsigned int irq_nr, cpumask_t cpumask); struct hw_interrupt_type open_pic = {	.typename	= " OpenPIC  ",	.enable		= openpic_enable_irq,	.disable	= openpic_disable_irq,	.ack		= openpic_ack_irq,	.end		= openpic_end_irq,	.set_affinity	= openpic_set_affinity,}; #ifdef CONFIG_SMPstatic void openpic_end_ipi(unsigned int irq_nr);static void openpic_ack_ipi(unsigned int irq_nr);static void openpic_enable_ipi(unsigned int irq_nr);static void openpic_disable_ipi(unsigned int irq_nr); struct hw_interrupt_type open_pic_ipi = {	.typename	= " OpenPIC  ",	.enable		= openpic_enable_ipi,	.disable	= openpic_disable_ipi,	.ack		= openpic_ack_ipi,	.end		= openpic_end_ipi,};#endif /* CONFIG_SMP */ /* *  Accesses to the current processor's openpic registers */#ifdef CONFIG_SMP#define THIS_CPU		Processor[cpu]#define DECL_THIS_CPU		int cpu = smp_hw_index[smp_processor_id()]#define CHECK_THIS_CPU		check_arg_cpu(cpu)#else#define THIS_CPU		Processor[0]#define DECL_THIS_CPU#define CHECK_THIS_CPU#endif /* CONFIG_SMP */ #if 1#define check_arg_ipi(ipi) \    if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \	printk("open_pic.c:%d: invalid ipi %d\n", __LINE__, ipi);#define check_arg_timer(timer) \    if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \	printk("open_pic.c:%d: invalid timer %d\n", __LINE__, timer);#define check_arg_vec(vec) \    if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \	printk("open_pic.c:%d: invalid vector %d\n", __LINE__, vec);#define check_arg_pri(pri) \    if (pri < 0 || pri >= OPENPIC_NUM_PRI) \	printk("open_pic.c:%d: invalid priority %d\n", __LINE__, pri);/* * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's * data has probably been corrupted and we're going to panic or deadlock later * anyway --Troy */#define check_arg_irq(irq) \    if (irq < open_pic_irq_offset || irq >= NumSources+open_pic_irq_offset \	|| ISR[irq - open_pic_irq_offset] == 0) { \      printk("open_pic.c:%d: invalid irq %d\n", __LINE__, irq); \      dump_stack(); }#define check_arg_cpu(cpu) \    if (cpu < 0 || cpu >= NumProcessors){ \	printk("open_pic.c:%d: invalid cpu %d\n", __LINE__, cpu); \	dump_stack(); }#else#define check_arg_ipi(ipi)	do {} while (0)#define check_arg_timer(timer)	do {} while (0)#define check_arg_vec(vec)	do {} while (0)#define check_arg_pri(pri)	do {} while (0)#define check_arg_irq(irq)	do {} while (0)#define check_arg_cpu(cpu)	do {} while (0)#endif u_int openpic_read(volatile u_int __iomem *addr){	u_int val; #ifdef OPENPIC_BIG_ENDIAN	val = in_be32(addr);#else	val = in_le32(addr);#endif	return val;} static inline void openpic_write(volatile u_int __iomem *addr, u_int val){#ifdef OPENPIC_BIG_ENDIAN	out_be32(addr, val);#else	out_le32(addr, val);#endif} static inline u_int openpic_readfield(volatile u_int __iomem *addr, u_int mask){	u_int val = openpic_read(addr);	return val & mask;} inline void openpic_writefield(volatile u_int __iomem *addr, u_int mask,			       u_int field){	u_int val = openpic_read(addr);	openpic_write(addr, (val & ~mask) | (field & mask));} static inline void openpic_clearfield(volatile u_int __iomem *addr, u_int mask){	openpic_writefield(addr, mask, 0);} static inline void openpic_setfield(volatile u_int __iomem *addr, u_int mask){	openpic_writefield(addr, mask, mask);} static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,				    u_int field){	openpic_setfield(addr, OPENPIC_MASK);	while (openpic_read(addr) & OPENPIC_ACTIVITY);	openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);} #ifdef CONFIG_SMP/* yes this is right ... bug, feature, you decide! -- tgall */u_int openpic_read_IPI(volatile u_int __iomem * addr){         u_int val = 0;#if defined(OPENPIC_BIG_ENDIAN)        val = in_be32(addr);#else        val = in_le32(addr);#endif        return val;} /* because of the power3 be / le above, this is needed */inline void openpic_writefield_IPI(volatile u_int __iomem * addr, u_int mask, u_int field){        u_int  val = openpic_read_IPI(addr);        openpic_write(addr, (val & ~mask) | (field & mask));} static inline void openpic_clearfield_IPI(volatile u_int __iomem *addr, u_int mask){        openpic_writefield_IPI(addr, mask, 0);} static inline void openpic_setfield_IPI(volatile u_int __iomem *addr, u_int mask){        openpic_writefield_IPI(addr, mask, mask);} static void openpic_safe_writefield_IPI(volatile u_int __iomem *addr, u_int mask, u_int field){        openpic_setfield_IPI(addr, OPENPIC_MASK);         /* wait until it's not in use */        /* BenH: Is this code really enough ? I would rather check the result         *       and eventually retry ...         */        while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);         openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);}#endif /* CONFIG_SMP */ #ifdef CONFIG_EPIC_SERIAL_MODE/* On platforms that may use EPIC serial mode, the default is enabled. */int epic_serial_mode = 1; static void __init openpic_eicr_set_clk(u_int clkval){	openpic_writefield(&OpenPIC->Global.Global_Configuration1,			OPENPIC_EICR_S_CLK_MASK, (clkval << 28));} static void __init openpic_enable_sie(void){	openpic_setfield(&OpenPIC->Global.Global_Configuration1,			OPENPIC_EICR_SIE);}#endif #if defined(CONFIG_EPIC_SERIAL_MODE)static void openpic_reset(void){	openpic_setfield(&OpenPIC->Global.Global_Configuration0,			 OPENPIC_CONFIG_RESET);	while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,				 OPENPIC_CONFIG_RESET))		mb();}#endif void __init openpic_set_sources(int first_irq, int num_irqs, void __iomem *first_ISR){	volatile OpenPIC_Source __iomem *src = first_ISR;	int i, last_irq; 	last_irq = first_irq + num_irqs;	if (last_irq > NumSources)		NumSources = last_irq;	if (src == 0)		src = &((struct OpenPIC __iomem *)OpenPIC_Addr)->Source[first_irq];	for (i = first_irq; i < last_irq; ++i, ++src)		ISR[i] = src;} /* * The `offset' parameter defines where the interrupts handled by the * OpenPIC start in the space of interrupt numbers that the kernel knows * about.  In other words, the OpenPIC's IRQ0 is numbered `offset' in the * kernel's interrupt numbering scheme. * We assume there is only one OpenPIC. */void __init openpic_init(int offset){	u_int t, i;	u_int timerfreq;	const char *version; 	if (!OpenPIC_Addr) {		printk("No OpenPIC found !\n");		return;	}	OpenPIC = (volatile struct OpenPIC __iomem *)OpenPIC_Addr; #ifdef CONFIG_EPIC_SERIAL_MODE	/* Have to start from ground zero.	*/	openpic_reset();#endif 	if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122); 	t = openpic_read(&OpenPIC->Global.Feature_Reporting0);	switch (t & OPENPIC_FEATURE_VERSION_MASK) {	case 1:		version = "1.0";		break;	case 2:		version = "1.2";		break;	case 3:		version = "1.3";		break;	default:		version = "?";		break;	}	NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>			 OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;	if (NumSources == 0)		openpic_set_sources(0,				    ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>				     OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,				    NULL);	printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",	       version, NumProcessors, NumSources, OpenPIC);	timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);	if (timerfreq)		printk("OpenPIC timer frequency is %d.%06d MHz\n",		       timerfreq / 1000000, timerfreq % 1000000); 	open_pic_irq_offset = offset; 	/* Initialize timer interrupts */	if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);	for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {		/* Disabled, Priority 0 */		openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);		/* No processor */		openpic_maptimer(i, CPU_MASK_NONE);	} #ifdef CONFIG_SMP	/* Initialize IPI interrupts */	if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);	for (i = 0; i < OPENPIC_NUM_IPI; i++) {		/* Disabled, increased priorities 10..13 */		openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,				OPENPIC_VEC_IPI+i+offset);		/* IPIs are per-CPU */		irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;		irq_desc[OPENPIC_VEC_IPI+i+offset].chip = &open_pic_ipi;	}#endif 	/* Initialize external interrupts */	if (ppc_md.progress) ppc_md.progress("openpic: external",0x3bc); 	openpic_set_priority(0xf); 	/* Init all external sources, including possibly the cascade. */	for (i = 0; i < NumSources; i++) {		int sense; 		if (ISR[i] == 0)			continue; 		/* the bootloader may have left it enabled (bad !) */		openpic_disable_irq(i+offset); 		sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \				(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE); 		if (sense & IRQ_SENSE_MASK)			irq_desc[i+offset].status = IRQ_LEVEL; 		/* Enabled, Default priority */		openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,				(sense & IRQ_POLARITY_MASK),				(sense & IRQ_SENSE_MASK));		/* Processor 0 */		openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);	} 	/* Init descriptors */	for (i = offset; i < NumSources + offset; i++)		irq_desc[i].chip = &open_pic; 	/* Initialize the spurious interrupt */	if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);	openpic_set_spurious(OPENPIC_VEC_SPURIOUS);	openpic_disable_8259_pass_through();#ifdef CONFIG_EPIC_SERIAL_MODE	if (epic_serial_mode) {		openpic_eicr_set_clk(7);	/* Slowest value until we know better */		openpic_enable_sie();	}#endif	openpic_set_priority(0); 	if (ppc_md.progress) ppc_md.progress("openpic: exit",0x222);} #ifdef notusedstatic void openpic_enable_8259_pass_through(void){	openpic_clearfield(&OpenPIC->Global.Global_Configuration0,			   OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);}#endif /* notused */ static void openpic_disable_8259_pass_through(void){	openpic_setfield(&OpenPIC->Global.Global_Configuration0,			 OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);} /* *  Find out the current interrupt */u_int openpic_irq(void){	u_int vec;	DECL_THIS_CPU; 	CHECK_THIS_CPU;	vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,				OPENPIC_VECTOR_MASK);	return vec;} void openpic_eoi(void){	DECL_THIS_CPU; 	CHECK_THIS_CPU;	openpic_write(&OpenPIC->THIS_CPU.EOI, 0);	/* Handle PCI write posting */	(void)openpic_read(&OpenPIC->THIS_CPU.EOI);} u_int openpic_get_priority(void){	DECL_THIS_CPU; 	CHECK_THIS_CPU;	return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,				 OPENPIC_CURRENT_TASK_PRIORITY_MASK);} void openpic_set_priority(u_int pri){	DECL_THIS_CPU; 	CHECK_THIS_CPU;	check_arg_pri(pri);	openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,			   OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);} /* *  Get/set the spurious vector */#ifdef notusedstatic u_int openpic_get_spurious(void){	return openpic_readfield(&OpenPIC->Global.Spurious_Vector,				 OPENPIC_VECTOR_MASK);}#endif /* notused */ static void openpic_set_spurious(u_int vec){	check_arg_vec(vec);	openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,			   vec);}

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