/* *  arch/s390/kernel/entry.S *    S390 low-level entry points. * *    Copyright (C) IBM Corp. 1999,2006 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com), *		 Hartmut Penner (hp@de.ibm.com), *		 Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com), *		 Heiko Carstens <heiko.carstens@de.ibm.com> */ #include <linux/sys.h>#include <linux/linkage.h>#include <asm/cache.h>#include <asm/lowcore.h>#include <asm/errno.h>#include <asm/ptrace.h>#include <asm/thread_info.h>#include <asm/asm-offsets.h>#include <asm/unistd.h>#include <asm/page.h> /* * Stack layout for the system_call stack entry. * The first few entries are identical to the user_regs_struct. */SP_PTREGS    =	STACK_FRAME_OVERHEADSP_ARGS      =	STACK_FRAME_OVERHEAD + __PT_ARGSSP_PSW	     =	STACK_FRAME_OVERHEAD + __PT_PSWSP_R0	     =	STACK_FRAME_OVERHEAD + __PT_GPRSSP_R1	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 4SP_R2	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 8SP_R3	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 12SP_R4	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 16SP_R5	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 20SP_R6	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 24SP_R7	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 28SP_R8	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 32SP_R9	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 36SP_R10	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 40SP_R11	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 44SP_R12	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 48SP_R13	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 52SP_R14	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 56SP_R15	     =	STACK_FRAME_OVERHEAD + __PT_GPRS + 60SP_ORIG_R2   =	STACK_FRAME_OVERHEAD + __PT_ORIG_GPR2SP_ILC	     =	STACK_FRAME_OVERHEAD + __PT_ILCSP_TRAP      =	STACK_FRAME_OVERHEAD + __PT_TRAPSP_SIZE      =	STACK_FRAME_OVERHEAD + __PT_SIZE _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \		 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )_TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NEED_RESCHED | \		 _TIF_MCCK_PENDING) STACK_SHIFT = PAGE_SHIFT + THREAD_ORDERSTACK_SIZE  = 1 << STACK_SHIFT #define BASED(name) name-system_call(%r13) #ifdef CONFIG_TRACE_IRQFLAGS	.macro	TRACE_IRQS_ON	l	%r1,BASED(.Ltrace_irq_on)	basr	%r14,%r1	.endm 	.macro	TRACE_IRQS_OFF	l	%r1,BASED(.Ltrace_irq_off)	basr	%r14,%r1	.endm#else#define TRACE_IRQS_ON#define TRACE_IRQS_OFF#endif /* * Register usage in interrupt handlers: *    R9  - pointer to current task structure *    R13 - pointer to literal pool *    R14 - return register for function calls *    R15 - kernel stack pointer */ 	.macro	STORE_TIMER lc_offset#ifdef CONFIG_VIRT_CPU_ACCOUNTING	stpt	\lc_offset#endif	.endm #ifdef CONFIG_VIRT_CPU_ACCOUNTING	.macro	UPDATE_VTIME lc_from,lc_to,lc_sum	lm	%r10,%r11,\lc_from	sl	%r10,\lc_to	sl	%r11,\lc_to+4	bc	3,BASED(0f)	sl	%r10,BASED(.Lc_1)0:	al	%r10,\lc_sum	al	%r11,\lc_sum+4	bc	12,BASED(1f)	al	%r10,BASED(.Lc_1)1:	stm	%r10,%r11,\lc_sum	.endm#endif 	.macro	SAVE_ALL_BASE savearea	stm	%r12,%r15,\savearea	l	%r13,__LC_SVC_NEW_PSW+4	# load &system_call to %r13	.endm 	.macro	SAVE_ALL_SYNC psworg,savearea	la	%r12,\psworg	tm	\psworg+1,0x01		# test problem state bit	bz	BASED(2f)		# skip stack setup save	l	%r15,__LC_KERNEL_STACK	# problem state -> load ksp#ifdef CONFIG_CHECK_STACK	b	BASED(3f)2:	tml	%r15,STACK_SIZE - CONFIG_STACK_GUARD	bz	BASED(stack_overflow)3:#endif2:	.endm 	.macro	SAVE_ALL_ASYNC psworg,savearea	la	%r12,\psworg	tm	\psworg+1,0x01		# test problem state bit	bnz	BASED(1f)		# from user -> load async stack	clc	\psworg+4(4),BASED(.Lcritical_end)	bhe	BASED(0f)	clc	\psworg+4(4),BASED(.Lcritical_start)	bl	BASED(0f)	l	%r14,BASED(.Lcleanup_critical)	basr	%r14,%r14	tm	1(%r12),0x01		# retest problem state after cleanup	bnz	BASED(1f)0:	l	%r14,__LC_ASYNC_STACK	# are we already on the async stack ?	slr	%r14,%r15	sra	%r14,STACK_SHIFT	be	BASED(2f)1:	l	%r15,__LC_ASYNC_STACK#ifdef CONFIG_CHECK_STACK	b	BASED(3f)2:	tml	%r15,STACK_SIZE - CONFIG_STACK_GUARD	bz	BASED(stack_overflow)3:#endif2:	.endm 	.macro	CREATE_STACK_FRAME psworg,savearea	s	%r15,BASED(.Lc_spsize)	# make room for registers & psw	mvc	SP_PSW(8,%r15),0(%r12)	# move user PSW to stack	la	%r12,\psworg	st	%r2,SP_ORIG_R2(%r15)	# store original content of gpr 2	icm	%r12,12,__LC_SVC_ILC	stm	%r0,%r11,SP_R0(%r15)	# store gprs %r0-%r11 to kernel stack	st	%r12,SP_ILC(%r15)	mvc	SP_R12(16,%r15),\savearea # move %r12-%r15 to stack	la	%r12,0	st	%r12,__SF_BACKCHAIN(%r15)	# clear back chain	.endm 	.macro	RESTORE_ALL psworg,sync	mvc	\psworg(8),SP_PSW(%r15) # move user PSW to lowcore	.if !\sync	ni	\psworg+1,0xfd		# clear wait state bit	.endif	lm	%r0,%r15,SP_R0(%r15)	# load gprs 0-15 of user	STORE_TIMER __LC_EXIT_TIMER	lpsw	\psworg			# back to caller	.endm /* * Scheduler resume function, called by switch_to *  gpr2 = (task_struct *) prev *  gpr3 = (task_struct *) next * Returns: *  gpr2 = prev */	.globl	__switch_to__switch_to:	basr	%r1,0__switch_to_base:	tm	__THREAD_per(%r3),0xe8		# new process is using per ?	bz	__switch_to_noper-__switch_to_base(%r1)	# if not we're fine	stctl	%c9,%c11,__SF_EMPTY(%r15)	# We are using per stuff	clc	__THREAD_per(12,%r3),__SF_EMPTY(%r15)	be	__switch_to_noper-__switch_to_base(%r1)	# we got away w/o bashing TLB's	lctl	%c9,%c11,__THREAD_per(%r3)	# Nope we didn't__switch_to_noper:	l	%r4,__THREAD_info(%r2)		# get thread_info of prev	tm	__TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending?	bz	__switch_to_no_mcck-__switch_to_base(%r1)	ni	__TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev	l	%r4,__THREAD_info(%r3)		# get thread_info of next	oi	__TI_flags+3(%r4),_TIF_MCCK_PENDING # set it in next__switch_to_no_mcck:	stm	%r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task	st	%r15,__THREAD_ksp(%r2)	# store kernel stack to prev->tss.ksp	l	%r15,__THREAD_ksp(%r3)	# load kernel stack from next->tss.ksp	lm	%r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task	st	%r3,__LC_CURRENT	# __LC_CURRENT = current task struct	lctl	%c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4	l	%r3,__THREAD_info(%r3)	# load thread_info from task struct	st	%r3,__LC_THREAD_INFO	ahi	%r3,STACK_SIZE	st	%r3,__LC_KERNEL_STACK	# __LC_KERNEL_STACK = new kernel stack	br	%r14 __critical_start:/* * SVC interrupt handler routine. System calls are synchronous events and * are executed with interrupts enabled. */ 	.globl	system_callsystem_call:	STORE_TIMER __LC_SYNC_ENTER_TIMERsysc_saveall:	SAVE_ALL_BASE __LC_SAVE_AREA	SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA	CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA	lh	%r7,0x8a	  # get svc number from lowcore#ifdef CONFIG_VIRT_CPU_ACCOUNTINGsysc_vtime:	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	bz	BASED(sysc_do_svc)	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMERsysc_stime:	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMERsysc_update:	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER#endifsysc_do_svc:	l	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	sla	%r7,2			# *4 and test for svc 0	bnz	BASED(sysc_nr_ok)	# svc number > 0	# svc 0: system call number in %r1	cl	%r1,BASED(.Lnr_syscalls)	bnl	BASED(sysc_nr_ok)	lr	%r7,%r1 	  # copy svc number to %r7	sla	%r7,2		  # *4sysc_nr_ok:	mvc	SP_ARGS(4,%r15),SP_R7(%r15)sysc_do_restart:	l	%r8,BASED(.Lsysc_table)	tm	__TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)	l	%r8,0(%r7,%r8)	  # get system call addr.	bnz	BASED(sysc_tracesys)	basr	%r14,%r8	  # call sys_xxxx	st	%r2,SP_R2(%r15)   # store return value (change R2 on stack)				  # ATTENTION: check sys_execve_glue before				  # changing anything here !! sysc_return:	tm	SP_PSW+1(%r15),0x01	# returning to user ?	bno	BASED(sysc_leave)	tm	__TI_flags+3(%r9),_TIF_WORK_SVC	bnz	BASED(sysc_work)  # there is work to do (signals etc.)sysc_leave:	RESTORE_ALL __LC_RETURN_PSW,1 ## recheck if there is more work to do#sysc_work_loop:	tm	__TI_flags+3(%r9),_TIF_WORK_SVC	bz	BASED(sysc_leave)	# there is no work to do## One of the work bits is on. Find out which one.#sysc_work:	tm	__TI_flags+3(%r9),_TIF_MCCK_PENDING	bo	BASED(sysc_mcck_pending)	tm	__TI_flags+3(%r9),_TIF_NEED_RESCHED	bo	BASED(sysc_reschedule)	tm	__TI_flags+3(%r9),(_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK)	bnz	BASED(sysc_sigpending)	tm	__TI_flags+3(%r9),_TIF_RESTART_SVC	bo	BASED(sysc_restart)	tm	__TI_flags+3(%r9),_TIF_SINGLE_STEP	bo	BASED(sysc_singlestep)	b	BASED(sysc_leave) ## _TIF_NEED_RESCHED is set, call schedule#sysc_reschedule:	l	%r1,BASED(.Lschedule)	la	%r14,BASED(sysc_work_loop)	br	%r1			# call scheduler ## _TIF_MCCK_PENDING is set, call handler#sysc_mcck_pending:	l	%r1,BASED(.Ls390_handle_mcck)	la	%r14,BASED(sysc_work_loop)	br	%r1			# TIF bit will be cleared by handler ## _TIF_SIGPENDING or _TIF_RESTORE_SIGMASK is set, call do_signal#sysc_sigpending:	ni	__TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP	la	%r2,SP_PTREGS(%r15)	# load pt_regs	l	%r1,BASED(.Ldo_signal)	basr	%r14,%r1		# call do_signal	tm	__TI_flags+3(%r9),_TIF_RESTART_SVC	bo	BASED(sysc_restart)	tm	__TI_flags+3(%r9),_TIF_SINGLE_STEP	bo	BASED(sysc_singlestep)	b	BASED(sysc_work_loop) ## _TIF_RESTART_SVC is set, set up registers and restart svc#sysc_restart:	ni	__TI_flags+3(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC	l	%r7,SP_R2(%r15) 	# load new svc number	sla	%r7,2	mvc	SP_R2(4,%r15),SP_ORIG_R2(%r15) # restore first argument	lm	%r2,%r6,SP_R2(%r15)	# load svc arguments	b	BASED(sysc_do_restart)	# restart svc ## _TIF_SINGLE_STEP is set, call do_single_step#sysc_singlestep:	ni	__TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP	mvi	SP_TRAP+1(%r15),0x28	# set trap indication to pgm check	la	%r2,SP_PTREGS(%r15)	# address of register-save area	l	%r1,BASED(.Lhandle_per)	# load adr. of per handler	la	%r14,BASED(sysc_return)	# load adr. of system return	br	%r1			# branch to do_single_step ## call trace before and after sys_call#sysc_tracesys:	l	%r1,BASED(.Ltrace)	la	%r2,SP_PTREGS(%r15)	# load pt_regs	la	%r3,0	srl	%r7,2	st	%r7,SP_R2(%r15)	basr	%r14,%r1	clc	SP_R2(4,%r15),BASED(.Lnr_syscalls)	bnl	BASED(sysc_tracenogo)	l	%r8,BASED(.Lsysc_table)	l	%r7,SP_R2(%r15) 	# strace might have changed the	sll	%r7,2			#  system call	l	%r8,0(%r7,%r8)sysc_tracego:	lm	%r3,%r6,SP_R3(%r15)	l	%r2,SP_ORIG_R2(%r15)	basr	%r14,%r8		# call sys_xxx	st	%r2,SP_R2(%r15)		# store return valuesysc_tracenogo:	tm	__TI_flags+3(%r9),(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT)	bz	BASED(sysc_return)	l	%r1,BASED(.Ltrace)	la	%r2,SP_PTREGS(%r15)	# load pt_regs	la	%r3,1	la	%r14,BASED(sysc_return)	br	%r1 ## a new process exits the kernel with ret_from_fork#	.globl	ret_from_forkret_from_fork:	l	%r13,__LC_SVC_NEW_PSW+4	l	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	tm	SP_PSW+1(%r15),0x01	# forking a kernel thread ?	bo	BASED(0f)	st	%r15,SP_R15(%r15)	# store stack pointer for new kthread0:	l	%r1,BASED(.Lschedtail)	basr	%r14,%r1	TRACE_IRQS_ON	stosm	__SF_EMPTY(%r15),0x03	# reenable interrupts	b	BASED(sysc_return) ## clone, fork, vfork, exec and sigreturn need glue,# because they all expect pt_regs as parameter,# but are called with different parameter.# return-address is set up above#sys_clone_glue:	la	%r2,SP_PTREGS(%r15)	# load pt_regs	l	%r1,BASED(.Lclone)	br	%r1			# branch to sys_clone sys_fork_glue:	la	%r2,SP_PTREGS(%r15)	# load pt_regs	l	%r1,BASED(.Lfork)	br	%r1			# branch to sys_fork sys_vfork_glue:	la	%r2,SP_PTREGS(%r15)	# load pt_regs	l	%r1,BASED(.Lvfork)	br	%r1			# branch to sys_vfork sys_execve_glue:	la	%r2,SP_PTREGS(%r15)	# load pt_regs	l	%r1,BASED(.Lexecve)	lr	%r12,%r14		# save return address	basr	%r14,%r1		# call sys_execve	ltr	%r2,%r2			# check if execve failed	bnz	0(%r12)			# it did fail -> store result in gpr2	b	4(%r12)			# SKIP ST 2,SP_R2(15) after BASR 14,8					# in system_call/sysc_tracesys sys_sigreturn_glue:	la	%r2,SP_PTREGS(%r15)	# load pt_regs as parameter	l	%r1,BASED(.Lsigreturn)	br	%r1			# branch to sys_sigreturn sys_rt_sigreturn_glue:	la	%r2,SP_PTREGS(%r15)	# load pt_regs as parameter	l	%r1,BASED(.Lrt_sigreturn)	br	%r1			# branch to sys_sigreturn sys_sigaltstack_glue:	la	%r4,SP_PTREGS(%r15)	# load pt_regs as parameter	l	%r1,BASED(.Lsigaltstack)	br	%r1			# branch to sys_sigreturn /* * Program check handler routine */ 	.globl	pgm_check_handlerpgm_check_handler:/* * First we need to check for a special case: * Single stepping an instruction that disables the PER event mask will * cause a PER event AFTER the mask has been set. Example: SVC or LPSW. * For a single stepped SVC the program check handler gets control after * the SVC new PSW has been loaded. But we want to execute the SVC first and * then handle the PER event. Therefore we update the SVC old PSW to point * to the pgm_check_handler and branch to the SVC handler after we checked * if we have to load the kernel stack register. * For every other possible cause for PER event without the PER mask set * we just ignore the PER event (FIXME: is there anything we have to do * for LPSW?). */	STORE_TIMER __LC_SYNC_ENTER_TIMER	SAVE_ALL_BASE __LC_SAVE_AREA	tm	__LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception	bnz	BASED(pgm_per)		# got per exception -> special case	SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA	CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	bz	BASED(pgm_no_vtime)	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMERpgm_no_vtime:#endif	l	%r9,__LC_THREAD_INFO	# load pointer to thread_info struct	l	%r3,__LC_PGM_ILC	# load program interruption code	la	%r8,0x7f	nr	%r8,%r3pgm_do_call:	l	%r7,BASED(.Ljump_table)	sll	%r8,2	l	%r7,0(%r8,%r7)		# load address of handler routine	la	%r2,SP_PTREGS(%r15)	# address of register-save area	la	%r14,BASED(sysc_return)	br	%r7			# branch to interrupt-handler ## handle per exception#pgm_per:	tm	__LC_PGM_OLD_PSW,0x40	# test if per event recording is on	bnz	BASED(pgm_per_std)	# ok, normal per event from user space# ok its one of the special cases, now we need to find out which one	clc	__LC_PGM_OLD_PSW(8),__LC_SVC_NEW_PSW	be	BASED(pgm_svcper)# no interesting special case, ignore PER event	lm	%r12,%r15,__LC_SAVE_AREA	lpsw	0x28 ## Normal per exception#pgm_per_std:	SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA	CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA#ifdef CONFIG_VIRT_CPU_ACCOUNTING	tm	SP_PSW+1(%r15),0x01	# interrupting from user ?	bz	BASED(pgm_no_vtime2)	UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER	UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER	mvc	__LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMERpgm_no_vtime2:#endif

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