/* * drivers/serial/sh-sci.c * * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) * * Copyright (C) 2002 - 2006 Paul Mundt * * based off of the old drivers/char/sh-sci.c by: * * Copyright (C) 1999, 2000 Niibe Yutaka * Copyright (C) 2000 Sugioka Toshinobu * Modified to support multiple serial ports. Stuart Menefy (May 2000). * Modified to support SecureEdge. David McCullough (2002) * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)#define SUPPORT_SYSRQ#endif #undef DEBUG #include <linux/module.h>#include <linux/errno.h>#include <linux/timer.h>#include <linux/interrupt.h>#include <linux/tty.h>#include <linux/tty_flip.h>#include <linux/serial.h>#include <linux/major.h>#include <linux/string.h>#include <linux/sysrq.h>#include <linux/ioport.h>#include <linux/mm.h>#include <linux/init.h>#include <linux/delay.h>#include <linux/console.h>#include <linux/platform_device.h> #ifdef CONFIG_CPU_FREQ#include <linux/notifier.h>#include <linux/cpufreq.h>#endif #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)#include <asm/clock.h>#include <asm/sh_bios.h>#include <asm/kgdb.h>#endif #include <asm/sci.h>#include "sh-sci.h" struct sci_port { struct uart_port port; /* Port type */ unsigned int type; /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ unsigned int irqs[SCIx_NR_IRQS]; /* Port pin configuration */ void (*init_pins)(struct uart_port *port, unsigned int cflag); /* Port enable callback */ void (*enable)(struct uart_port *port); /* Port disable callback */ void (*disable)(struct uart_port *port); /* Break timer */ struct timer_list break_timer; int break_flag;}; #ifdef CONFIG_SH_KGDBstatic struct sci_port *kgdb_sci_port;#endif #ifdef CONFIG_SERIAL_SH_SCI_CONSOLEstatic struct sci_port *serial_console_port;#endif /* Function prototypes */static void sci_stop_tx(struct uart_port *port); #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS static struct sci_port sci_ports[SCI_NPORTS];static struct uart_driver sci_uart_driver; #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \ defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)static inline void handle_error(struct uart_port *port){ /* Clear error flags */ sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));} static int get_char(struct uart_port *port){ unsigned long flags; unsigned short status; int c; spin_lock_irqsave(&port->lock, flags); do { status = sci_in(port, SCxSR); if (status & SCxSR_ERRORS(port)) { handle_error(port); continue; } } while (!(status & SCxSR_RDxF(port))); c = sci_in(port, SCxRDR); sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); spin_unlock_irqrestore(&port->lock, flags); return c;}#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)static void put_char(struct uart_port *port, char c){ unsigned long flags; unsigned short status; spin_lock_irqsave(&port->lock, flags); do { status = sci_in(port, SCxSR); } while (!(status & SCxSR_TDxE(port))); sci_out(port, SCxTDR, c); sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); spin_unlock_irqrestore(&port->lock, flags);}#endif #ifdef CONFIG_SERIAL_SH_SCI_CONSOLEstatic void put_string(struct sci_port *sci_port, const char *buffer, int count){ struct uart_port *port = &sci_port->port; const unsigned char *p = buffer; int i; #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) int checksum; int usegdb=0; #ifdef CONFIG_SH_STANDARD_BIOS /* This call only does a trap the first time it is * called, and so is safe to do here unconditionally */ usegdb |= sh_bios_in_gdb_mode();#endif#ifdef CONFIG_SH_KGDB usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));#endif if (usegdb) { /* $<packet info>#<checksum>. */ do { unsigned char c; put_char(port, '$'); put_char(port, 'O'); /* 'O'utput to console */ checksum = 'O'; for (i=0; i<count; i++) { /* Don't use run length encoding */ int h, l; c = *p++; h = highhex(c); l = lowhex(c); put_char(port, h); put_char(port, l); checksum += h + l; } put_char(port, '#'); put_char(port, highhex(checksum)); put_char(port, lowhex(checksum)); } while (get_char(port) != '+'); } else#endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ for (i=0; i<count; i++) { if (*p == 10) put_char(port, '\r'); put_char(port, *p++); }}#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ #ifdef CONFIG_SH_KGDBstatic int kgdb_sci_getchar(void){ int c; /* Keep trying to read a character, this could be neater */ while ((c = get_char(kgdb_sci_port)) < 0) cpu_relax(); return c;} static inline void kgdb_sci_putchar(int c){ put_char(kgdb_sci_port, c);}#endif /* CONFIG_SH_KGDB */ #if defined(__H8300S__)enum { sci_disable, sci_enable }; static void h8300_sci_config(struct uart_port* port, unsigned int ctrl){ volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL; int ch = (port->mapbase - SMR0) >> 3; unsigned char mask = 1 << (ch+1); if (ctrl == sci_disable) { *mstpcrl |= mask; } else { *mstpcrl &= ~mask; }} static inline void h8300_sci_enable(struct uart_port *port){ h8300_sci_config(port, sci_enable);} static inline void h8300_sci_disable(struct uart_port *port){ h8300_sci_config(port, sci_disable);}#endif #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ defined(__H8300H__) || defined(__H8300S__)static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag){ int ch = (port->mapbase - SMR0) >> 3; /* set DDR regs */ H8300_GPIO_DDR(h8300_sci_pins[ch].port, h8300_sci_pins[ch].rx, H8300_GPIO_INPUT); H8300_GPIO_DDR(h8300_sci_pins[ch].port, h8300_sci_pins[ch].tx, H8300_GPIO_OUTPUT); /* tx mark output*/ H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;}#else#define sci_init_pins_sci NULL#endif #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag){ unsigned int fcr_val = 0; if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; sci_out(port, SCFCR, fcr_val);}#else#define sci_init_pins_irda NULL#endif #ifdef SCI_ONLY#define sci_init_pins_scif NULL#endif #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)/* SH7300 doesn't use RTS/CTS */static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag){ sci_out(port, SCFCR, 0);}#elif defined(CONFIG_CPU_SH3)/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag){ unsigned int fcr_val = 0; unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ ctrl_outw(data & 0x0fcf, SCPCR); if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; else { /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP4MD1,0, Set SCP6MD1,0 = {01} (output) */ ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR); data = ctrl_inb(SCPDR); /* Set /RTS2 (bit6) = 0 */ ctrl_outb(data & 0xbf, SCPDR); } sci_out(port, SCFCR, fcr_val);}#elif defined(CONFIG_CPU_SUBTYPE_SH7722)static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag){ unsigned int fcr_val = 0; if (cflag & CRTSCTS) { fcr_val |= SCFCR_MCE; ctrl_outw(0x0000, PORT_PSCR); } else { unsigned short data; data = ctrl_inw(PORT_PSCR); data &= 0x033f; data |= 0x0400; ctrl_outw(data, PORT_PSCR); ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0); } sci_out(port, SCFCR, fcr_val);}#else/* For SH7750 */static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag){ unsigned int fcr_val = 0; if (cflag & CRTSCTS) { fcr_val |= SCFCR_MCE; } else {#ifdef CONFIG_CPU_SUBTYPE_SH7343 /* Nothing */#elif defined(CONFIG_CPU_SUBTYPE_SH7780) ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */#else ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */#endif } sci_out(port, SCFCR, fcr_val);}#endif #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)static inline int scif_txroom(struct uart_port *port){ return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);} static inline int scif_rxroom(struct uart_port *port){ return sci_in(port, SCRFDR) & 0x7f;}#elsestatic inline int scif_txroom(struct uart_port *port){ return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);} static inline int scif_rxroom(struct uart_port *port){ return sci_in(port, SCFDR) & SCIF_RFDC_MASK;}#endif#endif /* SCIF_ONLY || SCI_AND_SCIF */ static inline int sci_txroom(struct uart_port *port){ return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);} static inline int sci_rxroom(struct uart_port *port){ return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);} /* ********************************************************************** * * the interrupt related routines * * ********************************************************************** */ static void sci_transmit_chars(struct uart_port *port){ struct circ_buf *xmit = &port->info->xmit; unsigned int stopped = uart_tx_stopped(port); unsigned short status; unsigned short ctrl; int count; status = sci_in(port, SCxSR); if (!(status & SCxSR_TDxE(port))) { ctrl = sci_in(port, SCSCR); if (uart_circ_empty(xmit)) { ctrl &= ~SCI_CTRL_FLAGS_TIE; } else { ctrl |= SCI_CTRL_FLAGS_TIE; } sci_out(port, SCSCR, ctrl); return; } #ifndef SCI_ONLY if (port->type == PORT_SCIF) count = scif_txroom(port); else#endif count = sci_txroom(port); do { unsigned char c; if (port->x_char) { c = port->x_char; port->x_char = 0; } else if (!uart_circ_empty(xmit) && !stopped) { c = xmit->buf[xmit->tail]; xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); } else { break; } sci_out(port, SCxTDR, c); port->icount.tx++; } while (--count > 0); sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); if (uart_circ_empty(xmit)) { sci_stop_tx(port); } else { ctrl = sci_in(port, SCSCR); #if !defined(SCI_ONLY) if (port->type == PORT_SCIF) { sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); }#endif ctrl |= SCI_CTRL_FLAGS_TIE; sci_out(port, SCSCR, ctrl); }} /* On SH3, SCIF may read end-of-break as a space->mark char */#define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); }) static inline void sci_receive_chars(struct uart_port *port){ struct sci_port *sci_port = (struct sci_port *)port; struct tty_struct *tty = port->info->tty; int i, count, copied = 0; unsigned short status; unsigned char flag; status = sci_in(port, SCxSR); if (!(status & SCxSR_RDxF(port))) return; while (1) {#if !defined(SCI_ONLY) if (port->type == PORT_SCIF) count = scif_rxroom(port); else#endif count = sci_rxroom(port); /* Don't copy more bytes than there is room for in the buffer */ count = tty_buffer_request_room(tty, count); /* If for any reason we can't copy more data, we're done! */ if (count == 0) break; if (port->type == PORT_SCI) { char c = sci_in(port, SCxRDR); if (uart_handle_sysrq_char(port, c) || sci_port->break_flag) count = 0; else {Lines 1–500 of 1477. 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/* * drivers/serial/sh-sci.c * * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) * * Copyright (C) 2002 - 2006 Paul Mundt * * based off of the old drivers/char/sh-sci.c by: * * Copyright (C) 1999, 2000 Niibe Yutaka * Copyright (C) 2000 Sugioka Toshinobu * Modified to support multiple serial ports. Stuart Menefy (May 2000). * Modified to support SecureEdge. David McCullough (2002) * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ #endif #undef DEBUG #include <linux/module.h> #include <linux/errno.h> #include <linux/timer.h> #include <linux/interrupt.h> #include <linux/tty.h> #include <linux/tty_flip.h> #include <linux/serial.h> #include <linux/major.h> #include <linux/string.h> #include <linux/sysrq.h> #include <linux/ioport.h> #include <linux/mm.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/console.h> #include <linux/platform_device.h> #ifdef CONFIG_CPU_FREQ #include <linux/notifier.h> #include <linux/cpufreq.h> #endif #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64) #include <asm/clock.h> #include <asm/sh_bios.h> #include <asm/kgdb.h> #endif #include <asm/sci.h> #include "sh-sci.h" struct sci_port { struct uart_port port; /* Port type */ unsigned int type; /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ unsigned int irqs[SCIx_NR_IRQS]; /* Port pin configuration */ void (*init_pins)(struct uart_port *port, unsigned int cflag); /* Port enable callback */ void (*enable)(struct uart_port *port); /* Port disable callback */ void (*disable)(struct uart_port *port); /* Break timer */ struct timer_list break_timer; int break_flag; }; #ifdef CONFIG_SH_KGDB static struct sci_port *kgdb_sci_port; #endif #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE static struct sci_port *serial_console_port; #endif /* Function prototypes */ static void sci_stop_tx(struct uart_port *port); #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS static struct sci_port sci_ports[SCI_NPORTS]; static struct uart_driver sci_uart_driver; #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \ defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) static inline void handle_error(struct uart_port *port) { /* Clear error flags */ sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); } static int get_char(struct uart_port *port) { unsigned long flags; unsigned short status; int c; spin_lock_irqsave(&port->lock, flags); do { status = sci_in(port, SCxSR); if (status & SCxSR_ERRORS(port)) { handle_error(port); continue; } } while (!(status & SCxSR_RDxF(port))); c = sci_in(port, SCxRDR); sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); spin_unlock_irqrestore(&port->lock, flags); return c; } #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB) static void put_char(struct uart_port *port, char c) { unsigned long flags; unsigned short status; spin_lock_irqsave(&port->lock, flags); do { status = sci_in(port, SCxSR); } while (!(status & SCxSR_TDxE(port))); sci_out(port, SCxTDR, c); sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); spin_unlock_irqrestore(&port->lock, flags); } #endif #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE static void put_string(struct sci_port *sci_port, const char *buffer, int count) { struct uart_port *port = &sci_port->port; const unsigned char *p = buffer; int i; #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) int checksum; int usegdb=0; #ifdef CONFIG_SH_STANDARD_BIOS /* This call only does a trap the first time it is * called, and so is safe to do here unconditionally */ usegdb |= sh_bios_in_gdb_mode(); #endif #ifdef CONFIG_SH_KGDB usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port)); #endif if (usegdb) { /* $<packet info>#<checksum>. */ do { unsigned char c; put_char(port, '$'); put_char(port, 'O'); /* 'O'utput to console */ checksum = 'O'; for (i=0; i<count; i++) { /* Don't use run length encoding */ int h, l; c = *p++; h = highhex(c); l = lowhex(c); put_char(port, h); put_char(port, l); checksum += h + l; } put_char(port, '#'); put_char(port, highhex(checksum)); put_char(port, lowhex(checksum)); } while (get_char(port) != '+'); } else #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ for (i=0; i<count; i++) { if (*p == 10) put_char(port, '\r'); put_char(port, *p++); } } #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ #ifdef CONFIG_SH_KGDB static int kgdb_sci_getchar(void) { int c; /* Keep trying to read a character, this could be neater */ while ((c = get_char(kgdb_sci_port)) < 0) cpu_relax(); return c; } static inline void kgdb_sci_putchar(int c) { put_char(kgdb_sci_port, c); } #endif /* CONFIG_SH_KGDB */ #if defined(__H8300S__) enum { sci_disable, sci_enable }; static void h8300_sci_config(struct uart_port* port, unsigned int ctrl) { volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL; int ch = (port->mapbase - SMR0) >> 3; unsigned char mask = 1 << (ch+1); if (ctrl == sci_disable) { *mstpcrl |= mask; } else { *mstpcrl &= ~mask; } } static inline void h8300_sci_enable(struct uart_port *port) { h8300_sci_config(port, sci_enable); } static inline void h8300_sci_disable(struct uart_port *port) { h8300_sci_config(port, sci_disable); } #endif #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ defined(__H8300H__) || defined(__H8300S__) static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) { int ch = (port->mapbase - SMR0) >> 3; /* set DDR regs */ H8300_GPIO_DDR(h8300_sci_pins[ch].port, h8300_sci_pins[ch].rx, H8300_GPIO_INPUT); H8300_GPIO_DDR(h8300_sci_pins[ch].port, h8300_sci_pins[ch].tx, H8300_GPIO_OUTPUT); /* tx mark output*/ H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; } #else #define sci_init_pins_sci NULL #endif #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; sci_out(port, SCFCR, fcr_val); } #else #define sci_init_pins_irda NULL #endif #ifdef SCI_ONLY #define sci_init_pins_scif NULL #endif #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) /* SH7300 doesn't use RTS/CTS */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { sci_out(port, SCFCR, 0); } #elif defined(CONFIG_CPU_SH3) /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ ctrl_outw(data & 0x0fcf, SCPCR); if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; else { /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP4MD1,0, Set SCP6MD1,0 = {01} (output) */ ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR); data = ctrl_inb(SCPDR); /* Set /RTS2 (bit6) = 0 */ ctrl_outb(data & 0xbf, SCPDR); } sci_out(port, SCFCR, fcr_val); } #elif defined(CONFIG_CPU_SUBTYPE_SH7722) static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; if (cflag & CRTSCTS) { fcr_val |= SCFCR_MCE; ctrl_outw(0x0000, PORT_PSCR); } else { unsigned short data; data = ctrl_inw(PORT_PSCR); data &= 0x033f; data |= 0x0400; ctrl_outw(data, PORT_PSCR); ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0); } sci_out(port, SCFCR, fcr_val); } #else /* For SH7750 */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; if (cflag & CRTSCTS) { fcr_val |= SCFCR_MCE; } else { #ifdef CONFIG_CPU_SUBTYPE_SH7343 /* Nothing */ #elif defined(CONFIG_CPU_SUBTYPE_SH7780) ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ #else ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ #endif } sci_out(port, SCFCR, fcr_val); } #endif #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) static inline int scif_txroom(struct uart_port *port) { return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f); } static inline int scif_rxroom(struct uart_port *port) { return sci_in(port, SCRFDR) & 0x7f; } #else static inline int scif_txroom(struct uart_port *port) { return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); } static inline int scif_rxroom(struct uart_port *port) { return sci_in(port, SCFDR) & SCIF_RFDC_MASK; } #endif #endif /* SCIF_ONLY || SCI_AND_SCIF */ static inline int sci_txroom(struct uart_port *port) { return ((sci_in(port, SCxSR) & SCI_TDRE) != 0); } static inline int sci_rxroom(struct uart_port *port) { return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0); } /* ********************************************************************** * * the interrupt related routines * * ********************************************************************** */ static void sci_transmit_chars(struct uart_port *port) { struct circ_buf *xmit = &port->info->xmit; unsigned int stopped = uart_tx_stopped(port); unsigned short status; unsigned short ctrl; int count; status = sci_in(port, SCxSR); if (!(status & SCxSR_TDxE(port))) { ctrl = sci_in(port, SCSCR); if (uart_circ_empty(xmit)) { ctrl &= ~SCI_CTRL_FLAGS_TIE; } else { ctrl |= SCI_CTRL_FLAGS_TIE; } sci_out(port, SCSCR, ctrl); return; } #ifndef SCI_ONLY if (port->type == PORT_SCIF) count = scif_txroom(port); else #endif count = sci_txroom(port); do { unsigned char c; if (port->x_char) { c = port->x_char; port->x_char = 0; } else if (!uart_circ_empty(xmit) && !stopped) { c = xmit->buf[xmit->tail]; xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); } else { break; } sci_out(port, SCxTDR, c); port->icount.tx++; } while (--count > 0); sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); if (uart_circ_empty(xmit)) { sci_stop_tx(port); } else { ctrl = sci_in(port, SCSCR); #if !defined(SCI_ONLY) if (port->type == PORT_SCIF) { sci_in(port, SCxSR); /* Dummy read */ sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); } #endif ctrl |= SCI_CTRL_FLAGS_TIE; sci_out(port, SCSCR, ctrl); } } /* On SH3, SCIF may read end-of-break as a space->mark char */ #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); }) static inline void sci_receive_chars(struct uart_port *port) { struct sci_port *sci_port = (struct sci_port *)port; struct tty_struct *tty = port->info->tty; int i, count, copied = 0; unsigned short status; unsigned char flag; status = sci_in(port, SCxSR); if (!(status & SCxSR_RDxF(port))) return; while (1) { #if !defined(SCI_ONLY) if (port->type == PORT_SCIF) count = scif_rxroom(port); else #endif count = sci_rxroom(port); /* Don't copy more bytes than there is room for in the buffer */ count = tty_buffer_request_room(tty, count); /* If for any reason we can't copy more data, we're done! */ if (count == 0) break; if (port->type == PORT_SCI) { char c = sci_in(port, SCxRDR); if (uart_handle_sysrq_char(port, c) || sci_port->break_flag) count = 0; else {