#ifndef __ASM_X86_PROCESSOR_H#define __ASM_X86_PROCESSOR_H #include <asm/processor-flags.h> /* migration helpers, for KVM - will be removed in 2.6.25: */#include <asm/vm86.h>#define Xgt_desc_struct	desc_ptr /* Forward declaration, a strange C thing */struct task_struct;struct mm_struct; #include <asm/vm86.h>#include <asm/math_emu.h>#include <asm/segment.h>#include <asm/types.h>#include <asm/sigcontext.h>#include <asm/current.h>#include <asm/cpufeature.h>#include <asm/system.h>#include <asm/page.h>#include <asm/percpu.h>#include <asm/msr.h>#include <asm/desc_defs.h>#include <asm/nops.h>#include <linux/personality.h>#include <linux/cpumask.h>#include <linux/cache.h>#include <linux/threads.h>#include <linux/init.h> /* * Default implementation of macro that returns current * instruction pointer ("program counter"). */static inline void *current_text_addr(void){	void *pc;	asm volatile("mov $1f,%0\n1:":"=r" (pc));	return pc;} #ifdef CONFIG_X86_VSMP#define ARCH_MIN_TASKALIGN	(1 << INTERNODE_CACHE_SHIFT)#define ARCH_MIN_MMSTRUCT_ALIGN	(1 << INTERNODE_CACHE_SHIFT)#else#define ARCH_MIN_TASKALIGN	16#define ARCH_MIN_MMSTRUCT_ALIGN	0#endif /* *  CPU type and hardware bug flags. Kept separately for each CPU. *  Members of this structure are referenced in head.S, so think twice *  before touching them. [mj] */ struct cpuinfo_x86 {	__u8	x86;		/* CPU family */	__u8	x86_vendor;	/* CPU vendor */	__u8	x86_model;	__u8	x86_mask;#ifdef CONFIG_X86_32	char	wp_works_ok;	/* It doesn't on 386's */	char	hlt_works_ok;	/* Problems on some 486Dx4's and old 386's */	char	hard_math;	char	rfu;	char	fdiv_bug;	char	f00f_bug;	char	coma_bug;	char	pad0;#else	/* number of 4K pages in DTLB/ITLB combined(in pages)*/	int     x86_tlbsize;	__u8    x86_virt_bits, x86_phys_bits;	/* cpuid returned core id bits */	__u8    x86_coreid_bits;	/* Max extended CPUID function supported */	__u32   extended_cpuid_level;#endif	int	cpuid_level;	/* Maximum supported CPUID level, -1=no CPUID */	__u32	x86_capability[NCAPINTS];	char	x86_vendor_id[16];	char	x86_model_id[64];	int 	x86_cache_size;  /* in KB - valid for CPUS which support this				    call  */	int 	x86_cache_alignment;	/* In bytes */	int	x86_power;	unsigned long loops_per_jiffy;#ifdef CONFIG_SMP	cpumask_t llc_shared_map;	/* cpus sharing the last level cache */#endif	u16 x86_max_cores;		/* cpuid returned max cores value */	u16 apicid;	u16 x86_clflush_size;#ifdef CONFIG_SMP	u16 booted_cores;		/* number of cores as seen by OS */	u16 phys_proc_id; 		/* Physical processor id. */	u16 cpu_core_id;  		/* Core id */	u16 cpu_index;			/* index into per_cpu list */#endif} __attribute__((__aligned__(SMP_CACHE_BYTES))); #define X86_VENDOR_INTEL 0#define X86_VENDOR_CYRIX 1#define X86_VENDOR_AMD 2#define X86_VENDOR_UMC 3#define X86_VENDOR_NEXGEN 4#define X86_VENDOR_CENTAUR 5#define X86_VENDOR_TRANSMETA 7#define X86_VENDOR_NSC 8#define X86_VENDOR_NUM 9#define X86_VENDOR_UNKNOWN 0xff /* * capabilities of CPUs */extern struct cpuinfo_x86 boot_cpu_data;extern struct cpuinfo_x86 new_cpu_data;extern struct tss_struct doublefault_tss;extern __u32 cleared_cpu_caps[NCAPINTS]; #ifdef CONFIG_SMPDECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);#define cpu_data(cpu)		per_cpu(cpu_info, cpu)#define current_cpu_data	cpu_data(smp_processor_id())#else#define cpu_data(cpu)		boot_cpu_data#define current_cpu_data	boot_cpu_data#endif void cpu_detect(struct cpuinfo_x86 *c); extern void identify_cpu(struct cpuinfo_x86 *);extern void identify_boot_cpu(void);extern void identify_secondary_cpu(struct cpuinfo_x86 *);extern void print_cpu_info(struct cpuinfo_x86 *);extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);extern unsigned short num_cache_leaves; #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)extern void detect_ht(struct cpuinfo_x86 *c);#elsestatic inline void detect_ht(struct cpuinfo_x86 *c) {}#endif static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,					 unsigned int *ecx, unsigned int *edx){	/* ecx is often an input as well as an output. */	__asm__("cpuid"		: "=a" (*eax),		  "=b" (*ebx),		  "=c" (*ecx),		  "=d" (*edx)		: "0" (*eax), "2" (*ecx));} static inline void load_cr3(pgd_t *pgdir){	write_cr3(__pa(pgdir));} #ifdef CONFIG_X86_32/* This is the TSS defined by the hardware. */struct x86_hw_tss {	unsigned short	back_link, __blh;	unsigned long	sp0;	unsigned short	ss0, __ss0h;	unsigned long	sp1;	unsigned short	ss1, __ss1h;	/* ss1 caches MSR_IA32_SYSENTER_CS */	unsigned long	sp2;	unsigned short	ss2, __ss2h;	unsigned long	__cr3;	unsigned long	ip;	unsigned long	flags;	unsigned long	ax, cx, dx, bx;	unsigned long	sp, bp, si, di;	unsigned short	es, __esh;	unsigned short	cs, __csh;	unsigned short	ss, __ssh;	unsigned short	ds, __dsh;	unsigned short	fs, __fsh;	unsigned short	gs, __gsh;	unsigned short	ldt, __ldth;	unsigned short	trace, io_bitmap_base;} __attribute__((packed));#elsestruct x86_hw_tss {	u32 reserved1;	u64 sp0;	u64 sp1;	u64 sp2;	u64 reserved2;	u64 ist[7];	u32 reserved3;	u32 reserved4;	u16 reserved5;	u16 io_bitmap_base;} __attribute__((packed)) ____cacheline_aligned;#endif /* * Size of io_bitmap. */#define IO_BITMAP_BITS  65536#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)#define INVALID_IO_BITMAP_OFFSET 0x8000#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 struct tss_struct {	struct x86_hw_tss x86_tss; 	/*	 * The extra 1 is there because the CPU will access an	 * additional byte beyond the end of the IO permission	 * bitmap. The extra byte must be all 1 bits, and must	 * be within the limit.	 */	unsigned long	io_bitmap[IO_BITMAP_LONGS + 1];	/*	 * Cache the current maximum and the last task that used the bitmap:	 */	unsigned long io_bitmap_max;	struct thread_struct *io_bitmap_owner;	/*	 * pads the TSS to be cacheline-aligned (size is 0x100)	 */	unsigned long __cacheline_filler[35];	/*	 * .. and then another 0x100 bytes for emergency kernel stack	 */	unsigned long stack[64];} __attribute__((packed)); DECLARE_PER_CPU(struct tss_struct, init_tss); /* Save the original ist values for checking stack pointers during debugging */struct orig_ist {	unsigned long ist[7];}; #define	MXCSR_DEFAULT		0x1f80 struct i387_fsave_struct {	u32	cwd;	u32	swd;	u32	twd;	u32	fip;	u32	fcs;	u32	foo;	u32	fos;	u32	st_space[20];	/* 8*10 bytes for each FP-reg = 80 bytes */	u32	status;		/* software status information */}; struct i387_fxsave_struct {	u16	cwd;	u16	swd;	u16	twd;	u16	fop;	union {		struct {			u64	rip;			u64	rdp;		};		struct {			u32	fip;			u32	fcs;			u32	foo;			u32	fos;		};	};	u32	mxcsr;	u32	mxcsr_mask;	u32	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */	u32	xmm_space[64];	/* 16*16 bytes for each XMM-reg = 256 bytes */	u32	padding[24];} __attribute__((aligned(16))); struct i387_soft_struct {	u32	cwd;	u32	swd;	u32	twd;	u32	fip;	u32	fcs;	u32	foo;	u32	fos;	u32	st_space[20];	/* 8*10 bytes for each FP-reg = 80 bytes */	u8	ftop, changed, lookahead, no_update, rm, alimit;	struct info	*info;	u32	entry_eip;}; union i387_union {	struct i387_fsave_struct	fsave;	struct i387_fxsave_struct	fxsave;	struct i387_soft_struct 	soft;}; #ifdef CONFIG_X86_32DECLARE_PER_CPU(u8, cpu_llc_id);#elseDECLARE_PER_CPU(struct orig_ist, orig_ist);#endif extern void print_cpu_info(struct cpuinfo_x86 *);extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);extern unsigned short num_cache_leaves; struct thread_struct {/* cached TLS descriptors. */	struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];	unsigned long	sp0;	unsigned long	sp;#ifdef CONFIG_X86_32	unsigned long	sysenter_cs;#else	unsigned long 	usersp;	/* Copy from PDA */	unsigned short	es, ds, fsindex, gsindex;#endif	unsigned long	ip;	unsigned long	fs;	unsigned long	gs;/* Hardware debugging registers */	unsigned long	debugreg0;	unsigned long	debugreg1;	unsigned long	debugreg2;	unsigned long	debugreg3;	unsigned long	debugreg6;	unsigned long	debugreg7;/* fault info */	unsigned long	cr2, trap_no, error_code;/* floating point info */	union i387_union	i387 __attribute__((aligned(16)));;#ifdef CONFIG_X86_32/* virtual 86 mode info */	struct vm86_struct __user *vm86_info;	unsigned long		screen_bitmap;	unsigned long		v86flags, v86mask, saved_sp0;	unsigned int		saved_fs, saved_gs;#endif/* IO permissions */	unsigned long	*io_bitmap_ptr;	unsigned long	iopl;/* max allowed port in the bitmap, in bytes: */	unsigned io_bitmap_max;/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */	unsigned long	debugctlmsr;/* Debug Store - if not 0 points to a DS Save Area configuration; *               goes into MSR_IA32_DS_AREA */	unsigned long	ds_area_msr;}; static inline unsigned long native_get_debugreg(int regno){	unsigned long val = 0; 	/* Damn you, gcc! */ 	switch (regno) {	case 0:		asm("mov %%db0, %0" :"=r" (val)); break;	case 1:		asm("mov %%db1, %0" :"=r" (val)); break;	case 2:		asm("mov %%db2, %0" :"=r" (val)); break;	case 3:		asm("mov %%db3, %0" :"=r" (val)); break;	case 6:		asm("mov %%db6, %0" :"=r" (val)); break;	case 7:		asm("mov %%db7, %0" :"=r" (val)); break;	default:		BUG();	}	return val;} static inline void native_set_debugreg(int regno, unsigned long value){	switch (regno) {	case 0:		asm("mov %0,%%db0"	: /* no output */ :"r" (value));		break;	case 1:		asm("mov %0,%%db1"	: /* no output */ :"r" (value));		break;	case 2:		asm("mov %0,%%db2"	: /* no output */ :"r" (value));		break;	case 3:		asm("mov %0,%%db3"	: /* no output */ :"r" (value));		break;	case 6:		asm("mov %0,%%db6"	: /* no output */ :"r" (value));		break;	case 7:		asm("mov %0,%%db7"	: /* no output */ :"r" (value));		break;	default:		BUG();	}} /* * Set IOPL bits in EFLAGS from given mask */static inline void native_set_iopl_mask(unsigned mask){#ifdef CONFIG_X86_32	unsigned int reg;	__asm__ __volatile__ ("pushfl;"			      "popl %0;"			      "andl %1, %0;"			      "orl %2, %0;"			      "pushl %0;"			      "popfl"				: "=&r" (reg)				: "i" (~X86_EFLAGS_IOPL), "r" (mask));#endif} static inline void native_load_sp0(struct tss_struct *tss,				   struct thread_struct *thread){	tss->x86_tss.sp0 = thread->sp0;#ifdef CONFIG_X86_32	/* Only happens when SEP is enabled, no need to test "SEP"arately */	if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {		tss->x86_tss.ss1 = thread->sysenter_cs;		wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);	}#endif} static inline void native_swapgs(void){#ifdef CONFIG_X86_64	asm volatile("swapgs" ::: "memory");#endif} #ifdef CONFIG_PARAVIRT#include <asm/paravirt.h>#else#define __cpuid native_cpuid#define paravirt_enabled() 0 /* * These special macros can be used to get or set a debugging register */#define get_debugreg(var, register)				\	(var) = native_get_debugreg(register)#define set_debugreg(value, register)				\	native_set_debugreg(register, value) static inline void load_sp0(struct tss_struct *tss,			    struct thread_struct *thread){	native_load_sp0(tss, thread);} #define set_iopl_mask native_set_iopl_mask#define SWAPGS	swapgs#endif /* CONFIG_PARAVIRT */ /* * Save the cr4 feature set we're using (ie * Pentium 4MB enable and PPro Global page * enable), so that any CPU's that boot up * after us can get the correct flags. */extern unsigned long mmu_cr4_features; static inline void set_in_cr4(unsigned long mask){	unsigned cr4;	mmu_cr4_features |= mask;	cr4 = read_cr4();	cr4 |= mask;	write_cr4(cr4);} static inline void clear_in_cr4(unsigned long mask){	unsigned cr4;	mmu_cr4_features &= ~mask;	cr4 = read_cr4();	cr4 &= ~mask;	write_cr4(cr4);} struct microcode_header {	unsigned int hdrver;	unsigned int rev;	unsigned int date;	unsigned int sig;

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