/* * arch/powerpc/sysdev/ipic.c * * IPIC routines implementations. * * Copyright 2005 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute  it and/or modify it * under  the terms of  the GNU General  Public License as published by the * Free Software Foundation;  either version 2 of the  License, or (at your * option) any later version. */#include <linux/kernel.h>#include <linux/init.h>#include <linux/errno.h>#include <linux/reboot.h>#include <linux/slab.h>#include <linux/stddef.h>#include <linux/sched.h>#include <linux/signal.h>#include <linux/syscore_ops.h>#include <linux/device.h>#include <linux/bootmem.h>#include <linux/spinlock.h>#include <linux/fsl_devices.h>#include <asm/irq.h>#include <asm/io.h>#include <asm/prom.h>#include <asm/ipic.h> #include "ipic.h" static struct ipic * primary_ipic;static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;static DEFINE_RAW_SPINLOCK(ipic_lock); static struct ipic_info ipic_info[] = {	[1] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 16,		.prio_mask = 0,	},	[2] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 17,		.prio_mask = 1,	},	[3] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 18,		.prio_mask = 2,	},	[4] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 19,		.prio_mask = 3,	},	[5] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 20,		.prio_mask = 4,	},	[6] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 21,		.prio_mask = 5,	},	[7] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 22,		.prio_mask = 6,	},	[8] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_C,		.force	= IPIC_SIFCR_H,		.bit	= 23,		.prio_mask = 7,	},	[9] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 24,		.prio_mask = 0,	},	[10] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 25,		.prio_mask = 1,	},	[11] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 26,		.prio_mask = 2,	},	[12] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 27,		.prio_mask = 3,	},	[13] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 28,		.prio_mask = 4,	},	[14] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 29,		.prio_mask = 5,	},	[15] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 30,		.prio_mask = 6,	},	[16] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_D,		.force	= IPIC_SIFCR_H,		.bit	= 31,		.prio_mask = 7,	},	[17] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SEFCR,		.bit	= 1,		.prio_mask = 5,	},	[18] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SEFCR,		.bit	= 2,		.prio_mask = 6,	},	[19] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SEFCR,		.bit	= 3,		.prio_mask = 7,	},	[20] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SEFCR,		.bit	= 4,		.prio_mask = 4,	},	[21] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SEFCR,		.bit	= 5,		.prio_mask = 5,	},	[22] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SEFCR,		.bit	= 6,		.prio_mask = 6,	},	[23] = {		.ack	= IPIC_SEPNR,		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SEFCR,		.bit	= 7,		.prio_mask = 7,	},	[32] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 0,		.prio_mask = 0,	},	[33] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 1,		.prio_mask = 1,	},	[34] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 2,		.prio_mask = 2,	},	[35] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 3,		.prio_mask = 3,	},	[36] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 4,		.prio_mask = 4,	},	[37] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 5,		.prio_mask = 5,	},	[38] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 6,		.prio_mask = 6,	},	[39] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_A,		.force	= IPIC_SIFCR_H,		.bit	= 7,		.prio_mask = 7,	},	[40] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 8,		.prio_mask = 0,	},	[41] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 9,		.prio_mask = 1,	},	[42] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 10,		.prio_mask = 2,	},	[43] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 11,		.prio_mask = 3,	},	[44] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 12,		.prio_mask = 4,	},	[45] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 13,		.prio_mask = 5,	},	[46] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 14,		.prio_mask = 6,	},	[47] = {		.mask	= IPIC_SIMSR_H,		.prio	= IPIC_SIPRR_B,		.force	= IPIC_SIFCR_H,		.bit	= 15,		.prio_mask = 7,	},	[48] = {		.mask	= IPIC_SEMSR,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SEFCR,		.bit	= 0,		.prio_mask = 4,	},	[64] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SIFCR_L,		.bit	= 0,		.prio_mask = 0,	},	[65] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SIFCR_L,		.bit	= 1,		.prio_mask = 1,	},	[66] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SIFCR_L,		.bit	= 2,		.prio_mask = 2,	},	[67] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_A,		.force	= IPIC_SIFCR_L,		.bit	= 3,		.prio_mask = 3,	},	[68] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SIFCR_L,		.bit	= 4,		.prio_mask = 0,	},	[69] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SIFCR_L,		.bit	= 5,		.prio_mask = 1,	},	[70] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SIFCR_L,		.bit	= 6,		.prio_mask = 2,	},	[71] = {		.mask	= IPIC_SIMSR_L,		.prio	= IPIC_SMPRR_B,		.force	= IPIC_SIFCR_L,		.bit	= 7,		.prio_mask = 3,	},	[72] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 8,	},	[73] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 9,	},	[74] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 10,	},	[75] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 11,	},	[76] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 12,	},	[77] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 13,	},	[78] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 14,	},	[79] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 15,	},	[80] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 16,	},	[81] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 17,	},	[82] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 18,	},	[83] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 19,	},	[84] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 20,	},	[85] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 21,	},	[86] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 22,	},	[87] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 23,	},	[88] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 24,	},	[89] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 25,	},	[90] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 26,	},	[91] = {		.mask	= IPIC_SIMSR_L,		.prio	= 0,		.force	= IPIC_SIFCR_L,		.bit	= 27,	},

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