/* * Processor capabilities determination functions. * * Copyright (C) xxxx the Anonymous * Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 2003, 2004 Maciej W. Rozycki * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */#include <linux/init.h>#include <linux/kernel.h>#include <linux/ptrace.h>#include <linux/smp.h>#include <linux/stddef.h>#include <linux/export.h> #include <asm/bugs.h>#include <asm/cpu.h>#include <asm/cpu-type.h>#include <asm/fpu.h>#include <asm/mipsregs.h>#include <asm/watch.h>#include <asm/elf.h>#include <asm/spram.h>#include <asm/uaccess.h> static int mips_fpu_disabled; static int __init fpu_disable(char *s){ cpu_data[0].options &= ~MIPS_CPU_FPU; mips_fpu_disabled = 1; return 1;} __setup("nofpu", fpu_disable); int mips_dsp_disabled; static int __init dsp_disable(char *s){ cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); mips_dsp_disabled = 1; return 1;} __setup("nodsp", dsp_disable); static inline void check_errata(void){ struct cpuinfo_mips *c = ¤t_cpu_data; switch (current_cpu_type()) { case CPU_34K: /* * Erratum "RPS May Cause Incorrect Instruction Execution" * This code only handles VPE0, any SMP/SMTC/RTOS code * making use of VPE1 will be responsable for that VPE. */ if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); break; default: break; }} void __init check_bugs32(void){ check_errata();} /* * Probe whether cpu has config register by trying to play with * alternate cache bit and see whether it matters. * It's used by cpu_probe to distinguish between R3000A and R3081. */static inline int cpu_has_confreg(void){#ifdef CONFIG_CPU_R3000 extern unsigned long r3k_cache_size(unsigned long); unsigned long size1, size2; unsigned long cfg = read_c0_conf(); size1 = r3k_cache_size(ST0_ISC); write_c0_conf(cfg ^ R30XX_CONF_AC); size2 = r3k_cache_size(ST0_ISC); write_c0_conf(cfg); return size1 != size2;#else return 0;#endif} static inline void set_elf_platform(int cpu, const char *plat){ if (cpu == 0) __elf_platform = plat;} /* * Get the FPU Implementation/Revision. */static inline unsigned long cpu_get_fpu_id(void){ unsigned long tmp, fpu_id; tmp = read_c0_status(); __enable_fpu(); fpu_id = read_32bit_cp1_register(CP1_REVISION); write_c0_status(tmp); return fpu_id;} /* * Check the CPU has an FPU the official way. */static inline int __cpu_has_fpu(void){ return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);} static inline void cpu_probe_vmbits(struct cpuinfo_mips *c){#ifdef __NEED_VMBITS_PROBE write_c0_entryhi(0x3fffffffffffe000ULL); back_to_back_c0_hazard(); c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);#endif} static void set_isa(struct cpuinfo_mips *c, unsigned int isa){ switch (isa) { case MIPS_CPU_ISA_M64R2: c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; case MIPS_CPU_ISA_M64R1: c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; case MIPS_CPU_ISA_V: c->isa_level |= MIPS_CPU_ISA_V; case MIPS_CPU_ISA_IV: c->isa_level |= MIPS_CPU_ISA_IV; case MIPS_CPU_ISA_III: c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; break; case MIPS_CPU_ISA_M32R2: c->isa_level |= MIPS_CPU_ISA_M32R2; case MIPS_CPU_ISA_M32R1: c->isa_level |= MIPS_CPU_ISA_M32R1; case MIPS_CPU_ISA_II: c->isa_level |= MIPS_CPU_ISA_II; break; }} static char unknown_isa[] = KERN_ERR \ "Unsupported ISA type, c0.config0: %d."; static inline unsigned int decode_config0(struct cpuinfo_mips *c){ unsigned int config0; int isa; config0 = read_c0_config(); if (((config0 & MIPS_CONF_MT) >> 7) == 1) c->options |= MIPS_CPU_TLB; isa = (config0 & MIPS_CONF_AT) >> 13; switch (isa) { case 0: switch ((config0 & MIPS_CONF_AR) >> 10) { case 0: set_isa(c, MIPS_CPU_ISA_M32R1); break; case 1: set_isa(c, MIPS_CPU_ISA_M32R2); break; default: goto unknown; } break; case 2: switch ((config0 & MIPS_CONF_AR) >> 10) { case 0: set_isa(c, MIPS_CPU_ISA_M64R1); break; case 1: set_isa(c, MIPS_CPU_ISA_M64R2); break; default: goto unknown; } break; default: goto unknown; } return config0 & MIPS_CONF_M; unknown: panic(unknown_isa, config0);} static inline unsigned int decode_config1(struct cpuinfo_mips *c){ unsigned int config1; config1 = read_c0_config1(); if (config1 & MIPS_CONF1_MD) c->ases |= MIPS_ASE_MDMX; if (config1 & MIPS_CONF1_WR) c->options |= MIPS_CPU_WATCH; if (config1 & MIPS_CONF1_CA) c->ases |= MIPS_ASE_MIPS16; if (config1 & MIPS_CONF1_EP) c->options |= MIPS_CPU_EJTAG; if (config1 & MIPS_CONF1_FP) { c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_32FPR; } if (cpu_has_tlb) c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; return config1 & MIPS_CONF_M;} static inline unsigned int decode_config2(struct cpuinfo_mips *c){ unsigned int config2; config2 = read_c0_config2(); if (config2 & MIPS_CONF2_SL) c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; return config2 & MIPS_CONF_M;} static inline unsigned int decode_config3(struct cpuinfo_mips *c){ unsigned int config3; config3 = read_c0_config3(); if (config3 & MIPS_CONF3_SM) { c->ases |= MIPS_ASE_SMARTMIPS; c->options |= MIPS_CPU_RIXI; } if (config3 & MIPS_CONF3_RXI) c->options |= MIPS_CPU_RIXI; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_DSP2P) c->ases |= MIPS_ASE_DSP2P; if (config3 & MIPS_CONF3_VINT) c->options |= MIPS_CPU_VINT; if (config3 & MIPS_CONF3_VEIC) c->options |= MIPS_CPU_VEIC; if (config3 & MIPS_CONF3_MT) c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_ISA) c->options |= MIPS_CPU_MICROMIPS; if (config3 & MIPS_CONF3_VZ) c->ases |= MIPS_ASE_VZ; return config3 & MIPS_CONF_M;} static inline unsigned int decode_config4(struct cpuinfo_mips *c){ unsigned int config4; config4 = read_c0_config4(); if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT && cpu_has_tlb) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; c->kscratch_mask = (config4 >> 16) & 0xff; return config4 & MIPS_CONF_M;} static inline unsigned int decode_config5(struct cpuinfo_mips *c){ unsigned int config5; config5 = read_c0_config5(); config5 &= ~MIPS_CONF5_UFR; write_c0_config5(config5); return config5 & MIPS_CONF_M;} static void decode_configs(struct cpuinfo_mips *c){ int ok; /* MIPS32 or MIPS64 compliant CPU. */ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; ok = decode_config0(c); /* Read Config registers. */ BUG_ON(!ok); /* Arch spec violation! */ if (ok) ok = decode_config1(c); if (ok) ok = decode_config2(c); if (ok) ok = decode_config3(c); if (ok) ok = decode_config4(c); if (ok) ok = decode_config5(c); mips_probe_watch_registers(c); if (cpu_has_mips_r2) c->core = read_c0_ebase() & 0x3ff;} #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu){ switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_R2000: c->cputype = CPU_R2000; __cpu_name[cpu] = "R2000"; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; break; case PRID_IMP_R3000: if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { if (cpu_has_confreg()) { c->cputype = CPU_R3081E; __cpu_name[cpu] = "R3081"; } else { c->cputype = CPU_R3000A; __cpu_name[cpu] = "R3000A"; } } else { c->cputype = CPU_R3000; __cpu_name[cpu] = "R3000"; } c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400) { c->cputype = CPU_R4400PC; __cpu_name[cpu] = "R4400PC"; } else { c->cputype = CPU_R4000PC; __cpu_name[cpu] = "R4000PC"; } } else { int cca = read_c0_config() & CONF_CM_CMASK; int mc; /* * SC and MC versions can't be reliably told apart, * but only the latter support coherent caching * modes so assume the firmware has set the KSEG0 * coherency attribute reasonably (if uncached, we * assume SC). */ switch (cca) { case CONF_CM_CACHABLE_CE: case CONF_CM_CACHABLE_COW: case CONF_CM_CACHABLE_CUW: mc = 1; break; default: mc = 0; break; } if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400) { c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; } else { c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; } } set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_VCE | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_VR41XX: set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS; c->tlbsize = 32; switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; __cpu_name[cpu] = "NEC VR4111"; break; case PRID_REV_VR4121: c->cputype = CPU_VR4121; __cpu_name[cpu] = "NEC VR4121"; break; case PRID_REV_VR4122: if ((c->processor_id & 0xf) < 0x3) { c->cputype = CPU_VR4122; __cpu_name[cpu] = "NEC VR4122"; } else { c->cputype = CPU_VR4181A; __cpu_name[cpu] = "NEC VR4181A"; } break; case PRID_REV_VR4130: if ((c->processor_id & 0xf) < 0x4) { c->cputype = CPU_VR4131; __cpu_name[cpu] = "NEC VR4131"; } else { c->cputype = CPU_VR4133; c->options |= MIPS_CPU_LLSC; __cpu_name[cpu] = "NEC VR4133"; } break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); c->cputype = CPU_VR41XX; __cpu_name[cpu] = "NEC Vr41xx"; break; } break; case PRID_IMP_R4300: c->cputype = CPU_R4300; __cpu_name[cpu] = "R4300"; set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_R4600: c->cputype = CPU_R4600; __cpu_name[cpu] = "R4600"; set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 48; break; #if 0 case PRID_IMP_R4650: /* * This processor doesn't have an MMU, so it's not * "real easy" to run Linux on it. It is left purely * for documentation. Commented out because it shares * it's c0_prid id number with the TX3900. */ c->cputype = CPU_R4650; __cpu_name[cpu] = "R4650"; set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; break; #endif case PRID_IMP_TX39: c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; __cpu_name[cpu] = "TX3912"; c->tlbsize = 32; break; case PRID_REV_TX3922: c->cputype = CPU_TX3922;Lines 1–500 of 1106. Load more
/* * Processor capabilities determination functions. * * Copyright (C) xxxx the Anonymous * Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 2003, 2004 Maciej W. Rozycki * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #include <linux/init.h> #include <linux/kernel.h> #include <linux/ptrace.h> #include <linux/smp.h> #include <linux/stddef.h> #include <linux/export.h> #include <asm/bugs.h> #include <asm/cpu.h> #include <asm/cpu-type.h> #include <asm/fpu.h> #include <asm/mipsregs.h> #include <asm/watch.h> #include <asm/elf.h> #include <asm/spram.h> #include <asm/uaccess.h> static int mips_fpu_disabled; static int __init fpu_disable(char *s) { cpu_data[0].options &= ~MIPS_CPU_FPU; mips_fpu_disabled = 1; return 1; } __setup("nofpu", fpu_disable); int mips_dsp_disabled; static int __init dsp_disable(char *s) { cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); mips_dsp_disabled = 1; return 1; } __setup("nodsp", dsp_disable); static inline void check_errata(void) { struct cpuinfo_mips *c = ¤t_cpu_data; switch (current_cpu_type()) { case CPU_34K: /* * Erratum "RPS May Cause Incorrect Instruction Execution" * This code only handles VPE0, any SMP/SMTC/RTOS code * making use of VPE1 will be responsable for that VPE. */ if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); break; default: break; } } void __init check_bugs32(void) { check_errata(); } /* * Probe whether cpu has config register by trying to play with * alternate cache bit and see whether it matters. * It's used by cpu_probe to distinguish between R3000A and R3081. */ static inline int cpu_has_confreg(void) { #ifdef CONFIG_CPU_R3000 extern unsigned long r3k_cache_size(unsigned long); unsigned long size1, size2; unsigned long cfg = read_c0_conf(); size1 = r3k_cache_size(ST0_ISC); write_c0_conf(cfg ^ R30XX_CONF_AC); size2 = r3k_cache_size(ST0_ISC); write_c0_conf(cfg); return size1 != size2; #else return 0; #endif } static inline void set_elf_platform(int cpu, const char *plat) { if (cpu == 0) __elf_platform = plat; } /* * Get the FPU Implementation/Revision. */ static inline unsigned long cpu_get_fpu_id(void) { unsigned long tmp, fpu_id; tmp = read_c0_status(); __enable_fpu(); fpu_id = read_32bit_cp1_register(CP1_REVISION); write_c0_status(tmp); return fpu_id; } /* * Check the CPU has an FPU the official way. */ static inline int __cpu_has_fpu(void) { return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE); } static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) { #ifdef __NEED_VMBITS_PROBE write_c0_entryhi(0x3fffffffffffe000ULL); back_to_back_c0_hazard(); c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); #endif } static void set_isa(struct cpuinfo_mips *c, unsigned int isa) { switch (isa) { case MIPS_CPU_ISA_M64R2: c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; case MIPS_CPU_ISA_M64R1: c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; case MIPS_CPU_ISA_V: c->isa_level |= MIPS_CPU_ISA_V; case MIPS_CPU_ISA_IV: c->isa_level |= MIPS_CPU_ISA_IV; case MIPS_CPU_ISA_III: c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; break; case MIPS_CPU_ISA_M32R2: c->isa_level |= MIPS_CPU_ISA_M32R2; case MIPS_CPU_ISA_M32R1: c->isa_level |= MIPS_CPU_ISA_M32R1; case MIPS_CPU_ISA_II: c->isa_level |= MIPS_CPU_ISA_II; break; } } static char unknown_isa[] = KERN_ERR \ "Unsupported ISA type, c0.config0: %d."; static inline unsigned int decode_config0(struct cpuinfo_mips *c) { unsigned int config0; int isa; config0 = read_c0_config(); if (((config0 & MIPS_CONF_MT) >> 7) == 1) c->options |= MIPS_CPU_TLB; isa = (config0 & MIPS_CONF_AT) >> 13; switch (isa) { case 0: switch ((config0 & MIPS_CONF_AR) >> 10) { case 0: set_isa(c, MIPS_CPU_ISA_M32R1); break; case 1: set_isa(c, MIPS_CPU_ISA_M32R2); break; default: goto unknown; } break; case 2: switch ((config0 & MIPS_CONF_AR) >> 10) { case 0: set_isa(c, MIPS_CPU_ISA_M64R1); break; case 1: set_isa(c, MIPS_CPU_ISA_M64R2); break; default: goto unknown; } break; default: goto unknown; } return config0 & MIPS_CONF_M; unknown: panic(unknown_isa, config0); } static inline unsigned int decode_config1(struct cpuinfo_mips *c) { unsigned int config1; config1 = read_c0_config1(); if (config1 & MIPS_CONF1_MD) c->ases |= MIPS_ASE_MDMX; if (config1 & MIPS_CONF1_WR) c->options |= MIPS_CPU_WATCH; if (config1 & MIPS_CONF1_CA) c->ases |= MIPS_ASE_MIPS16; if (config1 & MIPS_CONF1_EP) c->options |= MIPS_CPU_EJTAG; if (config1 & MIPS_CONF1_FP) { c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_32FPR; } if (cpu_has_tlb) c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; return config1 & MIPS_CONF_M; } static inline unsigned int decode_config2(struct cpuinfo_mips *c) { unsigned int config2; config2 = read_c0_config2(); if (config2 & MIPS_CONF2_SL) c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; return config2 & MIPS_CONF_M; } static inline unsigned int decode_config3(struct cpuinfo_mips *c) { unsigned int config3; config3 = read_c0_config3(); if (config3 & MIPS_CONF3_SM) { c->ases |= MIPS_ASE_SMARTMIPS; c->options |= MIPS_CPU_RIXI; } if (config3 & MIPS_CONF3_RXI) c->options |= MIPS_CPU_RIXI; if (config3 & MIPS_CONF3_DSP) c->ases |= MIPS_ASE_DSP; if (config3 & MIPS_CONF3_DSP2P) c->ases |= MIPS_ASE_DSP2P; if (config3 & MIPS_CONF3_VINT) c->options |= MIPS_CPU_VINT; if (config3 & MIPS_CONF3_VEIC) c->options |= MIPS_CPU_VEIC; if (config3 & MIPS_CONF3_MT) c->ases |= MIPS_ASE_MIPSMT; if (config3 & MIPS_CONF3_ULRI) c->options |= MIPS_CPU_ULRI; if (config3 & MIPS_CONF3_ISA) c->options |= MIPS_CPU_MICROMIPS; if (config3 & MIPS_CONF3_VZ) c->ases |= MIPS_ASE_VZ; return config3 & MIPS_CONF_M; } static inline unsigned int decode_config4(struct cpuinfo_mips *c) { unsigned int config4; config4 = read_c0_config4(); if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT && cpu_has_tlb) c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; c->kscratch_mask = (config4 >> 16) & 0xff; return config4 & MIPS_CONF_M; } static inline unsigned int decode_config5(struct cpuinfo_mips *c) { unsigned int config5; config5 = read_c0_config5(); config5 &= ~MIPS_CONF5_UFR; write_c0_config5(config5); return config5 & MIPS_CONF_M; } static void decode_configs(struct cpuinfo_mips *c) { int ok; /* MIPS32 or MIPS64 compliant CPU. */ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; ok = decode_config0(c); /* Read Config registers. */ BUG_ON(!ok); /* Arch spec violation! */ if (ok) ok = decode_config1(c); if (ok) ok = decode_config2(c); if (ok) ok = decode_config3(c); if (ok) ok = decode_config4(c); if (ok) ok = decode_config5(c); mips_probe_watch_registers(c); if (cpu_has_mips_r2) c->core = read_c0_ebase() & 0x3ff; } #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) { switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_R2000: c->cputype = CPU_R2000; __cpu_name[cpu] = "R2000"; c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; break; case PRID_IMP_R3000: if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { if (cpu_has_confreg()) { c->cputype = CPU_R3081E; __cpu_name[cpu] = "R3081"; } else { c->cputype = CPU_R3000A; __cpu_name[cpu] = "R3000A"; } } else { c->cputype = CPU_R3000; __cpu_name[cpu] = "R3000"; } c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400) { c->cputype = CPU_R4400PC; __cpu_name[cpu] = "R4400PC"; } else { c->cputype = CPU_R4000PC; __cpu_name[cpu] = "R4000PC"; } } else { int cca = read_c0_config() & CONF_CM_CMASK; int mc; /* * SC and MC versions can't be reliably told apart, * but only the latter support coherent caching * modes so assume the firmware has set the KSEG0 * coherency attribute reasonably (if uncached, we * assume SC). */ switch (cca) { case CONF_CM_CACHABLE_CE: case CONF_CM_CACHABLE_COW: case CONF_CM_CACHABLE_CUW: mc = 1; break; default: mc = 0; break; } if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400) { c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; } else { c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; } } set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_VCE | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_VR41XX: set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS; c->tlbsize = 32; switch (c->processor_id & 0xf0) { case PRID_REV_VR4111: c->cputype = CPU_VR4111; __cpu_name[cpu] = "NEC VR4111"; break; case PRID_REV_VR4121: c->cputype = CPU_VR4121; __cpu_name[cpu] = "NEC VR4121"; break; case PRID_REV_VR4122: if ((c->processor_id & 0xf) < 0x3) { c->cputype = CPU_VR4122; __cpu_name[cpu] = "NEC VR4122"; } else { c->cputype = CPU_VR4181A; __cpu_name[cpu] = "NEC VR4181A"; } break; case PRID_REV_VR4130: if ((c->processor_id & 0xf) < 0x4) { c->cputype = CPU_VR4131; __cpu_name[cpu] = "NEC VR4131"; } else { c->cputype = CPU_VR4133; c->options |= MIPS_CPU_LLSC; __cpu_name[cpu] = "NEC VR4133"; } break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); c->cputype = CPU_VR41XX; __cpu_name[cpu] = "NEC Vr41xx"; break; } break; case PRID_IMP_R4300: c->cputype = CPU_R4300; __cpu_name[cpu] = "R4300"; set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_R4600: c->cputype = CPU_R4600; __cpu_name[cpu] = "R4600"; set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 48; break; #if 0 case PRID_IMP_R4650: /* * This processor doesn't have an MMU, so it's not * "real easy" to run Linux on it. It is left purely * for documentation. Commented out because it shares * it's c0_prid id number with the TX3900. */ c->cputype = CPU_R4650; __cpu_name[cpu] = "R4650"; set_isa(c, MIPS_CPU_ISA_III); c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; break; #endif case PRID_IMP_TX39: c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; __cpu_name[cpu] = "TX3927"; c->tlbsize = 64; } else { switch (c->processor_id & PRID_REV_MASK) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; __cpu_name[cpu] = "TX3912"; c->tlbsize = 32; break; case PRID_REV_TX3922: c->cputype = CPU_TX3922;