#ifndef _ASM_X86_PROCESSOR_H#define _ASM_X86_PROCESSOR_H #include <asm/processor-flags.h> /* Forward declaration, a strange C thing */struct task_struct;struct mm_struct; #include <asm/vm86.h>#include <asm/math_emu.h>#include <asm/segment.h>#include <asm/types.h>#include <asm/sigcontext.h>#include <asm/current.h>#include <asm/cpufeature.h>#include <asm/page.h>#include <asm/pgtable_types.h>#include <asm/percpu.h>#include <asm/msr.h>#include <asm/desc_defs.h>#include <asm/nops.h>#include <asm/special_insns.h> #include <linux/personality.h>#include <linux/cpumask.h>#include <linux/cache.h>#include <linux/threads.h>#include <linux/math64.h>#include <linux/init.h>#include <linux/err.h>#include <linux/irqflags.h> /* * We handle most unaligned accesses in hardware.  On the other hand * unaligned DMA can be quite expensive on some Nehalem processors. * * Based on this we disable the IP header alignment in network drivers. */#define NET_IP_ALIGN	0 #define HBP_NUM 4/* * Default implementation of macro that returns current * instruction pointer ("program counter"). */static inline void *current_text_addr(void){	void *pc; 	asm volatile("mov $1f, %0; 1:":"=r" (pc)); 	return pc;} #ifdef CONFIG_X86_VSMP# define ARCH_MIN_TASKALIGN		(1 << INTERNODE_CACHE_SHIFT)# define ARCH_MIN_MMSTRUCT_ALIGN	(1 << INTERNODE_CACHE_SHIFT)#else# define ARCH_MIN_TASKALIGN		16# define ARCH_MIN_MMSTRUCT_ALIGN	0#endif enum tlb_infos {	ENTRIES,	NR_INFO}; extern u16 __read_mostly tlb_lli_4k[NR_INFO];extern u16 __read_mostly tlb_lli_2m[NR_INFO];extern u16 __read_mostly tlb_lli_4m[NR_INFO];extern u16 __read_mostly tlb_lld_4k[NR_INFO];extern u16 __read_mostly tlb_lld_2m[NR_INFO];extern u16 __read_mostly tlb_lld_4m[NR_INFO];extern s8  __read_mostly tlb_flushall_shift; /* *  CPU type and hardware bug flags. Kept separately for each CPU. *  Members of this structure are referenced in head.S, so think twice *  before touching them. [mj] */ struct cpuinfo_x86 {	__u8			x86;		/* CPU family */	__u8			x86_vendor;	/* CPU vendor */	__u8			x86_model;	__u8			x86_mask;#ifdef CONFIG_X86_32	char			wp_works_ok;	/* It doesn't on 386's */ 	/* Problems on some 486Dx4's and old 386's: */	char			rfu;	char			pad0;	char			pad1;#else	/* Number of 4K pages in DTLB/ITLB combined(in pages): */	int			x86_tlbsize;#endif	__u8			x86_virt_bits;	__u8			x86_phys_bits;	/* CPUID returned core id bits: */	__u8			x86_coreid_bits;	/* Max extended CPUID function supported: */	__u32			extended_cpuid_level;	/* Maximum supported CPUID level, -1=no CPUID: */	int			cpuid_level;	__u32			x86_capability[NCAPINTS + NBUGINTS];	char			x86_vendor_id[16];	char			x86_model_id[64];	/* in KB - valid for CPUS which support this call: */	int			x86_cache_size;	int			x86_cache_alignment;	/* In bytes */	int			x86_power;	unsigned long		loops_per_jiffy;	/* cpuid returned max cores value: */	u16			 x86_max_cores;	u16			apicid;	u16			initial_apicid;	u16			x86_clflush_size;	/* number of cores as seen by the OS: */	u16			booted_cores;	/* Physical processor id: */	u16			phys_proc_id;	/* Core id: */	u16			cpu_core_id;	/* Compute unit id */	u8			compute_unit_id;	/* Index into per_cpu list: */	u16			cpu_index;	u32			microcode;} __attribute__((__aligned__(SMP_CACHE_BYTES))); #define X86_VENDOR_INTEL	0#define X86_VENDOR_CYRIX	1#define X86_VENDOR_AMD		2#define X86_VENDOR_UMC		3#define X86_VENDOR_CENTAUR	5#define X86_VENDOR_TRANSMETA	7#define X86_VENDOR_NSC		8#define X86_VENDOR_NUM		9 #define X86_VENDOR_UNKNOWN	0xff /* * capabilities of CPUs */extern struct cpuinfo_x86	boot_cpu_data;extern struct cpuinfo_x86	new_cpu_data; extern struct tss_struct	doublefault_tss;extern __u32			cpu_caps_cleared[NCAPINTS];extern __u32			cpu_caps_set[NCAPINTS]; #ifdef CONFIG_SMPDECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);#define cpu_data(cpu)		per_cpu(cpu_info, cpu)#else#define cpu_info		boot_cpu_data#define cpu_data(cpu)		boot_cpu_data#endif extern const struct seq_operations cpuinfo_op; #define cache_line_size()	(boot_cpu_data.x86_cache_alignment) extern void cpu_detect(struct cpuinfo_x86 *c);extern void fpu_detect(struct cpuinfo_x86 *c); extern void early_cpu_init(void);extern void identify_boot_cpu(void);extern void identify_secondary_cpu(struct cpuinfo_x86 *);extern void print_cpu_info(struct cpuinfo_x86 *);void print_cpu_msr(struct cpuinfo_x86 *);extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); extern void detect_extended_topology(struct cpuinfo_x86 *c);extern void detect_ht(struct cpuinfo_x86 *c); #ifdef CONFIG_X86_32extern int have_cpuid_p(void);#elsestatic inline int have_cpuid_p(void){	return 1;}#endifstatic inline void native_cpuid(unsigned int *eax, unsigned int *ebx,				unsigned int *ecx, unsigned int *edx){	/* ecx is often an input as well as an output. */	asm volatile("cpuid"	    : "=a" (*eax),	      "=b" (*ebx),	      "=c" (*ecx),	      "=d" (*edx)	    : "0" (*eax), "2" (*ecx)	    : "memory");} static inline void load_cr3(pgd_t *pgdir){	write_cr3(__pa(pgdir));} #ifdef CONFIG_X86_32/* This is the TSS defined by the hardware. */struct x86_hw_tss {	unsigned short		back_link, __blh;	unsigned long		sp0;	unsigned short		ss0, __ss0h;	unsigned long		sp1;	/* ss1 caches MSR_IA32_SYSENTER_CS: */	unsigned short		ss1, __ss1h;	unsigned long		sp2;	unsigned short		ss2, __ss2h;	unsigned long		__cr3;	unsigned long		ip;	unsigned long		flags;	unsigned long		ax;	unsigned long		cx;	unsigned long		dx;	unsigned long		bx;	unsigned long		sp;	unsigned long		bp;	unsigned long		si;	unsigned long		di;	unsigned short		es, __esh;	unsigned short		cs, __csh;	unsigned short		ss, __ssh;	unsigned short		ds, __dsh;	unsigned short		fs, __fsh;	unsigned short		gs, __gsh;	unsigned short		ldt, __ldth;	unsigned short		trace;	unsigned short		io_bitmap_base; } __attribute__((packed));#elsestruct x86_hw_tss {	u32			reserved1;	u64			sp0;	u64			sp1;	u64			sp2;	u64			reserved2;	u64			ist[7];	u32			reserved3;	u32			reserved4;	u16			reserved5;	u16			io_bitmap_base; } __attribute__((packed)) ____cacheline_aligned;#endif /* * IO-bitmap sizes: */#define IO_BITMAP_BITS			65536#define IO_BITMAP_BYTES			(IO_BITMAP_BITS/8)#define IO_BITMAP_LONGS			(IO_BITMAP_BYTES/sizeof(long))#define IO_BITMAP_OFFSET		offsetof(struct tss_struct, io_bitmap)#define INVALID_IO_BITMAP_OFFSET	0x8000 struct tss_struct {	/*	 * The hardware state:	 */	struct x86_hw_tss	x86_tss; 	/*	 * The extra 1 is there because the CPU will access an	 * additional byte beyond the end of the IO permission	 * bitmap. The extra byte must be all 1 bits, and must	 * be within the limit.	 */	unsigned long		io_bitmap[IO_BITMAP_LONGS + 1]; 	/*	 * .. and then another 0x100 bytes for the emergency kernel stack:	 */	unsigned long		stack[64]; } ____cacheline_aligned; DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss); /* * Save the original ist values for checking stack pointers during debugging */struct orig_ist {	unsigned long		ist[7];}; #define	MXCSR_DEFAULT		0x1f80 struct i387_fsave_struct {	u32			cwd;	/* FPU Control Word		*/	u32			swd;	/* FPU Status Word		*/	u32			twd;	/* FPU Tag Word			*/	u32			fip;	/* FPU IP Offset		*/	u32			fcs;	/* FPU IP Selector		*/	u32			foo;	/* FPU Operand Pointer Offset	*/	u32			fos;	/* FPU Operand Pointer Selector	*/ 	/* 8*10 bytes for each FP-reg = 80 bytes:			*/	u32			st_space[20]; 	/* Software status information [not touched by FSAVE ]:		*/	u32			status;}; struct i387_fxsave_struct {	u16			cwd; /* Control Word			*/	u16			swd; /* Status Word			*/	u16			twd; /* Tag Word			*/	u16			fop; /* Last Instruction Opcode		*/	union {		struct {			u64	rip; /* Instruction Pointer		*/			u64	rdp; /* Data Pointer			*/		};		struct {			u32	fip; /* FPU IP Offset			*/			u32	fcs; /* FPU IP Selector			*/			u32	foo; /* FPU Operand Offset		*/			u32	fos; /* FPU Operand Selector		*/		};	};	u32			mxcsr;		/* MXCSR Register State */	u32			mxcsr_mask;	/* MXCSR Mask		*/ 	/* 8*16 bytes for each FP-reg = 128 bytes:			*/	u32			st_space[32]; 	/* 16*16 bytes for each XMM-reg = 256 bytes:			*/	u32			xmm_space[64]; 	u32			padding[12]; 	union {		u32		padding1[12];		u32		sw_reserved[12];	}; } __attribute__((aligned(16))); struct i387_soft_struct {	u32			cwd;	u32			swd;	u32			twd;	u32			fip;	u32			fcs;	u32			foo;	u32			fos;	/* 8*10 bytes for each FP-reg = 80 bytes: */	u32			st_space[20];	u8			ftop;	u8			changed;	u8			lookahead;	u8			no_update;	u8			rm;	u8			alimit;	struct math_emu_info	*info;	u32			entry_eip;}; struct ymmh_struct {	/* 16 * 16 bytes for each YMMH-reg = 256 bytes */	u32 ymmh_space[64];}; struct xsave_hdr_struct {	u64 xstate_bv;	u64 reserved1[2];	u64 reserved2[5];} __attribute__((packed)); struct xsave_struct {	struct i387_fxsave_struct i387;	struct xsave_hdr_struct xsave_hdr;	struct ymmh_struct ymmh;	/* new processor state extensions will go here */} __attribute__ ((packed, aligned (64))); union thread_xstate {	struct i387_fsave_struct	fsave;	struct i387_fxsave_struct	fxsave;	struct i387_soft_struct		soft;	struct xsave_struct		xsave;}; struct fpu {	unsigned int last_cpu;	unsigned int has_fpu;	union thread_xstate *state;}; #ifdef CONFIG_X86_64DECLARE_PER_CPU(struct orig_ist, orig_ist); union irq_stack_union {	char irq_stack[IRQ_STACK_SIZE];	/*	 * GCC hardcodes the stack canary as %gs:40.  Since the	 * irq_stack is the object at %gs:0, we reserve the bottom	 * 48 bytes of the irq stack for the canary.	 */	struct {		char gs_base[40];		unsigned long stack_canary;	};}; DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;DECLARE_INIT_PER_CPU(irq_stack_union); DECLARE_PER_CPU(char *, irq_stack_ptr);DECLARE_PER_CPU(unsigned int, irq_count);extern asmlinkage void ignore_sysret(void);#else	/* X86_64 */#ifdef CONFIG_CC_STACKPROTECTOR/* * Make sure stack canary segment base is cached-aligned: *   "For Intel Atom processors, avoid non zero segment base address *    that is not aligned to cache line boundary at all cost." * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) */struct stack_canary {	char __pad[20];		/* canary at %gs:20 */	unsigned long canary;};DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);#endif#endif	/* X86_64 */ extern unsigned int xstate_size;extern void free_thread_xstate(struct task_struct *);extern struct kmem_cache *task_xstate_cachep; struct perf_event; struct thread_struct {	/* Cached TLS descriptors: */	struct desc_struct	tls_array[GDT_ENTRY_TLS_ENTRIES];	unsigned long		sp0;	unsigned long		sp;#ifdef CONFIG_X86_32	unsigned long		sysenter_cs;#else	unsigned long		usersp;	/* Copy from PDA */	unsigned short		es;	unsigned short		ds;	unsigned short		fsindex;	unsigned short		gsindex;#endif#ifdef CONFIG_X86_32	unsigned long		ip;#endif#ifdef CONFIG_X86_64	unsigned long		fs;#endif	unsigned long		gs;	/* Save middle states of ptrace breakpoints */	struct perf_event	*ptrace_bps[HBP_NUM];	/* Debug status used for traps, single steps, etc... */	unsigned long           debugreg6;	/* Keep track of the exact dr7 value set by the user */	unsigned long           ptrace_dr7;	/* Fault info: */	unsigned long		cr2;	unsigned long		trap_nr;	unsigned long		error_code;	/* floating point and extended processor state */	struct fpu		fpu;#ifdef CONFIG_X86_32	/* Virtual 86 mode info */	struct vm86_struct __user *vm86_info;	unsigned long		screen_bitmap;	unsigned long		v86flags;	unsigned long		v86mask;	unsigned long		saved_sp0;	unsigned int		saved_fs;	unsigned int		saved_gs;#endif	/* IO permissions: */	unsigned long		*io_bitmap_ptr;	unsigned long		iopl;	/* Max allowed port in the bitmap, in bytes: */	unsigned		io_bitmap_max;	/*	 * fpu_counter contains the number of consecutive context switches	 * that the FPU is used. If this is over a threshold, the lazy fpu	 * saving becomes unlazy to save the trap. This is an unsigned char	 * so that after 256 times the counter wraps and the behavior turns	 * lazy again; this to deal with bursty apps that only use FPU for	 * a short time	 */	unsigned char fpu_counter;};

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