/* * EMIF driver * * Copyright (C) 2012 Texas Instruments, Inc. * * Aneesh V <aneesh@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */#include <linux/err.h>#include <linux/kernel.h>#include <linux/reboot.h>#include <linux/platform_data/emif_plat.h>#include <linux/io.h>#include <linux/device.h>#include <linux/platform_device.h>#include <linux/interrupt.h>#include <linux/slab.h>#include <linux/of.h>#include <linux/debugfs.h>#include <linux/seq_file.h>#include <linux/module.h>#include <linux/list.h>#include <linux/spinlock.h>#include <linux/pm.h>#include <memory/jedec_ddr.h>#include "emif.h"#include "of_memory.h" /** * struct emif_data - Per device static data for driver's use * @duplicate:			Whether the DDR devices attached to this EMIF *				instance are exactly same as that on EMIF1. In *				this case we can save some memory and processing * @temperature_level:		Maximum temperature of LPDDR2 devices attached *				to this EMIF - read from MR4 register. If there *				are two devices attached to this EMIF, this *				value is the maximum of the two temperature *				levels. * @node:			node in the device list * @base:			base address of memory-mapped IO registers. * @dev:			device pointer. * @addressing			table with addressing information from the spec * @regs_cache:			An array of 'struct emif_regs' that stores *				calculated register values for different *				frequencies, to avoid re-calculating them on *				each DVFS transition. * @curr_regs:			The set of register values used in the last *				frequency change (i.e. corresponding to the *				frequency in effect at the moment) * @plat_data:			Pointer to saved platform data. * @debugfs_root:		dentry to the root folder for EMIF in debugfs * @np_ddr:			Pointer to ddr device tree node */struct emif_data {	u8				duplicate;	u8				temperature_level;	u8				lpmode;	struct list_head		node;	unsigned long			irq_state;	void __iomem			*base;	struct device			*dev;	const struct lpddr2_addressing	*addressing;	struct emif_regs		*regs_cache[EMIF_MAX_NUM_FREQUENCIES];	struct emif_regs		*curr_regs;	struct emif_platform_data	*plat_data;	struct dentry			*debugfs_root;	struct device_node		*np_ddr;}; static struct emif_data *emif1;static spinlock_t	emif_lock;static unsigned long	irq_state;static u32		t_ck; /* DDR clock period in ps */static LIST_HEAD(device_list); #ifdef CONFIG_DEBUG_FSstatic void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,	struct emif_regs *regs){	u32 type = emif->plat_data->device_info->type;	u32 ip_rev = emif->plat_data->ip_rev; 	seq_printf(s, "EMIF register cache dump for %dMHz\n",		regs->freq/1000000); 	seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);	seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);	seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);	seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw); 	if (ip_rev == EMIF_4D) {		seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",			regs->read_idle_ctrl_shdw_normal);		seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",			regs->read_idle_ctrl_shdw_volt_ramp);	} else if (ip_rev == EMIF_4D5) {		seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",			regs->dll_calib_ctrl_shdw_normal);		seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",			regs->dll_calib_ctrl_shdw_volt_ramp);	} 	if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {		seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",			regs->ref_ctrl_shdw_derated);		seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",			regs->sdram_tim1_shdw_derated);		seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",			regs->sdram_tim3_shdw_derated);	}} static int emif_regdump_show(struct seq_file *s, void *unused){	struct emif_data	*emif	= s->private;	struct emif_regs	**regs_cache;	int			i; 	if (emif->duplicate)		regs_cache = emif1->regs_cache;	else		regs_cache = emif->regs_cache; 	for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {		do_emif_regdump_show(s, emif, regs_cache[i]);		seq_printf(s, "\n");	} 	return 0;} static int emif_regdump_open(struct inode *inode, struct file *file){	return single_open(file, emif_regdump_show, inode->i_private);} static const struct file_operations emif_regdump_fops = {	.open			= emif_regdump_open,	.read			= seq_read,	.release		= single_release,}; static int emif_mr4_show(struct seq_file *s, void *unused){	struct emif_data *emif = s->private; 	seq_printf(s, "MR4=%d\n", emif->temperature_level);	return 0;} static int emif_mr4_open(struct inode *inode, struct file *file){	return single_open(file, emif_mr4_show, inode->i_private);} static const struct file_operations emif_mr4_fops = {	.open			= emif_mr4_open,	.read			= seq_read,	.release		= single_release,}; static int __init_or_module emif_debugfs_init(struct emif_data *emif){	struct dentry	*dentry;	int		ret; 	dentry = debugfs_create_dir(dev_name(emif->dev), NULL);	if (!dentry) {		ret = -ENOMEM;		goto err0;	}	emif->debugfs_root = dentry; 	dentry = debugfs_create_file("regcache_dump", S_IRUGO,			emif->debugfs_root, emif, &emif_regdump_fops);	if (!dentry) {		ret = -ENOMEM;		goto err1;	} 	dentry = debugfs_create_file("mr4", S_IRUGO,			emif->debugfs_root, emif, &emif_mr4_fops);	if (!dentry) {		ret = -ENOMEM;		goto err1;	} 	return 0;err1:	debugfs_remove_recursive(emif->debugfs_root);err0:	return ret;} static void __exit emif_debugfs_exit(struct emif_data *emif){	debugfs_remove_recursive(emif->debugfs_root);	emif->debugfs_root = NULL;}#elsestatic inline int __init_or_module emif_debugfs_init(struct emif_data *emif){	return 0;} static inline void __exit emif_debugfs_exit(struct emif_data *emif){}#endif /* * Calculate the period of DDR clock from frequency value */static void set_ddr_clk_period(u32 freq){	/* Divide 10^12 by frequency to get period in ps */	t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);} /* * Get bus width used by EMIF. Note that this may be different from the * bus width of the DDR devices used. For instance two 16-bit DDR devices * may be connected to a given CS of EMIF. In this case bus width as far * as EMIF is concerned is 32, where as the DDR bus width is 16 bits. */static u32 get_emif_bus_width(struct emif_data *emif){	u32		width;	void __iomem	*base = emif->base; 	width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)			>> NARROW_MODE_SHIFT;	width = width == 0 ? 32 : 16; 	return width;} /* * Get the CL from SDRAM_CONFIG register */static u32 get_cl(struct emif_data *emif){	u32		cl;	void __iomem	*base = emif->base; 	cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT; 	return cl;} static void set_lpmode(struct emif_data *emif, u8 lpmode){	u32 temp;	void __iomem *base = emif->base; 	/*	 * Workaround for errata i743 - LPDDR2 Power-Down State is Not	 * Efficient	 *	 * i743 DESCRIPTION:	 * The EMIF supports power-down state for low power. The EMIF	 * automatically puts the SDRAM into power-down after the memory is	 * not accessed for a defined number of cycles and the	 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.	 * As the EMIF supports automatic output impedance calibration, a ZQ	 * calibration long command is issued every time it exits active	 * power-down and precharge power-down modes. The EMIF waits and	 * blocks any other command during this calibration.	 * The EMIF does not allow selective disabling of ZQ calibration upon	 * exit of power-down mode. Due to very short periods of power-down	 * cycles, ZQ calibration overhead creates bandwidth issues and	 * increases overall system power consumption. On the other hand,	 * issuing ZQ calibration long commands when exiting self-refresh is	 * still required.	 *	 * WORKAROUND	 * Because there is no power consumption benefit of the power-down due	 * to the calibration and there is a performance risk, the guideline	 * is to not allow power-down state and, therefore, to not have set	 * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.	 */	if ((emif->plat_data->ip_rev == EMIF_4D) &&	    (EMIF_LP_MODE_PWR_DN == lpmode)) {		WARN_ONCE(1,			  "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by"			  "erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");		/* rollback LP_MODE to Self-refresh mode */		lpmode = EMIF_LP_MODE_SELF_REFRESH;	} 	temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);	temp &= ~LP_MODE_MASK;	temp |= (lpmode << LP_MODE_SHIFT);	writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);} static void do_freq_update(void){	struct emif_data *emif; 	/*	 * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE	 *	 * i728 DESCRIPTION:	 * The EMIF automatically puts the SDRAM into self-refresh mode	 * after the EMIF has not performed accesses during	 * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles	 * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set	 * to 0x2. If during a small window the following three events	 * occur:	 * - The SR_TIMING counter expires	 * - And frequency change is requested	 * - And OCP access is requested	 * Then it causes instable clock on the DDR interface.	 *	 * WORKAROUND	 * To avoid the occurrence of the three events, the workaround	 * is to disable the self-refresh when requesting a frequency	 * change. Before requesting a frequency change the software must	 * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the	 * frequency change has been done, the software can reprogram	 * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2	 */	list_for_each_entry(emif, &device_list, node) {		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)			set_lpmode(emif, EMIF_LP_MODE_DISABLE);	} 	/*	 * TODO: Do FREQ_UPDATE here when an API	 * is available for this as part of the new	 * clock framework	 */ 	list_for_each_entry(emif, &device_list, node) {		if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)			set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);	}} /* Find addressing table entry based on the device's type and density */static const struct lpddr2_addressing *get_addressing_table(	const struct ddr_device_info *device_info){	u32		index, type, density; 	type = device_info->type;	density = device_info->density; 	switch (type) {	case DDR_TYPE_LPDDR2_S4:		index = density - 1;		break;	case DDR_TYPE_LPDDR2_S2:		switch (density) {		case DDR_DENSITY_1Gb:		case DDR_DENSITY_2Gb:			index = density + 3;			break;		default:			index = density - 1;		}		break;	default:		return NULL;	} 	return &lpddr2_jedec_addressing_table[index];} /* * Find the the right timing table from the array of timing * tables of the device using DDR clock frequency */static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,		u32 freq){	u32				i, min, max, freq_nearest;	const struct lpddr2_timings	*timings = NULL;	const struct lpddr2_timings	*timings_arr = emif->plat_data->timings;	struct				device *dev = emif->dev; 	/* Start with a very high frequency - 1GHz */	freq_nearest = 1000000000; 	/*	 * Find the timings table such that:	 *  1. the frequency range covers the required frequency(safe) AND	 *  2. the max_freq is closest to the required frequency(optimal)	 */	for (i = 0; i < emif->plat_data->timings_arr_size; i++) {		max = timings_arr[i].max_freq;		min = timings_arr[i].min_freq;		if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {			freq_nearest = max;			timings = &timings_arr[i];		}	} 	if (!timings)		dev_err(dev, "%s: couldn't find timings for - %dHz\n",			__func__, freq); 	dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",		__func__, freq, freq_nearest); 	return timings;} static u32 get_sdram_ref_ctrl_shdw(u32 freq,		const struct lpddr2_addressing *addressing){	u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi; 	/* Scale down frequency and t_refi to avoid overflow */	freq_khz = freq / 1000;	t_refi = addressing->tREFI_ns / 100; 	/*	 * refresh rate to be set is 'tREFI(in us) * freq in MHz	 * division by 10000 to account for change in units	 */	val = t_refi * freq_khz / 10000;	ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT; 	return ref_ctrl_shdw;} static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,		const struct lpddr2_min_tck *min_tck,		const struct lpddr2_addressing *addressing){	u32 tim1 = 0, val = 0; 	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;	tim1 |= val << T_WTR_SHIFT; 	if (addressing->num_banks == B8)		val = DIV_ROUND_UP(timings->tFAW, t_ck*4);	else		val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));	tim1 |= (val - 1) << T_RRD_SHIFT; 	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;	tim1 |= val << T_RC_SHIFT; 	val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));	tim1 |= (val - 1) << T_RAS_SHIFT; 	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;	tim1 |= val << T_WR_SHIFT; 	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;	tim1 |= val << T_RCD_SHIFT; 	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;	tim1 |= val << T_RP_SHIFT; 	return tim1;} static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,		const struct lpddr2_min_tck *min_tck,		const struct lpddr2_addressing *addressing){	u32 tim1 = 0, val = 0; 	val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;	tim1 = val << T_WTR_SHIFT; 	/*	 * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps	 * to tFAW for de-rating	 */	if (addressing->num_banks == B8) {		val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;	} else {		val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);		val = max(min_tck->tRRD, val) - 1;	}	tim1 |= val << T_RRD_SHIFT; 	val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);	tim1 |= (val - 1) << T_RC_SHIFT; 	val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);	val = max(min_tck->tRASmin, val) - 1;	tim1 |= val << T_RAS_SHIFT; 	val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;	tim1 |= val << T_WR_SHIFT; 	val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));	tim1 |= (val - 1) << T_RCD_SHIFT; 	val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));

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