=========================Dynamic DMA mapping Guide========================= :Author: David S. Miller <davem@redhat.com>:Author: Richard Henderson <rth@cygnus.com>:Author: Jakub Jelinek <jakub@redhat.com> This is a guide to device driver writers on how to use the DMA APIwith example pseudo-code.  For a concise description of the API, seeDMA-API.txt. CPU and DMA addresses===================== There are several kinds of addresses involved in the DMA API, and it'simportant to understand the differences. The kernel normally uses virtual addresses.  Any address returned bykmalloc(), vmalloc(), and similar interfaces is a virtual address and canbe stored in a ``void *``. The virtual memory system (TLB, page tables, etc.) translates virtualaddresses to CPU physical addresses, which are stored as "phys_addr_t" or"resource_size_t".  The kernel manages device resources like registers asphysical addresses.  These are the addresses in /proc/iomem.  The physicaladdress is not directly useful to a driver; it must use ioremap() to mapthe space and produce a virtual address. I/O devices use a third kind of address: a "bus address".  If a device hasregisters at an MMIO address, or if it performs DMA to read or write systemmemory, the addresses used by the device are bus addresses.  In somesystems, bus addresses are identical to CPU physical addresses, but ingeneral they are not.  IOMMUs and host bridges can produce arbitrarymappings between physical and bus addresses. From a device's point of view, DMA uses the bus address space, but it maybe restricted to a subset of that space.  For example, even if a systemsupports 64-bit addresses for main memory and PCI BARs, it may use an IOMMUso devices only need to use 32-bit DMA addresses. Here's a picture and some examples::                CPU                  CPU                  Bus             Virtual              Physical             Address             Address              Address               Space              Space                Space             +-------+             +------+             +------+            |       |             |MMIO  |   Offset    |      |            |       |  Virtual    |Space |   applied   |      |          C +-------+ --------> B +------+ ----------> +------+ A            |       |  mapping    |      |   by host   |      |  +-----+   |       |             |      |   bridge    |      |   +--------+  |     |   |       |             +------+             |      |   |        |  | CPU |   |       |             | RAM  |             |      |   | Device |  |     |   |       |             |      |             |      |   |        |  +-----+   +-------+             +------+             +------+   +--------+            |       |  Virtual    |Buffer|   Mapping   |      |          X +-------+ --------> Y +------+ <---------- +------+ Z            |       |  mapping    | RAM  |   by IOMMU            |       |             |      |            |       |             |      |            +-------+             +------+ During the enumeration process, the kernel learns about I/O devices andtheir MMIO space and the host bridges that connect them to the system.  Forexample, if a PCI device has a BAR, the kernel reads the bus address (A)from the BAR and converts it to a CPU physical address (B).  The address Bis stored in a struct resource and usually exposed via /proc/iomem.  When adriver claims a device, it typically uses ioremap() to map physical addressB at a virtual address (C).  It can then use, e.g., ioread32(C), to accessthe device registers at bus address A. If the device supports DMA, the driver sets up a buffer using kmalloc() ora similar interface, which returns a virtual address (X).  The virtualmemory system maps X to a physical address (Y) in system RAM.  The drivercan use virtual address X to access the buffer, but the device itselfcannot because DMA doesn't go through the CPU virtual memory system. In some simple systems, the device can do DMA directly to physical addressY.  But in many others, there is IOMMU hardware that translates DMAaddresses to physical addresses, e.g., it translates Z to Y.  This is partof the reason for the DMA API: the driver can give a virtual address X toan interface like dma_map_single(), which sets up any required IOMMUmapping and returns the DMA address Z.  The driver then tells the device todo DMA to Z, and the IOMMU maps it to the buffer at address Y in systemRAM. So that Linux can use the dynamic DMA mapping, it needs some help from thedrivers, namely it has to take into account that DMA addresses should bemapped only for the time they are actually used and unmapped after the DMAtransfer. The following API will work of course even on platforms where no suchhardware exists. Note that the DMA API works with any bus independent of the underlyingmicroprocessor architecture. You should use the DMA API rather than thebus-specific DMA API, i.e., use the dma_map_*() interfaces rather than thepci_map_*() interfaces. First of all, you should make sure:: 	#include <linux/dma-mapping.h> is in your driver, which provides the definition of dma_addr_t.  This typecan hold any valid DMA address for the platform and should be usedeverywhere you hold a DMA address returned from the DMA mapping functions. What memory is DMA'able?======================== The first piece of information you must know is what kernel memory canbe used with the DMA mapping facilities.  There has been an unwrittenset of rules regarding this, and this text is an attempt to finallywrite them down. If you acquired your memory via the page allocator(i.e. __get_free_page*()) or the generic memory allocators(i.e. kmalloc() or kmem_cache_alloc()) then you may DMA to/fromthat memory using the addresses returned from those routines. This means specifically that you may _not_ use the memory/addressesreturned from vmalloc() for DMA.  It is possible to DMA to the_underlying_ memory mapped into a vmalloc() area, but this requireswalking page tables to get the physical addresses, and thentranslating each of those pages back to a kernel address usingsomething like __va().  [ EDIT: Update this when we integrateGerd Knorr's generic code which does this. ] This rule also means that you may use neither kernel image addresses(items in data/text/bss segments), nor module image addresses, norstack addresses for DMA.  These could all be mapped somewhere entirelydifferent than the rest of physical memory.  Even if those classes ofmemory could physically work with DMA, you'd need to ensure the I/Obuffers were cacheline-aligned.  Without that, you'd see cachelinesharing problems (data corruption) on CPUs with DMA-incoherent caches.(The CPU could write to one word, DMA would write to a different onein the same cache line, and one of them could be overwritten.) Also, this means that you cannot take the return of a kmap()call and DMA to/from that.  This is similar to vmalloc(). What about block I/O and networking buffers?  The block I/O andnetworking subsystems make sure that the buffers they use are validfor you to DMA from/to. DMA addressing limitations========================== Does your device have any DMA addressing limitations?  For example, isyour device only capable of driving the low order 24-bits of address?If so, you need to inform the kernel of this fact. By default, the kernel assumes that your device can address the full32-bits.  For a 64-bit capable device, this needs to be increased.And for a device with limitations, as discussed in the previousparagraph, it needs to be decreased. Special note about PCI: PCI-X specification requires PCI-X devices tosupport 64-bit addressing (DAC) for all transactions.  And at leastone platform (SGI SN2) requires 64-bit consistent allocations tooperate correctly when the IO bus is in PCI-X mode. For correct operation, you must interrogate the kernel in your deviceprobe routine to see if the DMA controller on the machine can properlysupport the DMA addressing limitation your device has.  It is goodstyle to do this even if your device holds the default setting,because this shows that you did think about these issues wrt. yourdevice. The query is performed via a call to dma_set_mask_and_coherent():: 	int dma_set_mask_and_coherent(struct device *dev, u64 mask); which will query the mask for both streaming and coherent APIs together.If you have some special requirements, then the following two separatequeries can be used instead: 	The query for streaming mappings is performed via a call to	dma_set_mask():: 		int dma_set_mask(struct device *dev, u64 mask); 	The query for consistent allocations is performed via a call	to dma_set_coherent_mask():: 		int dma_set_coherent_mask(struct device *dev, u64 mask); Here, dev is a pointer to the device struct of your device, and maskis a bit mask describing which bits of an address your devicesupports.  It returns zero if your card can perform DMA properly onthe machine given the address mask you provided.  In general, thedevice struct of your device is embedded in the bus-specific devicestruct of your device.  For example, &pdev->dev is a pointer to thedevice struct of a PCI device (pdev is a pointer to the PCI devicestruct of your device). If it returns non-zero, your device cannot perform DMA properly onthis platform, and attempting to do so will result in undefinedbehavior.  You must either use a different mask, or not use DMA. This means that in the failure case, you have three options: 1) Use another DMA mask, if possible (see below).2) Use some non-DMA mode for data transfer, if possible.3) Ignore this device and do not initialize it. It is recommended that your driver print a kernel KERN_WARNING messagewhen you end up performing either #2 or #3.  In this manner, if a userof your driver reports that performance is bad or that the device is noteven detected, you can ask them for the kernel messages to find outexactly why. The standard 32-bit addressing device would do something like this:: 	if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) {		dev_warn(dev, "mydev: No suitable DMA available\n");		goto ignore_this_device;	} Another common scenario is a 64-bit capable device.  The approach hereis to try for 64-bit addressing, but back down to a 32-bit mask thatshould not fail.  The kernel may fail the 64-bit mask not because theplatform is not capable of 64-bit addressing.  Rather, it may fail inthis case simply because 32-bit addressing is done more efficientlythan 64-bit addressing.  For example, Sparc64 PCI SAC addressing ismore efficient than DAC addressing. Here is how you would handle a 64-bit capable device which can driveall 64-bits when accessing streaming DMA:: 	int using_dac; 	if (!dma_set_mask(dev, DMA_BIT_MASK(64))) {		using_dac = 1;	} else if (!dma_set_mask(dev, DMA_BIT_MASK(32))) {		using_dac = 0;	} else {		dev_warn(dev, "mydev: No suitable DMA available\n");		goto ignore_this_device;	} If a card is capable of using 64-bit consistent allocations as well,the case would look like this:: 	int using_dac, consistent_using_dac; 	if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64))) {		using_dac = 1;		consistent_using_dac = 1;	} else if (!dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32))) {		using_dac = 0;		consistent_using_dac = 0;	} else {		dev_warn(dev, "mydev: No suitable DMA available\n");		goto ignore_this_device;	} The coherent mask will always be able to set the same or a smaller mask asthe streaming mask. However for the rare case that a device driver onlyuses consistent allocations, one would have to check the return value fromdma_set_coherent_mask(). Finally, if your device can only drive the low 24-bits ofaddress you might do something like:: 	if (dma_set_mask(dev, DMA_BIT_MASK(24))) {		dev_warn(dev, "mydev: 24-bit DMA addressing not available\n");		goto ignore_this_device;	} When dma_set_mask() or dma_set_mask_and_coherent() is successful, andreturns zero, the kernel saves away this mask you have provided.  Thekernel will use this information later when you make DMA mappings. There is a case which we are aware of at this time, which is worthmentioning in this documentation.  If your device supports multiplefunctions (for example a sound card provides playback and recordfunctions) and the various different functions have _different_DMA addressing limitations, you may wish to probe each mask andonly provide the functionality which the machine can handle.  Itis important that the last call to dma_set_mask() be for themost specific mask. Here is pseudo-code showing how this might be done:: 	#define PLAYBACK_ADDRESS_BITS	DMA_BIT_MASK(32)	#define RECORD_ADDRESS_BITS	DMA_BIT_MASK(24) 	struct my_sound_card *card;	struct device *dev; 	...	if (!dma_set_mask(dev, PLAYBACK_ADDRESS_BITS)) {		card->playback_enabled = 1;	} else {		card->playback_enabled = 0;		dev_warn(dev, "%s: Playback disabled due to DMA limitations\n",		       card->name);	}	if (!dma_set_mask(dev, RECORD_ADDRESS_BITS)) {		card->record_enabled = 1;	} else {		card->record_enabled = 0;		dev_warn(dev, "%s: Record disabled due to DMA limitations\n",		       card->name);	} A sound card was used as an example here because this genre of PCIdevices seems to be littered with ISA chips given a PCI front end,and thus retaining the 16MB DMA addressing limitations of ISA. Types of DMA mappings===================== There are two types of DMA mappings: - Consistent DMA mappings which are usually mapped at driver  initialization, unmapped at the end and for which the hardware should  guarantee that the device and the CPU can access the data  in parallel and will see updates made by each other without any  explicit software flushing.   Think of "consistent" as "synchronous" or "coherent".   The current default is to return consistent memory in the low 32  bits of the DMA space.  However, for future compatibility you should  set the consistent mask even if this default is fine for your  driver.   Good examples of what to use consistent mappings for are: 	- Network card DMA ring descriptors.	- SCSI adapter mailbox command data structures.	- Device firmware microcode executed out of	  main memory.   The invariant these examples all require is that any CPU store  to memory is immediately visible to the device, and vice  versa.  Consistent mappings guarantee this.   .. important:: 	     Consistent DMA memory does not preclude the usage of	     proper memory barriers.  The CPU may reorder stores to	     consistent memory just as it may normal memory.  Example:	     if it is important for the device to see the first word	     of a descriptor updated before the second, you must do	     something like:: 		desc->word0 = address;		wmb();		desc->word1 = DESC_VALID;              in order to get correct behavior on all platforms. 	     Also, on some platforms your driver may need to flush CPU write	     buffers in much the same way as it needs to flush write buffers	     found in PCI bridges (such as by reading a register's value	     after writing it). - Streaming DMA mappings which are usually mapped for one DMA  transfer, unmapped right after it (unless you use dma_sync_* below)  and for which hardware can optimize for sequential accesses.   Think of "streaming" as "asynchronous" or "outside the coherency  domain".   Good examples of what to use streaming mappings for are: 	- Networking buffers transmitted/received by a device.	- Filesystem buffers written/read by a SCSI device.   The interfaces for using this type of mapping were designed in  such a way that an implementation can make whatever performance  optimizations the hardware allows.  To this end, when using  such mappings you must be explicit about what you want to happen. Neither type of DMA mapping has alignment restrictions that come fromthe underlying bus, although some devices may have such restrictions.Also, systems with caches that aren't DMA-coherent will work betterwhen the underlying buffers don't share cache lines with other data.  Using Consistent DMA mappings============================= To allocate and map large (PAGE_SIZE or so) consistent DMA regions,you should do:: 	dma_addr_t dma_handle; 	cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp); where device is a ``struct device *``. This may be called in interruptcontext with the GFP_ATOMIC flag. Size is the length of the region you want to allocate, in bytes. This routine will allocate RAM for that region, so it acts similarly to__get_free_pages() (but takes size instead of a page order).  If yourdriver needs regions sized smaller than a page, you may prefer usingthe dma_pool interface, described below. The consistent DMA mapping interfaces, for non-NULL dev, will bydefault return a DMA address which is 32-bit addressable.  Even if thedevice indicates (via DMA mask) that it may address the upper 32-bits,consistent allocation will only return > 32-bit addresses for DMA ifthe consistent DMA mask has been explicitly changed viadma_set_coherent_mask().  This is true of the dma_pool interface aswell. dma_alloc_coherent() returns two values: the virtual address which youcan use to access it from the CPU and dma_handle which you pass to thecard. The CPU virtual address and the DMA address are bothguaranteed to be aligned to the smallest PAGE_SIZE order whichis greater than or equal to the requested size.  This invariantexists (for example) to guarantee that if you allocate a chunkwhich is smaller than or equal to 64 kilobytes, the extent of thebuffer you receive will not cross a 64K boundary. To unmap and free such a DMA region, you call:: 	dma_free_coherent(dev, size, cpu_addr, dma_handle); where dev, size are the same as in the above call and cpu_addr anddma_handle are the values dma_alloc_coherent() returned to you.This function may not be called in interrupt context. If your driver needs lots of smaller memory regions, you can writecustom code to subdivide pages returned by dma_alloc_coherent(),or you can use the dma_pool API to do that.  A dma_pool is likea kmem_cache, but it uses dma_alloc_coherent(), not __get_free_pages().Also, it understands common hardware constraints for alignment,like queue heads needing to be aligned on N byte boundaries. Create a dma_pool like this:: 	struct dma_pool *pool; 	pool = dma_pool_create(name, dev, size, align, boundary); The "name" is for diagnostics (like a kmem_cache name); dev and sizeare as above.  The device's hardware alignment requirement for thistype of data is "align" (which is expressed in bytes, and must be apower of two).  If your device has no boundary crossing restrictions,pass 0 for boundary; passing 4096 says memory allocated from this poolmust not cross 4KByte boundaries (but at that time it may be better touse dma_alloc_coherent() directly instead). Allocate memory from a DMA pool like this:: 	cpu_addr = dma_pool_alloc(pool, flags, &dma_handle); flags are GFP_KERNEL if blocking is permitted (not in_interrupt norholding SMP locks), GFP_ATOMIC otherwise.  Like dma_alloc_coherent(),this returns two values, cpu_addr and dma_handle. Free memory that was allocated from a dma_pool like this:: 	dma_pool_free(pool, cpu_addr, dma_handle); where pool is what you passed to dma_pool_alloc(), and cpu_addr anddma_handle are the values dma_pool_alloc() returned. This functionmay be called in interrupt context. Destroy a dma_pool by calling:: 	dma_pool_destroy(pool); Make sure you've called dma_pool_free() for all memory allocatedfrom a pool before you destroy the pool. This function may notbe called in interrupt context. DMA Direction============= The interfaces described in subsequent portions of this documenttake a DMA direction argument, which is an integer and takes onone of the following values::  DMA_BIDIRECTIONAL DMA_TO_DEVICE DMA_FROM_DEVICE DMA_NONE You should provide the exact DMA direction if you know it. DMA_TO_DEVICE means "from main memory to the device"DMA_FROM_DEVICE means "from the device to main memory"It is the direction in which the data moves during the DMAtransfer. You are _strongly_ encouraged to specify this as preciselyas you possibly can. 

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