/* * Exception handling for Microblaze * * Rewriten interrupt handling * * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> * Copyright (C) 2008-2009 PetaLogix * * uClinux customisation (C) 2005 John Williams * * MMU code derived from arch/ppc/kernel/head_4xx.S: * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org> * Initial PowerPC version. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> * Rewritten for PReP * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au> * Low-level exception handers, MMU support, and rewrite. * Copyright (C) 1997 Dan Malek <dmalek@jlc.net> * PowerPC 8xx modifications. * Copyright (C) 1998-1999 TiVo, Inc. * PowerPC 403GCX modifications. * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu> * PowerPC 403GCX/405GP modifications. * Copyright 2000 MontaVista Software Inc. * PPC405 modifications * PowerPC 403GCX/405GP modifications. * Author: MontaVista Software, Inc. * frank_rowand@mvista.com or source@mvista.com * debbie_chu@mvista.com * * Original code * Copyright (C) 2004 Xilinx, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. */ /* * Here are the handlers which don't require enabling translation * and calling other kernel code thus we can keep their design very simple * and do all processing in real mode. All what they need is a valid current * (that is an issue for the CONFIG_REGISTER_TASK_PTR case) * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore * these registers are saved/restored * The handlers which require translation are in entry.S --KAA * * Microblaze HW Exception Handler * - Non self-modifying exception handler for the following exception conditions * - Unalignment * - Instruction bus error * - Data bus error * - Illegal instruction opcode * - Divide-by-zero * * - Privileged instruction exception (MMU) * - Data storage exception (MMU) * - Instruction storage exception (MMU) * - Data TLB miss exception (MMU) * - Instruction TLB miss exception (MMU) * * Note we disable interrupts during exception handling, otherwise we will * possibly get multiple re-entrancy if interrupt handles themselves cause * exceptions. JW */ #include <asm/exceptions.h>#include <asm/unistd.h>#include <asm/page.h> #include <asm/entry.h>#include <asm/current.h>#include <linux/linkage.h> #include <asm/mmu.h>#include <asm/pgtable.h>#include <asm/signal.h>#include <asm/registers.h>#include <asm/asm-offsets.h> #undef DEBUG /* Helpful Macros */#define NUM_TO_REG(num) r ## num #ifdef CONFIG_MMU #define RESTORE_STATE \ lwi r5, r1, 0; \ mts rmsr, r5; \ nop; \ lwi r3, r1, PT_R3; \ lwi r4, r1, PT_R4; \ lwi r5, r1, PT_R5; \ lwi r6, r1, PT_R6; \ lwi r11, r1, PT_R11; \ lwi r31, r1, PT_R31; \ lwi r1, r1, PT_R1;#endif /* CONFIG_MMU */ #define LWREG_NOP \ bri ex_handler_unhandled; \ nop; #define SWREG_NOP \ bri ex_handler_unhandled; \ nop; /* FIXME this is weird - for noMMU kernel is not possible to use brid * instruction which can shorten executed time */ /* r3 is the source */#define R3_TO_LWREG_V(regnum) \ swi r3, r1, 4 * regnum; \ bri ex_handler_done; /* r3 is the source */#define R3_TO_LWREG(regnum) \ or NUM_TO_REG (regnum), r0, r3; \ bri ex_handler_done; /* r3 is the target */#define SWREG_TO_R3_V(regnum) \ lwi r3, r1, 4 * regnum; \ bri ex_sw_tail; /* r3 is the target */#define SWREG_TO_R3(regnum) \ or r3, r0, NUM_TO_REG (regnum); \ bri ex_sw_tail; #ifdef CONFIG_MMU #define R3_TO_LWREG_VM_V(regnum) \ brid ex_lw_end_vm; \ swi r3, r7, 4 * regnum; #define R3_TO_LWREG_VM(regnum) \ brid ex_lw_end_vm; \ or NUM_TO_REG (regnum), r0, r3; #define SWREG_TO_R3_VM_V(regnum) \ brid ex_sw_tail_vm; \ lwi r3, r7, 4 * regnum; #define SWREG_TO_R3_VM(regnum) \ brid ex_sw_tail_vm; \ or r3, r0, NUM_TO_REG (regnum); /* Shift right instruction depending on available configuration */ #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0 /* Only the used shift constants defined here - add more if needed */ #define BSRLI2(rD, rA) \ srl rD, rA; /* << 1 */ \ srl rD, rD; /* << 2 */ #define BSRLI4(rD, rA) \ BSRLI2(rD, rA); \ BSRLI2(rD, rD) #define BSRLI10(rD, rA) \ srl rD, rA; /* << 1 */ \ srl rD, rD; /* << 2 */ \ srl rD, rD; /* << 3 */ \ srl rD, rD; /* << 4 */ \ srl rD, rD; /* << 5 */ \ srl rD, rD; /* << 6 */ \ srl rD, rD; /* << 7 */ \ srl rD, rD; /* << 8 */ \ srl rD, rD; /* << 9 */ \ srl rD, rD /* << 10 */ #define BSRLI20(rD, rA) \ BSRLI10(rD, rA); \ BSRLI10(rD, rD) .macro bsrli, rD, rA, IMM .if (\IMM) == 2 BSRLI2(\rD, \rA) .elseif (\IMM) == 10 BSRLI10(\rD, \rA) .elseif (\IMM) == 12 BSRLI2(\rD, \rA) BSRLI10(\rD, \rD) .elseif (\IMM) == 14 BSRLI4(\rD, \rA) BSRLI10(\rD, \rD) .elseif (\IMM) == 20 BSRLI20(\rD, \rA) .elseif (\IMM) == 24 BSRLI4(\rD, \rA) BSRLI20(\rD, \rD) .elseif (\IMM) == 28 BSRLI4(\rD, \rA) BSRLI4(\rD, \rD) BSRLI20(\rD, \rD) .else .error "BSRLI shift macros \IMM" .endif .endm #endif #endif /* CONFIG_MMU */ .extern other_exception_handler /* Defined in exception.c */ /* * hw_exception_handler - Handler for exceptions * * Exception handler notes: * - Handles all exceptions * - Does not handle unaligned exceptions during load into r17, r1, r0. * - Does not handle unaligned exceptions during store from r17 (cannot be * done) and r1 (slows down common case) * * Relevant register structures * * EAR - |----|----|----|----|----|----|----|----| * - < ## 32 bit faulting address ## > * * ESR - |----|----|----|----|----| - | - |-----|-----| * - W S REG EXC * * * STACK FRAME STRUCTURE (for CONFIG_MMU=n) * ---------------------------------------- * * +-------------+ + 0 * | MSR | * +-------------+ + 4 * | r1 | * | . | * | . | * | . | * | . | * | r18 | * +-------------+ + 76 * | . | * | . | * * MMU kernel uses the same 'pt_pool_space' pointed space * which is used for storing register values - noMMu style was, that values were * stored in stack but in case of failure you lost information about register. * Currently you can see register value in memory in specific place. * In compare to with previous solution the speed should be the same. * * MMU exception handler has different handling compare to no MMU kernel. * Exception handler use jump table for directing of what happen. For MMU kernel * is this approach better because MMU relate exception are handled by asm code * in this file. In compare to with MMU expect of unaligned exception * is everything handled by C code. */ /* * every of these handlers is entered having R3/4/5/6/11/current saved on stack * and clobbered so care should be taken to restore them if someone is going to * return from exception */ /* wrappers to restore state before coming to entry.S */#ifdef CONFIG_MMU.section .data.align 4pt_pool_space: .space PT_SIZE #ifdef DEBUG/* Create space for exception counting. */.section .data.global exception_debug_table.align 4exception_debug_table: /* Look at exception vector table. There is 32 exceptions * word size */ .space (32 * 4)#endif /* DEBUG */ .section .rodata.align 4_MB_HW_ExceptionVectorTable:/* 0 - Undefined */ .long TOPHYS(ex_handler_unhandled)/* 1 - Unaligned data access exception */ .long TOPHYS(handle_unaligned_ex)/* 2 - Illegal op-code exception */ .long TOPHYS(full_exception_trapw)/* 3 - Instruction bus error exception */ .long TOPHYS(full_exception_trapw)/* 4 - Data bus error exception */ .long TOPHYS(full_exception_trapw)/* 5 - Divide by zero exception */ .long TOPHYS(full_exception_trapw)/* 6 - Floating point unit exception */ .long TOPHYS(full_exception_trapw)/* 7 - Privileged instruction exception */ .long TOPHYS(full_exception_trapw)/* 8 - 15 - Undefined */ .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled)/* 16 - Data storage exception */ .long TOPHYS(handle_data_storage_exception)/* 17 - Instruction storage exception */ .long TOPHYS(handle_instruction_storage_exception)/* 18 - Data TLB miss exception */ .long TOPHYS(handle_data_tlb_miss_exception)/* 19 - Instruction TLB miss exception */ .long TOPHYS(handle_instruction_tlb_miss_exception)/* 20 - 31 - Undefined */ .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled)#endif .global _hw_exception_handler.section .text.align 4.ent _hw_exception_handler_hw_exception_handler:#ifndef CONFIG_MMU addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */#else swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */ /* Save date to kernel memory. Here is the problem * when you came from user space */ ori r1, r0, TOPHYS(pt_pool_space);#endif swi r3, r1, PT_R3 swi r4, r1, PT_R4 swi r5, r1, PT_R5 swi r6, r1, PT_R6 #ifdef CONFIG_MMU swi r11, r1, PT_R11 swi r31, r1, PT_R31 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */#endif mfs r5, rmsr; nop swi r5, r1, 0; mfs r4, resr nop mfs r3, rear; nop #ifndef CONFIG_MMU andi r5, r4, 0x1000; /* Check ESR[DS] */ beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */ mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ nopnot_in_delay_slot: swi r17, r1, PT_R17#endif andi r5, r4, 0x1F; /* Extract ESR[EXC] */ #ifdef CONFIG_MMU /* Calculate exception vector offset = r5 << 2 */ addk r6, r5, r5; /* << 1 */ addk r6, r6, r6; /* << 2 */ #ifdef DEBUG/* counting which exception happen */ lwi r5, r0, TOPHYS(exception_debug_table) addi r5, r5, 1 swi r5, r0, TOPHYS(exception_debug_table) lwi r5, r6, TOPHYS(exception_debug_table) addi r5, r5, 1 swi r5, r6, TOPHYS(exception_debug_table)#endif/* end */ /* Load the HW Exception vector */ lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable) bra r6 full_exception_trapw: RESTORE_STATE bri full_exception_trap#else /* Exceptions enabled here. This will allow nested exceptions */ mfs r6, rmsr; nop swi r6, r1, 0; /* RMSR_OFFSET */ ori r6, r6, 0x100; /* Turn ON the EE bit */ andi r6, r6, ~2; /* Disable interrupts */ mts rmsr, r6; nop xori r6, r5, 1; /* 00001 = Unaligned Exception */ /* Jump to unalignment exception handler */ beqi r6, handle_unaligned_ex; handle_other_ex: /* Handle Other exceptions here */ /* Save other volatiles before we make procedure calls below */ swi r7, r1, PT_R7 swi r8, r1, PT_R8 swi r9, r1, PT_R9 swi r10, r1, PT_R10 swi r11, r1, PT_R11 swi r12, r1, PT_R12 swi r14, r1, PT_R14 swi r15, r1, PT_R15 swi r18, r1, PT_R18 or r5, r1, r0 andi r6, r4, 0x1F; /* Load ESR[EC] */ lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */ swi r7, r1, PT_MODE mfs r7, rfsr nop addk r8, r17, r0; /* Load exception address */ bralid r15, full_exception; /* Branch to the handler */ nop; mts rfsr, r0; /* Clear sticky fsr */ nop /* * Trigger execution of the signal handler by enabling * interrupts and calling an invalid syscall. */ mfs r5, rmsr; nop ori r5, r5, 2; mts rmsr, r5; /* enable interrupt */ nop addi r12, r0, __NR_syscalls; brki r14, 0x08; mfs r5, rmsr; /* disable interrupt */ nop andi r5, r5, ~2; mts rmsr, r5; nop lwi r7, r1, PT_R7 lwi r8, r1, PT_R8 lwi r9, r1, PT_R9 lwi r10, r1, PT_R10 lwi r11, r1, PT_R11 lwi r12, r1, PT_R12 lwi r14, r1, PT_R14 lwi r15, r1, PT_R15 lwi r18, r1, PT_R18 bri ex_handler_done; /* Complete exception handling */#endif /* 0x01 - Unaligned data access exception * This occurs when a word access is not aligned on a word boundary, * or when a 16-bit access is not aligned on a 16-bit boundary. * This handler perform the access, and returns, except for MMU when * the unaligned address is last on a 4k page or the physical address is * not found in the page table, in which case unaligned_data_trap is called. */handle_unaligned_ex: /* Working registers already saved: R3, R4, R5, R6 * R4 = ESR * R3 = EAR */#ifdef CONFIG_MMU andi r6, r4, 0x1000 /* Check ESR[DS] */ beqi r6, _no_delayslot /* Branch if ESR[DS] not set */ mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ nop_no_delayslot: /* jump to high level unaligned handler */ RESTORE_STATE; bri unaligned_data_trap#endif andi r6, r4, 0x3E0; /* Mask and extract the register operand */ srl r6, r6; /* r6 >> 5 */ srl r6, r6; srl r6, r6; srl r6, r6; srl r6, r6; /* Store the register operand in a temporary location */ sbi r6, r0, TOPHYS(ex_reg_op); andi r6, r4, 0x400; /* Extract ESR[S] */ bnei r6, ex_sw;ex_lw: andi r6, r4, 0x800; /* Extract ESR[W] */ beqi r6, ex_lhw; lbui r5, r3, 0; /* Exception address in r3 */ /* Load a word, byte-by-byte from destination address and save it in tmp space */ sbi r5, r0, TOPHYS(ex_tmp_data_loc_0); lbui r5, r3, 1; sbi r5, r0, TOPHYS(ex_tmp_data_loc_1); lbui r5, r3, 2; sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);Lines 1–500 of 1225. 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/* * Exception handling for Microblaze * * Rewriten interrupt handling * * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> * Copyright (C) 2008-2009 PetaLogix * * uClinux customisation (C) 2005 John Williams * * MMU code derived from arch/ppc/kernel/head_4xx.S: * Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org> * Initial PowerPC version. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> * Rewritten for PReP * Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au> * Low-level exception handers, MMU support, and rewrite. * Copyright (C) 1997 Dan Malek <dmalek@jlc.net> * PowerPC 8xx modifications. * Copyright (C) 1998-1999 TiVo, Inc. * PowerPC 403GCX modifications. * Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu> * PowerPC 403GCX/405GP modifications. * Copyright 2000 MontaVista Software Inc. * PPC405 modifications * PowerPC 403GCX/405GP modifications. * Author: MontaVista Software, Inc. * frank_rowand@mvista.com or source@mvista.com * debbie_chu@mvista.com * * Original code * Copyright (C) 2004 Xilinx, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published * by the Free Software Foundation. */ /* * Here are the handlers which don't require enabling translation * and calling other kernel code thus we can keep their design very simple * and do all processing in real mode. All what they need is a valid current * (that is an issue for the CONFIG_REGISTER_TASK_PTR case) * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore * these registers are saved/restored * The handlers which require translation are in entry.S --KAA * * Microblaze HW Exception Handler * - Non self-modifying exception handler for the following exception conditions * - Unalignment * - Instruction bus error * - Data bus error * - Illegal instruction opcode * - Divide-by-zero * * - Privileged instruction exception (MMU) * - Data storage exception (MMU) * - Instruction storage exception (MMU) * - Data TLB miss exception (MMU) * - Instruction TLB miss exception (MMU) * * Note we disable interrupts during exception handling, otherwise we will * possibly get multiple re-entrancy if interrupt handles themselves cause * exceptions. JW */ #include <asm/exceptions.h> #include <asm/unistd.h> #include <asm/page.h> #include <asm/entry.h> #include <asm/current.h> #include <linux/linkage.h> #include <asm/mmu.h> #include <asm/pgtable.h> #include <asm/signal.h> #include <asm/registers.h> #include <asm/asm-offsets.h> #undef DEBUG /* Helpful Macros */ #define NUM_TO_REG(num) r ## num #ifdef CONFIG_MMU #define RESTORE_STATE \ lwi r5, r1, 0; \ mts rmsr, r5; \ nop; \ lwi r3, r1, PT_R3; \ lwi r4, r1, PT_R4; \ lwi r5, r1, PT_R5; \ lwi r6, r1, PT_R6; \ lwi r11, r1, PT_R11; \ lwi r31, r1, PT_R31; \ lwi r1, r1, PT_R1; #endif /* CONFIG_MMU */ #define LWREG_NOP \ bri ex_handler_unhandled; \ nop; #define SWREG_NOP \ bri ex_handler_unhandled; \ nop; /* FIXME this is weird - for noMMU kernel is not possible to use brid * instruction which can shorten executed time */ /* r3 is the source */ #define R3_TO_LWREG_V(regnum) \ swi r3, r1, 4 * regnum; \ bri ex_handler_done; /* r3 is the source */ #define R3_TO_LWREG(regnum) \ or NUM_TO_REG (regnum), r0, r3; \ bri ex_handler_done; /* r3 is the target */ #define SWREG_TO_R3_V(regnum) \ lwi r3, r1, 4 * regnum; \ bri ex_sw_tail; /* r3 is the target */ #define SWREG_TO_R3(regnum) \ or r3, r0, NUM_TO_REG (regnum); \ bri ex_sw_tail; #ifdef CONFIG_MMU #define R3_TO_LWREG_VM_V(regnum) \ brid ex_lw_end_vm; \ swi r3, r7, 4 * regnum; #define R3_TO_LWREG_VM(regnum) \ brid ex_lw_end_vm; \ or NUM_TO_REG (regnum), r0, r3; #define SWREG_TO_R3_VM_V(regnum) \ brid ex_sw_tail_vm; \ lwi r3, r7, 4 * regnum; #define SWREG_TO_R3_VM(regnum) \ brid ex_sw_tail_vm; \ or r3, r0, NUM_TO_REG (regnum); /* Shift right instruction depending on available configuration */ #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0 /* Only the used shift constants defined here - add more if needed */ #define BSRLI2(rD, rA) \ srl rD, rA; /* << 1 */ \ srl rD, rD; /* << 2 */ #define BSRLI4(rD, rA) \ BSRLI2(rD, rA); \ BSRLI2(rD, rD) #define BSRLI10(rD, rA) \ srl rD, rA; /* << 1 */ \ srl rD, rD; /* << 2 */ \ srl rD, rD; /* << 3 */ \ srl rD, rD; /* << 4 */ \ srl rD, rD; /* << 5 */ \ srl rD, rD; /* << 6 */ \ srl rD, rD; /* << 7 */ \ srl rD, rD; /* << 8 */ \ srl rD, rD; /* << 9 */ \ srl rD, rD /* << 10 */ #define BSRLI20(rD, rA) \ BSRLI10(rD, rA); \ BSRLI10(rD, rD) .macro bsrli, rD, rA, IMM .if (\IMM) == 2 BSRLI2(\rD, \rA) .elseif (\IMM) == 10 BSRLI10(\rD, \rA) .elseif (\IMM) == 12 BSRLI2(\rD, \rA) BSRLI10(\rD, \rD) .elseif (\IMM) == 14 BSRLI4(\rD, \rA) BSRLI10(\rD, \rD) .elseif (\IMM) == 20 BSRLI20(\rD, \rA) .elseif (\IMM) == 24 BSRLI4(\rD, \rA) BSRLI20(\rD, \rD) .elseif (\IMM) == 28 BSRLI4(\rD, \rA) BSRLI4(\rD, \rD) BSRLI20(\rD, \rD) .else .error "BSRLI shift macros \IMM" .endif .endm #endif #endif /* CONFIG_MMU */ .extern other_exception_handler /* Defined in exception.c */ /* * hw_exception_handler - Handler for exceptions * * Exception handler notes: * - Handles all exceptions * - Does not handle unaligned exceptions during load into r17, r1, r0. * - Does not handle unaligned exceptions during store from r17 (cannot be * done) and r1 (slows down common case) * * Relevant register structures * * EAR - |----|----|----|----|----|----|----|----| * - < ## 32 bit faulting address ## > * * ESR - |----|----|----|----|----| - | - |-----|-----| * - W S REG EXC * * * STACK FRAME STRUCTURE (for CONFIG_MMU=n) * ---------------------------------------- * * +-------------+ + 0 * | MSR | * +-------------+ + 4 * | r1 | * | . | * | . | * | . | * | . | * | r18 | * +-------------+ + 76 * | . | * | . | * * MMU kernel uses the same 'pt_pool_space' pointed space * which is used for storing register values - noMMu style was, that values were * stored in stack but in case of failure you lost information about register. * Currently you can see register value in memory in specific place. * In compare to with previous solution the speed should be the same. * * MMU exception handler has different handling compare to no MMU kernel. * Exception handler use jump table for directing of what happen. For MMU kernel * is this approach better because MMU relate exception are handled by asm code * in this file. In compare to with MMU expect of unaligned exception * is everything handled by C code. */ /* * every of these handlers is entered having R3/4/5/6/11/current saved on stack * and clobbered so care should be taken to restore them if someone is going to * return from exception */ /* wrappers to restore state before coming to entry.S */ #ifdef CONFIG_MMU .section .data .align 4 pt_pool_space: .space PT_SIZE #ifdef DEBUG /* Create space for exception counting. */ .section .data .global exception_debug_table .align 4 exception_debug_table: /* Look at exception vector table. There is 32 exceptions * word size */ .space (32 * 4) #endif /* DEBUG */ .section .rodata .align 4 _MB_HW_ExceptionVectorTable: /* 0 - Undefined */ .long TOPHYS(ex_handler_unhandled) /* 1 - Unaligned data access exception */ .long TOPHYS(handle_unaligned_ex) /* 2 - Illegal op-code exception */ .long TOPHYS(full_exception_trapw) /* 3 - Instruction bus error exception */ .long TOPHYS(full_exception_trapw) /* 4 - Data bus error exception */ .long TOPHYS(full_exception_trapw) /* 5 - Divide by zero exception */ .long TOPHYS(full_exception_trapw) /* 6 - Floating point unit exception */ .long TOPHYS(full_exception_trapw) /* 7 - Privileged instruction exception */ .long TOPHYS(full_exception_trapw) /* 8 - 15 - Undefined */ .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) /* 16 - Data storage exception */ .long TOPHYS(handle_data_storage_exception) /* 17 - Instruction storage exception */ .long TOPHYS(handle_instruction_storage_exception) /* 18 - Data TLB miss exception */ .long TOPHYS(handle_data_tlb_miss_exception) /* 19 - Instruction TLB miss exception */ .long TOPHYS(handle_instruction_tlb_miss_exception) /* 20 - 31 - Undefined */ .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) .long TOPHYS(ex_handler_unhandled) #endif .global _hw_exception_handler .section .text .align 4 .ent _hw_exception_handler _hw_exception_handler: #ifndef CONFIG_MMU addik r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */ #else swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */ /* Save date to kernel memory. Here is the problem * when you came from user space */ ori r1, r0, TOPHYS(pt_pool_space); #endif swi r3, r1, PT_R3 swi r4, r1, PT_R4 swi r5, r1, PT_R5 swi r6, r1, PT_R6 #ifdef CONFIG_MMU swi r11, r1, PT_R11 swi r31, r1, PT_R31 lwi r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */ #endif mfs r5, rmsr; nop swi r5, r1, 0; mfs r4, resr nop mfs r3, rear; nop #ifndef CONFIG_MMU andi r5, r4, 0x1000; /* Check ESR[DS] */ beqi r5, not_in_delay_slot; /* Branch if ESR[DS] not set */ mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ nop not_in_delay_slot: swi r17, r1, PT_R17 #endif andi r5, r4, 0x1F; /* Extract ESR[EXC] */ #ifdef CONFIG_MMU /* Calculate exception vector offset = r5 << 2 */ addk r6, r5, r5; /* << 1 */ addk r6, r6, r6; /* << 2 */ #ifdef DEBUG /* counting which exception happen */ lwi r5, r0, TOPHYS(exception_debug_table) addi r5, r5, 1 swi r5, r0, TOPHYS(exception_debug_table) lwi r5, r6, TOPHYS(exception_debug_table) addi r5, r5, 1 swi r5, r6, TOPHYS(exception_debug_table) #endif /* end */ /* Load the HW Exception vector */ lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable) bra r6 full_exception_trapw: RESTORE_STATE bri full_exception_trap #else /* Exceptions enabled here. This will allow nested exceptions */ mfs r6, rmsr; nop swi r6, r1, 0; /* RMSR_OFFSET */ ori r6, r6, 0x100; /* Turn ON the EE bit */ andi r6, r6, ~2; /* Disable interrupts */ mts rmsr, r6; nop xori r6, r5, 1; /* 00001 = Unaligned Exception */ /* Jump to unalignment exception handler */ beqi r6, handle_unaligned_ex; handle_other_ex: /* Handle Other exceptions here */ /* Save other volatiles before we make procedure calls below */ swi r7, r1, PT_R7 swi r8, r1, PT_R8 swi r9, r1, PT_R9 swi r10, r1, PT_R10 swi r11, r1, PT_R11 swi r12, r1, PT_R12 swi r14, r1, PT_R14 swi r15, r1, PT_R15 swi r18, r1, PT_R18 or r5, r1, r0 andi r6, r4, 0x1F; /* Load ESR[EC] */ lwi r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */ swi r7, r1, PT_MODE mfs r7, rfsr nop addk r8, r17, r0; /* Load exception address */ bralid r15, full_exception; /* Branch to the handler */ nop; mts rfsr, r0; /* Clear sticky fsr */ nop /* * Trigger execution of the signal handler by enabling * interrupts and calling an invalid syscall. */ mfs r5, rmsr; nop ori r5, r5, 2; mts rmsr, r5; /* enable interrupt */ nop addi r12, r0, __NR_syscalls; brki r14, 0x08; mfs r5, rmsr; /* disable interrupt */ nop andi r5, r5, ~2; mts rmsr, r5; nop lwi r7, r1, PT_R7 lwi r8, r1, PT_R8 lwi r9, r1, PT_R9 lwi r10, r1, PT_R10 lwi r11, r1, PT_R11 lwi r12, r1, PT_R12 lwi r14, r1, PT_R14 lwi r15, r1, PT_R15 lwi r18, r1, PT_R18 bri ex_handler_done; /* Complete exception handling */ #endif /* 0x01 - Unaligned data access exception * This occurs when a word access is not aligned on a word boundary, * or when a 16-bit access is not aligned on a 16-bit boundary. * This handler perform the access, and returns, except for MMU when * the unaligned address is last on a 4k page or the physical address is * not found in the page table, in which case unaligned_data_trap is called. */ handle_unaligned_ex: /* Working registers already saved: R3, R4, R5, R6 * R4 = ESR * R3 = EAR */ #ifdef CONFIG_MMU andi r6, r4, 0x1000 /* Check ESR[DS] */ beqi r6, _no_delayslot /* Branch if ESR[DS] not set */ mfs r17, rbtr; /* ESR[DS] set - return address in BTR */ nop _no_delayslot: /* jump to high level unaligned handler */ RESTORE_STATE; bri unaligned_data_trap #endif andi r6, r4, 0x3E0; /* Mask and extract the register operand */ srl r6, r6; /* r6 >> 5 */ srl r6, r6; srl r6, r6; srl r6, r6; srl r6, r6; /* Store the register operand in a temporary location */ sbi r6, r0, TOPHYS(ex_reg_op); andi r6, r4, 0x400; /* Extract ESR[S] */ bnei r6, ex_sw; ex_lw: andi r6, r4, 0x800; /* Extract ESR[W] */ beqi r6, ex_lhw; lbui r5, r3, 0; /* Exception address in r3 */ /* Load a word, byte-by-byte from destination address and save it in tmp space */ sbi r5, r0, TOPHYS(ex_tmp_data_loc_0); lbui r5, r3, 1; sbi r5, r0, TOPHYS(ex_tmp_data_loc_1); lbui r5, r3, 2; sbi r5, r0, TOPHYS(ex_tmp_data_loc_2);