#include <linux/device.h>#include <linux/cpu.h>#include <linux/smp.h>#include <linux/percpu.h>#include <linux/init.h>#include <linux/sched.h>#include <linux/export.h>#include <linux/nodemask.h>#include <linux/cpumask.h>#include <linux/notifier.h> #include <asm/current.h>#include <asm/processor.h>#include <asm/cputable.h>#include <asm/hvcall.h>#include <asm/prom.h>#include <asm/machdep.h>#include <asm/smp.h>#include <asm/pmc.h>#include <asm/firmware.h> #include "cacheinfo.h" #ifdef CONFIG_PPC64#include <asm/paca.h>#include <asm/lppaca.h>#endif static DEFINE_PER_CPU(struct cpu, cpu_devices); /* * SMT snooze delay stuff, 64-bit only for now */ #ifdef CONFIG_PPC64 /* Time in microseconds we delay before sleeping in the idle loop */static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 }; static ssize_t store_smt_snooze_delay(struct device *dev,				      struct device_attribute *attr,				      const char *buf,				      size_t count){	struct cpu *cpu = container_of(dev, struct cpu, dev);	ssize_t ret;	long snooze; 	ret = sscanf(buf, "%ld", &snooze);	if (ret != 1)		return -EINVAL; 	per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;	return count;} static ssize_t show_smt_snooze_delay(struct device *dev,				     struct device_attribute *attr,				     char *buf){	struct cpu *cpu = container_of(dev, struct cpu, dev); 	return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));} static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,		   store_smt_snooze_delay); static int __init setup_smt_snooze_delay(char *str){	unsigned int cpu;	long snooze; 	if (!cpu_has_feature(CPU_FTR_SMT))		return 1; 	snooze = simple_strtol(str, NULL, 10);	for_each_possible_cpu(cpu)		per_cpu(smt_snooze_delay, cpu) = snooze; 	return 1;}__setup("smt-snooze-delay=", setup_smt_snooze_delay); #endif /* CONFIG_PPC64 */ #ifdef CONFIG_PPC_FSL_BOOK3E#define MAX_BIT				63 static u64 pw20_wt;static u64 altivec_idle_wt; static unsigned int get_idle_ticks_bit(u64 ns){	u64 cycle; 	if (ns >= 10000)		cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;	else		cycle = div_u64(ns * tb_ticks_per_usec, 1000); 	if (!cycle)		return 0; 	return ilog2(cycle);} static void do_show_pwrmgtcr0(void *val){	u32 *value = val; 	*value = mfspr(SPRN_PWRMGTCR0);} static ssize_t show_pw20_state(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	unsigned int cpu = dev->id; 	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 	value &= PWRMGTCR0_PW20_WAIT; 	return sprintf(buf, "%u\n", value ? 1 : 0);} static void do_store_pw20_state(void *val){	u32 *value = val;	u32 pw20_state; 	pw20_state = mfspr(SPRN_PWRMGTCR0); 	if (*value)		pw20_state |= PWRMGTCR0_PW20_WAIT;	else		pw20_state &= ~PWRMGTCR0_PW20_WAIT; 	mtspr(SPRN_PWRMGTCR0, pw20_state);} static ssize_t store_pw20_state(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 value;	unsigned int cpu = dev->id; 	if (kstrtou32(buf, 0, &value))		return -EINVAL; 	if (value > 1)		return -EINVAL; 	smp_call_function_single(cpu, do_store_pw20_state, &value, 1); 	return count;} static ssize_t show_pw20_wait_time(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	u64 tb_cycle = 1;	u64 time; 	unsigned int cpu = dev->id; 	if (!pw20_wt) {		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);		value = (value & PWRMGTCR0_PW20_ENT) >>					PWRMGTCR0_PW20_ENT_SHIFT; 		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));		/* convert ms to ns */		if (tb_ticks_per_usec > 1000) {			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);		} else {			u32 rem_us; 			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,						&rem_us);			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;		}	} else {		time = pw20_wt;	} 	return sprintf(buf, "%llu\n", time > 0 ? time : 0);} static void set_pw20_wait_entry_bit(void *val){	u32 *value = val;	u32 pw20_idle; 	pw20_idle = mfspr(SPRN_PWRMGTCR0); 	/* Set Automatic PW20 Core Idle Count */	/* clear count */	pw20_idle &= ~PWRMGTCR0_PW20_ENT; 	/* set count */	pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT); 	mtspr(SPRN_PWRMGTCR0, pw20_idle);} static ssize_t store_pw20_wait_time(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 entry_bit;	u64 value; 	unsigned int cpu = dev->id; 	if (kstrtou64(buf, 0, &value))		return -EINVAL; 	if (!value)		return -EINVAL; 	entry_bit = get_idle_ticks_bit(value);	if (entry_bit > MAX_BIT)		return -EINVAL; 	pw20_wt = value; 	smp_call_function_single(cpu, set_pw20_wait_entry_bit,				&entry_bit, 1); 	return count;} static ssize_t show_altivec_idle(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	unsigned int cpu = dev->id; 	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1); 	value &= PWRMGTCR0_AV_IDLE_PD_EN; 	return sprintf(buf, "%u\n", value ? 1 : 0);} static void do_store_altivec_idle(void *val){	u32 *value = val;	u32 altivec_idle; 	altivec_idle = mfspr(SPRN_PWRMGTCR0); 	if (*value)		altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;	else		altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN; 	mtspr(SPRN_PWRMGTCR0, altivec_idle);} static ssize_t store_altivec_idle(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 value;	unsigned int cpu = dev->id; 	if (kstrtou32(buf, 0, &value))		return -EINVAL; 	if (value > 1)		return -EINVAL; 	smp_call_function_single(cpu, do_store_altivec_idle, &value, 1); 	return count;} static ssize_t show_altivec_idle_wait_time(struct device *dev,				struct device_attribute *attr, char *buf){	u32 value;	u64 tb_cycle = 1;	u64 time; 	unsigned int cpu = dev->id; 	if (!altivec_idle_wt) {		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);		value = (value & PWRMGTCR0_AV_IDLE_CNT) >>					PWRMGTCR0_AV_IDLE_CNT_SHIFT; 		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));		/* convert ms to ns */		if (tb_ticks_per_usec > 1000) {			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);		} else {			u32 rem_us; 			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,						&rem_us);			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;		}	} else {		time = altivec_idle_wt;	} 	return sprintf(buf, "%llu\n", time > 0 ? time : 0);} static void set_altivec_idle_wait_entry_bit(void *val){	u32 *value = val;	u32 altivec_idle; 	altivec_idle = mfspr(SPRN_PWRMGTCR0); 	/* Set Automatic AltiVec Idle Count */	/* clear count */	altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT; 	/* set count */	altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT); 	mtspr(SPRN_PWRMGTCR0, altivec_idle);} static ssize_t store_altivec_idle_wait_time(struct device *dev,				struct device_attribute *attr,				const char *buf, size_t count){	u32 entry_bit;	u64 value; 	unsigned int cpu = dev->id; 	if (kstrtou64(buf, 0, &value))		return -EINVAL; 	if (!value)		return -EINVAL; 	entry_bit = get_idle_ticks_bit(value);	if (entry_bit > MAX_BIT)		return -EINVAL; 	altivec_idle_wt = value; 	smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,				&entry_bit, 1); 	return count;} /* * Enable/Disable interface: * 0, disable. 1, enable. */static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle); /* * Set wait time interface:(Nanosecond) * Example: Base on TBfreq is 41MHZ. * 1~48(ns): TB[63] * 49~97(ns): TB[62] * 98~195(ns): TB[61] * 196~390(ns): TB[60] * 391~780(ns): TB[59] * 781~1560(ns): TB[58] * ... */static DEVICE_ATTR(pw20_wait_time, 0600,			show_pw20_wait_time,			store_pw20_wait_time);static DEVICE_ATTR(altivec_idle_wait_time, 0600,			show_altivec_idle_wait_time,			store_altivec_idle_wait_time);#endif /* * Enabling PMCs will slow partition context switch times so we only do * it the first time we write to the PMCs. */ static DEFINE_PER_CPU(char, pmcs_enabled); void ppc_enable_pmcs(void){	ppc_set_pmu_inuse(1); 	/* Only need to enable them once */	if (__this_cpu_read(pmcs_enabled))		return; 	__this_cpu_write(pmcs_enabled, 1); 	if (ppc_md.enable_pmcs)		ppc_md.enable_pmcs();}EXPORT_SYMBOL(ppc_enable_pmcs); #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \static void read_##NAME(void *val) \{ \	*(unsigned long *)val = mfspr(ADDRESS);	\} \static void write_##NAME(void *val) \{ \	EXTRA; \	mtspr(ADDRESS, *(unsigned long *)val);	\} #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \static ssize_t show_##NAME(struct device *dev, \			struct device_attribute *attr, \			char *buf) \{ \	struct cpu *cpu = container_of(dev, struct cpu, dev); \	unsigned long val; \	smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);	\	return sprintf(buf, "%lx\n", val); \} \static ssize_t __used \	store_##NAME(struct device *dev, struct device_attribute *attr, \			const char *buf, size_t count) \{ \	struct cpu *cpu = container_of(dev, struct cpu, dev); \	unsigned long val; \	int ret = sscanf(buf, "%lx", &val); \	if (ret != 1) \		return -EINVAL; \	smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \	return count; \} #define SYSFS_PMCSETUP(NAME, ADDRESS) \	__SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \	__SYSFS_SPRSETUP_SHOW_STORE(NAME)#define SYSFS_SPRSETUP(NAME, ADDRESS) \	__SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \	__SYSFS_SPRSETUP_SHOW_STORE(NAME) #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \	__SYSFS_SPRSETUP_SHOW_STORE(NAME) /* Let's define all possible registers, we'll only hook up the ones * that are implemented on the current processor */ #if defined(CONFIG_PPC64)#define HAS_PPC_PMC_CLASSIC	1#define HAS_PPC_PMC_IBM		1#define HAS_PPC_PMC_PA6T	1#elif defined(CONFIG_6xx)#define HAS_PPC_PMC_CLASSIC	1#define HAS_PPC_PMC_IBM		1#define HAS_PPC_PMC_G4		1#endif  #ifdef HAS_PPC_PMC_CLASSICSYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);SYSFS_PMCSETUP(pmc1, SPRN_PMC1);SYSFS_PMCSETUP(pmc2, SPRN_PMC2);SYSFS_PMCSETUP(pmc3, SPRN_PMC3);SYSFS_PMCSETUP(pmc4, SPRN_PMC4);SYSFS_PMCSETUP(pmc5, SPRN_PMC5);SYSFS_PMCSETUP(pmc6, SPRN_PMC6); #ifdef HAS_PPC_PMC_G4SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);#endif #ifdef CONFIG_PPC64SYSFS_PMCSETUP(pmc7, SPRN_PMC7);SYSFS_PMCSETUP(pmc8, SPRN_PMC8); SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);SYSFS_SPRSETUP(purr, SPRN_PURR);SYSFS_SPRSETUP(spurr, SPRN_SPURR);SYSFS_SPRSETUP(pir, SPRN_PIR); /*  Lets only enable read for phyp resources and  enable write when needed with a separate function.  Lets be conservative and default to pseries.*/static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);static DEVICE_ATTR(purr, 0400, show_purr, store_purr);static DEVICE_ATTR(pir, 0400, show_pir, NULL); /* * This is the system wide DSCR register default value. Any

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