/* * CAAM control-plane driver backend * Controller-level driver, kernel property detection, initialization * * Copyright 2008-2012 Freescale Semiconductor, Inc. */ #include <linux/device.h>#include <linux/of_address.h>#include <linux/of_irq.h> #include "compat.h"#include "regs.h"#include "intern.h"#include "jr.h"#include "desc_constr.h"#include "ctrl.h" bool caam_little_end;EXPORT_SYMBOL(caam_little_end); #ifdef CONFIG_CAAM_QI#include "qi.h"#endif /* * i.MX targets tend to have clock control subsystems that can * enable/disable clocking to our device. */#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMXstatic inline struct clk *caam_drv_identify_clk(struct device *dev,						char *clk_name){	return devm_clk_get(dev, clk_name);}#elsestatic inline struct clk *caam_drv_identify_clk(struct device *dev,						char *clk_name){	return NULL;}#endif /* * Descriptor to instantiate RNG State Handle 0 in normal mode and * load the JDKEK, TDKEK and TDSK registers */static void build_instantiation_desc(u32 *desc, int handle, int do_sk){	u32 *jump_cmd, op_flags; 	init_job_desc(desc, 0); 	op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |			(handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; 	/* INIT RNG in non-test mode */	append_operation(desc, op_flags); 	if (!handle && do_sk) {		/*		 * For SH0, Secure Keys must be generated as well		 */ 		/* wait for done */		jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);		set_jump_tgt_here(desc, jump_cmd); 		/*		 * load 1 to clear written reg:		 * resets the done interrrupt and returns the RNG to idle.		 */		append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); 		/* Initialize State Handle  */		append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |				 OP_ALG_AAI_RNG4_SK);	} 	append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);} /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */static void build_deinstantiation_desc(u32 *desc, int handle){	init_job_desc(desc, 0); 	/* Uninstantiate State Handle 0 */	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |			 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); 	append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);} /* * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of *			  the software (no JR/QI used). * @ctrldev - pointer to device * @status - descriptor status, after being run * * Return: - 0 if no error occurred *	   - -ENODEV if the DECO couldn't be acquired *	   - -EAGAIN if an error occurred while executing the descriptor */static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,					u32 *status){	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);	struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;	struct caam_deco __iomem *deco = ctrlpriv->deco;	unsigned int timeout = 100000;	u32 deco_dbg_reg, flags;	int i;  	if (ctrlpriv->virt_en == 1) {		clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0); 		while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&		       --timeout)			cpu_relax(); 		timeout = 100000;	} 	clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE); 	while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&								 --timeout)		cpu_relax(); 	if (!timeout) {		dev_err(ctrldev, "failed to acquire DECO 0\n");		clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);		return -ENODEV;	} 	for (i = 0; i < desc_len(desc); i++)		wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i))); 	flags = DECO_JQCR_WHL;	/*	 * If the descriptor length is longer than 4 words, then the	 * FOUR bit in JRCTRL register must be set.	 */	if (desc_len(desc) >= 4)		flags |= DECO_JQCR_FOUR; 	/* Instruct the DECO to execute it */	clrsetbits_32(&deco->jr_ctl_hi, 0, flags); 	timeout = 10000000;	do {		deco_dbg_reg = rd_reg32(&deco->desc_dbg);		/*		 * If an error occured in the descriptor, then		 * the DECO status field will be set to 0x0D		 */		if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==		    DESC_DBG_DECO_STAT_HOST_ERR)			break;		cpu_relax();	} while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); 	*status = rd_reg32(&deco->op_status_hi) &		  DECO_OP_STATUS_HI_ERR_MASK; 	if (ctrlpriv->virt_en == 1)		clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0); 	/* Mark the DECO as free */	clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0); 	if (!timeout)		return -EAGAIN; 	return 0;} /* * instantiate_rng - builds and executes a descriptor on DECO0, *		     which initializes the RNG block. * @ctrldev - pointer to device * @state_handle_mask - bitmask containing the instantiation status *			for the RNG4 state handles which exist in *			the RNG4 block: 1 if it's been instantiated *			by an external entry, 0 otherwise. * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK; *	      Caution: this can be done only once; if the keys need to be *	      regenerated, a POR is required * * Return: - 0 if no error occurred *	   - -ENOMEM if there isn't enough memory to allocate the descriptor *	   - -ENODEV if DECO0 couldn't be acquired *	   - -EAGAIN if an error occurred when executing the descriptor *	      f.i. there was a RNG hardware error due to not "good enough" *	      entropy being aquired. */static int instantiate_rng(struct device *ctrldev, int state_handle_mask,			   int gen_sk){	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);	struct caam_ctrl __iomem *ctrl;	u32 *desc, status = 0, rdsta_val;	int ret = 0, sh_idx; 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;	desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);	if (!desc)		return -ENOMEM; 	for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {		/*		 * If the corresponding bit is set, this state handle		 * was initialized by somebody else, so it's left alone.		 */		if ((1 << sh_idx) & state_handle_mask)			continue; 		/* Create the descriptor for instantiating RNG State Handle */		build_instantiation_desc(desc, sh_idx, gen_sk); 		/* Try to run it through DECO0 */		ret = run_descriptor_deco0(ctrldev, desc, &status); 		/*		 * If ret is not 0, or descriptor status is not 0, then		 * something went wrong. No need to try the next state		 * handle (if available), bail out here.		 * Also, if for some reason, the State Handle didn't get		 * instantiated although the descriptor has finished		 * without any error (HW optimizations for later		 * CAAM eras), then try again.		 */		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||		    !(rdsta_val & (1 << sh_idx)))			ret = -EAGAIN;		if (ret)			break;		dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);		/* Clear the contents before recreating the descriptor */		memset(desc, 0x00, CAAM_CMD_SZ * 7);	} 	kfree(desc); 	return ret;} /* * deinstantiate_rng - builds and executes a descriptor on DECO0, *		       which deinitializes the RNG block. * @ctrldev - pointer to device * @state_handle_mask - bitmask containing the instantiation status *			for the RNG4 state handles which exist in *			the RNG4 block: 1 if it's been instantiated * * Return: - 0 if no error occurred *	   - -ENOMEM if there isn't enough memory to allocate the descriptor *	   - -ENODEV if DECO0 couldn't be acquired *	   - -EAGAIN if an error occurred when executing the descriptor */static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask){	u32 *desc, status;	int sh_idx, ret = 0; 	desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);	if (!desc)		return -ENOMEM; 	for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {		/*		 * If the corresponding bit is set, then it means the state		 * handle was initialized by us, and thus it needs to be		 * deinitialized as well		 */		if ((1 << sh_idx) & state_handle_mask) {			/*			 * Create the descriptor for deinstantating this state			 * handle			 */			build_deinstantiation_desc(desc, sh_idx); 			/* Try to run it through DECO0 */			ret = run_descriptor_deco0(ctrldev, desc, &status); 			if (ret ||			    (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {				dev_err(ctrldev,					"Failed to deinstantiate RNG4 SH%d\n",					sh_idx);				break;			}			dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);		}	} 	kfree(desc); 	return ret;} static int caam_remove(struct platform_device *pdev){	struct device *ctrldev;	struct caam_drv_private *ctrlpriv;	struct caam_ctrl __iomem *ctrl; 	ctrldev = &pdev->dev;	ctrlpriv = dev_get_drvdata(ctrldev);	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; 	/* Remove platform devices under the crypto node */	of_platform_depopulate(ctrldev); #ifdef CONFIG_CAAM_QI	if (ctrlpriv->qidev)		caam_qi_shutdown(ctrlpriv->qidev);#endif 	/* De-initialize RNG state handles initialized by this driver. */	if (ctrlpriv->rng4_sh_init)		deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); 	/* Shut down debug views */#ifdef CONFIG_DEBUG_FS	debugfs_remove_recursive(ctrlpriv->dfs_root);#endif 	/* Unmap controller region */	iounmap(ctrl); 	/* shut clocks off before finalizing shutdown */	clk_disable_unprepare(ctrlpriv->caam_ipg);	clk_disable_unprepare(ctrlpriv->caam_mem);	clk_disable_unprepare(ctrlpriv->caam_aclk);	if (ctrlpriv->caam_emi_slow)		clk_disable_unprepare(ctrlpriv->caam_emi_slow);	return 0;} /* * kick_trng - sets the various parameters for enabling the initialization *	       of the RNG4 block in CAAM * @pdev - pointer to the platform device * @ent_delay - Defines the length (in system clocks) of each entropy sample. */static void kick_trng(struct platform_device *pdev, int ent_delay){	struct device *ctrldev = &pdev->dev;	struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);	struct caam_ctrl __iomem *ctrl;	struct rng4tst __iomem *r4tst;	u32 val; 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;	r4tst = &ctrl->r4tst[0]; 	/* put RNG4 into program mode */	clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); 	/*	 * Performance-wise, it does not make sense to	 * set the delay to a value that is lower	 * than the last one that worked (i.e. the state handles	 * were instantiated properly. Thus, instead of wasting	 * time trying to set the values controlling the sample	 * frequency, the function simply returns.	 */	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)	      >> RTSDCTL_ENT_DLY_SHIFT;	if (ent_delay <= val)		goto start_rng; 	val = rd_reg32(&r4tst->rtsdctl);	val = (val & ~RTSDCTL_ENT_DLY_MASK) |	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);	wr_reg32(&r4tst->rtsdctl, val);	/* min. freq. count, equal to 1/4 of the entropy sample length */	wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);	/* disable maximum frequency count */	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);	/* read the control register */	val = rd_reg32(&r4tst->rtmctl);start_rng:	/*	 * select raw sampling in both entropy shifter	 * and statistical checker; ; put RNG4 into run mode	 */	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);} /** * caam_get_era() - Return the ERA of the SEC on SoC, based * on "sec-era" propery in the DTS. This property is updated by u-boot. **/int caam_get_era(void){	struct device_node *caam_node;	int ret;	u32 prop; 	caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");	ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);	of_node_put(caam_node); 	return ret ? -ENOTSUPP : prop;}EXPORT_SYMBOL(caam_get_era); static const struct of_device_id caam_match[] = {	{		.compatible = "fsl,sec-v4.0",	},	{		.compatible = "fsl,sec4.0",	},	{},};MODULE_DEVICE_TABLE(of, caam_match); /* Probe routine for CAAM top (controller) level */static int caam_probe(struct platform_device *pdev){	int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;	u64 caam_id;	struct device *dev;	struct device_node *nprop, *np;	struct caam_ctrl __iomem *ctrl;	struct caam_drv_private *ctrlpriv;	struct clk *clk;#ifdef CONFIG_DEBUG_FS	struct caam_perfmon *perfmon;#endif	u32 scfgr, comp_params;	u32 cha_vid_ls;	int pg_size;	int BLOCK_OFFSET = 0; 	ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);	if (!ctrlpriv)		return -ENOMEM; 	dev = &pdev->dev;	dev_set_drvdata(dev, ctrlpriv);	ctrlpriv->pdev = pdev;	nprop = pdev->dev.of_node; 	/* Enable clocking */	clk = caam_drv_identify_clk(&pdev->dev, "ipg");	if (IS_ERR(clk)) {		ret = PTR_ERR(clk);		dev_err(&pdev->dev,			"can't identify CAAM ipg clk: %d\n", ret);		return ret;	}	ctrlpriv->caam_ipg = clk; 	clk = caam_drv_identify_clk(&pdev->dev, "mem");	if (IS_ERR(clk)) {		ret = PTR_ERR(clk);		dev_err(&pdev->dev,			"can't identify CAAM mem clk: %d\n", ret);		return ret;	}	ctrlpriv->caam_mem = clk; 	clk = caam_drv_identify_clk(&pdev->dev, "aclk");	if (IS_ERR(clk)) {		ret = PTR_ERR(clk);		dev_err(&pdev->dev,			"can't identify CAAM aclk clk: %d\n", ret);		return ret;	}	ctrlpriv->caam_aclk = clk; 	if (!of_machine_is_compatible("fsl,imx6ul")) {		clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");		if (IS_ERR(clk)) {			ret = PTR_ERR(clk);			dev_err(&pdev->dev,				"can't identify CAAM emi_slow clk: %d\n", ret);			return ret;		}		ctrlpriv->caam_emi_slow = clk;	} 	ret = clk_prepare_enable(ctrlpriv->caam_ipg);	if (ret < 0) {		dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);		return ret;	} 	ret = clk_prepare_enable(ctrlpriv->caam_mem);	if (ret < 0) {		dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",			ret);		goto disable_caam_ipg;	}

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