/* * Copyright 2011 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Alex Deucher */#ifndef SI_H#define SI_H #define TAHITI_RB_BITMAP_WIDTH_PER_SH  2 #define TAHITI_GB_ADDR_CONFIG_GOLDEN        0x12011003#define VERDE_GB_ADDR_CONFIG_GOLDEN         0x12010002#define HAINAN_GB_ADDR_CONFIG_GOLDEN        0x02010001 #define SI_MAX_SH_GPRS		 	256#define SI_MAX_TEMP_GPRS         	16#define SI_MAX_SH_THREADS        	256#define SI_MAX_SH_STACK_ENTRIES  	4096#define SI_MAX_FRC_EOV_CNT       	16384#define SI_MAX_BACKENDS          	8#define SI_MAX_BACKENDS_MASK     	0xFF#define SI_MAX_BACKENDS_PER_SE_MASK     0x0F#define SI_MAX_SIMDS             	12#define SI_MAX_SIMDS_MASK        	0x0FFF#define SI_MAX_SIMDS_PER_SE_MASK        0x00FF#define SI_MAX_PIPES            	8#define SI_MAX_PIPES_MASK        	0xFF#define SI_MAX_PIPES_PER_SIMD_MASK      0x3F#define SI_MAX_LDS_NUM           	0xFFFF#define SI_MAX_TCC               	16#define SI_MAX_TCC_MASK          	0xFFFF #define AMDGPU_NUM_OF_VMIDS 		8 /* SMC IND accessor regs */#define SMC_IND_INDEX_0                              0x80#define SMC_IND_DATA_0                               0x81 #define SMC_IND_ACCESS_CNTL                          0x8A#       define AUTO_INCREMENT_IND_0                  (1 << 0)#define SMC_MESSAGE_0                                0x8B#define SMC_RESP_0                                   0x8C /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */#define SMC_CG_IND_START                    0xc0030000#define SMC_CG_IND_END                      0xc0040000 #define	CG_CGTT_LOCAL_0				0x400#define	CG_CGTT_LOCAL_1				0x401 /* SMC IND registers */#define	SMC_SYSCON_RESET_CNTL				0x80000000#       define RST_REG                                  (1 << 0)#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004#       define CK_DISABLE                               (1 << 0)#       define CKEN                                     (1 << 24) #define VGA_HDP_CONTROL  				0xCA#define		VGA_MEMORY_DISABLE				(1 << 4) #define DCCG_DISP_SLOW_SELECT_REG                       0x13F#define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)#define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)#define		DCCG_DISP1_SLOW_SELECT_SHIFT		0#define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)#define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)#define		DCCG_DISP2_SLOW_SELECT_SHIFT		4 #define	CG_SPLL_FUNC_CNTL				0x180#define		SPLL_RESET				(1 << 0)#define		SPLL_SLEEP				(1 << 1)#define		SPLL_BYPASS_EN				(1 << 3)#define		SPLL_REF_DIV(x)				((x) << 4)#define		SPLL_REF_DIV_MASK			(0x3f << 4)#define		SPLL_PDIV_A(x)				((x) << 20)#define		SPLL_PDIV_A_MASK			(0x7f << 20)#define		SPLL_PDIV_A_SHIFT			20#define	CG_SPLL_FUNC_CNTL_2				0x181#define		SCLK_MUX_SEL(x)				((x) << 0)#define		SCLK_MUX_SEL_MASK			(0x1ff << 0)#define		SPLL_CTLREQ_CHG				(1 << 23)#define		SCLK_MUX_UPDATE				(1 << 26)#define	CG_SPLL_FUNC_CNTL_3				0x182#define		SPLL_FB_DIV(x)				((x) << 0)#define		SPLL_FB_DIV_MASK			(0x3ffffff << 0)#define		SPLL_FB_DIV_SHIFT			0#define		SPLL_DITHEN				(1 << 28)#define	CG_SPLL_FUNC_CNTL_4				0x183 #define	SPLL_STATUS					0x185#define		SPLL_CHG_STATUS				(1 << 1)#define	SPLL_CNTL_MODE					0x186#define		SPLL_SW_DIR_CONTROL			(1 << 0)#	define SPLL_REFCLK_SEL(x)			((x) << 26)#	define SPLL_REFCLK_SEL_MASK			(3 << 26) #define	CG_SPLL_SPREAD_SPECTRUM				0x188#define		SSEN					(1 << 0)#define		CLK_S(x)				((x) << 4)#define		CLK_S_MASK				(0xfff << 4)#define		CLK_S_SHIFT				4#define	CG_SPLL_SPREAD_SPECTRUM_2			0x189#define		CLK_V(x)				((x) << 0)#define		CLK_V_MASK				(0x3ffffff << 0)#define		CLK_V_SHIFT				0 #define	CG_SPLL_AUTOSCALE_CNTL				0x18b#       define AUTOSCALE_ON_SS_CLEAR                    (1 << 9) /* discrete uvd clocks */#define	CG_UPLL_FUNC_CNTL				0x18d#	define UPLL_RESET_MASK				0x00000001#	define UPLL_SLEEP_MASK				0x00000002#	define UPLL_BYPASS_EN_MASK			0x00000004#	define UPLL_CTLREQ_MASK				0x00000008#	define UPLL_VCO_MODE_MASK			0x00000600#	define UPLL_REF_DIV_MASK			0x003F0000#	define UPLL_CTLACK_MASK				0x40000000#	define UPLL_CTLACK2_MASK			0x80000000#define	CG_UPLL_FUNC_CNTL_2				0x18e#	define UPLL_PDIV_A(x)				((x) << 0)#	define UPLL_PDIV_A_MASK				0x0000007F#	define UPLL_PDIV_B(x)				((x) << 8)#	define UPLL_PDIV_B_MASK				0x00007F00#	define VCLK_SRC_SEL(x)				((x) << 20)#	define VCLK_SRC_SEL_MASK			0x01F00000#	define DCLK_SRC_SEL(x)				((x) << 25)#	define DCLK_SRC_SEL_MASK			0x3E000000#define	CG_UPLL_FUNC_CNTL_3				0x18f#	define UPLL_FB_DIV(x)				((x) << 0)#	define UPLL_FB_DIV_MASK				0x01FFFFFF#define	CG_UPLL_FUNC_CNTL_4                             0x191#	define UPLL_SPARE_ISPARE9			0x00020000#define	CG_UPLL_FUNC_CNTL_5				0x192#	define RESET_ANTI_MUX_MASK			0x00000200#define	CG_UPLL_SPREAD_SPECTRUM				0x194#	define SSEN_MASK				0x00000001 #define	MPLL_BYPASSCLK_SEL				0x197#	define MPLL_CLKOUT_SEL(x)			((x) << 8)#	define MPLL_CLKOUT_SEL_MASK			0xFF00 #define CG_CLKPIN_CNTL                                    0x198#       define XTALIN_DIVIDE                              (1 << 1)#       define BCLK_AS_XCLK                               (1 << 2)#define CG_CLKPIN_CNTL_2                                  0x199#       define FORCE_BIF_REFCLK_EN                        (1 << 3)#       define MUX_TCLK_TO_XCLK                           (1 << 8) #define	THM_CLK_CNTL					0x19b#	define CMON_CLK_SEL(x)				((x) << 0)#	define CMON_CLK_SEL_MASK			0xFF#	define TMON_CLK_SEL(x)				((x) << 8)#	define TMON_CLK_SEL_MASK			0xFF00#define	MISC_CLK_CNTL					0x19c#	define DEEP_SLEEP_CLK_SEL(x)			((x) << 0)#	define DEEP_SLEEP_CLK_SEL_MASK			0xFF#	define ZCLK_SEL(x)				((x) << 8)#	define ZCLK_SEL_MASK				0xFF00 #define	CG_THERMAL_CTRL					0x1c0#define 	DPM_EVENT_SRC(x)			((x) << 0)#define 	DPM_EVENT_SRC_MASK			(7 << 0)#define		DIG_THERM_DPM(x)			((x) << 14)#define		DIG_THERM_DPM_MASK			0x003FC000#define		DIG_THERM_DPM_SHIFT			14#define	CG_THERMAL_STATUS				0x1c1#define		FDO_PWM_DUTY(x)				((x) << 9)#define		FDO_PWM_DUTY_MASK			(0xff << 9)#define		FDO_PWM_DUTY_SHIFT			9#define	CG_THERMAL_INT					0x1c2#define		DIG_THERM_INTH(x)			((x) << 8)#define		DIG_THERM_INTH_MASK			0x0000FF00#define		DIG_THERM_INTH_SHIFT			8#define		DIG_THERM_INTL(x)			((x) << 16)#define		DIG_THERM_INTL_MASK			0x00FF0000#define		DIG_THERM_INTL_SHIFT			16#define 	THERM_INT_MASK_HIGH			(1 << 24)#define 	THERM_INT_MASK_LOW			(1 << 25) #define	CG_MULT_THERMAL_CTRL					0x1c4#define		TEMP_SEL(x)					((x) << 20)#define		TEMP_SEL_MASK					(0xff << 20)#define		TEMP_SEL_SHIFT					20#define	CG_MULT_THERMAL_STATUS					0x1c5#define		ASIC_MAX_TEMP(x)				((x) << 0)#define		ASIC_MAX_TEMP_MASK				0x000001ff#define		ASIC_MAX_TEMP_SHIFT				0#define		CTF_TEMP(x)					((x) << 9)#define		CTF_TEMP_MASK					0x0003fe00#define		CTF_TEMP_SHIFT					9 #define	CG_FDO_CTRL0					0x1d5#define		FDO_STATIC_DUTY(x)			((x) << 0)#define		FDO_STATIC_DUTY_MASK			0x000000FF#define		FDO_STATIC_DUTY_SHIFT			0#define	CG_FDO_CTRL1					0x1d6#define		FMAX_DUTY100(x)				((x) << 0)#define		FMAX_DUTY100_MASK			0x000000FF#define		FMAX_DUTY100_SHIFT			0#define	CG_FDO_CTRL2					0x1d7#define		TMIN(x)					((x) << 0)#define		TMIN_MASK				0x000000FF#define		TMIN_SHIFT				0#define		FDO_PWM_MODE(x)				((x) << 11)#define		FDO_PWM_MODE_MASK			(7 << 11)#define		FDO_PWM_MODE_SHIFT			11#define		TACH_PWM_RESP_RATE(x)			((x) << 25)#define		TACH_PWM_RESP_RATE_MASK			(0x7f << 25)#define		TACH_PWM_RESP_RATE_SHIFT		25 #define CG_TACH_CTRL                                    0x1dc#       define EDGE_PER_REV(x)                          ((x) << 0)#       define EDGE_PER_REV_MASK                        (0x7 << 0)#       define EDGE_PER_REV_SHIFT                       0#       define TARGET_PERIOD(x)                         ((x) << 3)#       define TARGET_PERIOD_MASK                       0xfffffff8#       define TARGET_PERIOD_SHIFT                      3#define CG_TACH_STATUS                                  0x1dd#       define TACH_PERIOD(x)                           ((x) << 0)#       define TACH_PERIOD_MASK                         0xffffffff#       define TACH_PERIOD_SHIFT                        0 #define GENERAL_PWRMGT                                  0x1e0#       define GLOBAL_PWRMGT_EN                         (1 << 0)#       define STATIC_PM_EN                             (1 << 1)#       define THERMAL_PROTECTION_DIS                   (1 << 2)#       define THERMAL_PROTECTION_TYPE                  (1 << 3)#       define SW_SMIO_INDEX(x)                         ((x) << 6)#       define SW_SMIO_INDEX_MASK                       (1 << 6)#       define SW_SMIO_INDEX_SHIFT                      6#       define VOLT_PWRMGT_EN                           (1 << 10)#       define DYN_SPREAD_SPECTRUM_EN                   (1 << 23)#define CG_TPC                                            0x1e1#define SCLK_PWRMGT_CNTL                                  0x1e2#       define SCLK_PWRMGT_OFF                            (1 << 0)#       define SCLK_LOW_D1                                (1 << 1)#       define FIR_RESET                                  (1 << 4)#       define FIR_FORCE_TREND_SEL                        (1 << 5)#       define FIR_TREND_MODE                             (1 << 6)#       define DYN_GFX_CLK_OFF_EN                         (1 << 7)#       define GFX_CLK_FORCE_ON                           (1 << 8)#       define GFX_CLK_REQUEST_OFF                        (1 << 9)#       define GFX_CLK_FORCE_OFF                          (1 << 10)#       define GFX_CLK_OFF_ACPI_D1                        (1 << 11)#       define GFX_CLK_OFF_ACPI_D2                        (1 << 12)#       define GFX_CLK_OFF_ACPI_D3                        (1 << 13)#       define DYN_LIGHT_SLEEP_EN                         (1 << 14) #define TARGET_AND_CURRENT_PROFILE_INDEX                  0x1e6#       define CURRENT_STATE_INDEX_MASK                   (0xf << 4)#       define CURRENT_STATE_INDEX_SHIFT                  4 #define CG_FTV                                            0x1ef #define CG_FFCT_0                                         0x1f0#       define UTC_0(x)                                   ((x) << 0)#       define UTC_0_MASK                                 (0x3ff << 0)#       define DTC_0(x)                                   ((x) << 10)#       define DTC_0_MASK                                 (0x3ff << 10) #define CG_BSP                                          0x1ff#       define BSP(x)					((x) << 0)#       define BSP_MASK					(0xffff << 0)#       define BSU(x)					((x) << 16)#       define BSU_MASK					(0xf << 16)#define CG_AT                                           0x200#       define CG_R(x)					((x) << 0)#       define CG_R_MASK				(0xffff << 0)#       define CG_L(x)					((x) << 16)#       define CG_L_MASK				(0xffff << 16) #define CG_GIT                                          0x201#       define CG_GICST(x)                              ((x) << 0)#       define CG_GICST_MASK                            (0xffff << 0)#       define CG_GIPOT(x)                              ((x) << 16)#       define CG_GIPOT_MASK                            (0xffff << 16) #define CG_SSP                                            0x203#       define SST(x)                                     ((x) << 0)#       define SST_MASK                                   (0xffff << 0)#       define SSTU(x)                                    ((x) << 16)#       define SSTU_MASK                                  (0xf << 16) #define CG_DISPLAY_GAP_CNTL                               0x20a#       define DISP1_GAP(x)                               ((x) << 0)#       define DISP1_GAP_MASK                             (3 << 0)#       define DISP2_GAP(x)                               ((x) << 2)#       define DISP2_GAP_MASK                             (3 << 2)#       define VBI_TIMER_COUNT(x)                         ((x) << 4)#       define VBI_TIMER_COUNT_MASK                       (0x3fff << 4)#       define VBI_TIMER_UNIT(x)                          ((x) << 20)#       define VBI_TIMER_UNIT_MASK                        (7 << 20)#       define DISP1_GAP_MCHG(x)                          ((x) << 24)#       define DISP1_GAP_MCHG_MASK                        (3 << 24)#       define DISP2_GAP_MCHG(x)                          ((x) << 26)#       define DISP2_GAP_MCHG_MASK                        (3 << 26) #define	CG_ULV_CONTROL					0x21e#define	CG_ULV_PARAMETER				0x21f #define	SMC_SCRATCH0					0x221 #define	CG_CAC_CTRL					0x22e#	define CAC_WINDOW(x)				((x) << 0)#	define CAC_WINDOW_MASK				0x00ffffff #define DMIF_ADDR_CONFIG  				0x2F5 #define DMIF_ADDR_CALC  				0x300 #define	PIPE0_DMIF_BUFFER_CONTROL			  0x0328#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4) #define	SRBM_STATUS				        0x394#define		GRBM_RQ_PENDING 			(1 << 5)#define		VMC_BUSY 				(1 << 8)#define		MCB_BUSY 				(1 << 9)#define		MCB_NON_DISPLAY_BUSY 			(1 << 10)#define		MCC_BUSY 				(1 << 11)#define		MCD_BUSY 				(1 << 12)#define		SEM_BUSY 				(1 << 14)#define		IH_BUSY 				(1 << 17) #define	SRBM_SOFT_RESET				        0x398#define		SOFT_RESET_BIF				(1 << 1)#define		SOFT_RESET_DC				(1 << 5)#define		SOFT_RESET_DMA1				(1 << 6)#define		SOFT_RESET_GRBM				(1 << 8)#define		SOFT_RESET_HDP				(1 << 9)#define		SOFT_RESET_IH				(1 << 10)#define		SOFT_RESET_MC				(1 << 11)#define		SOFT_RESET_ROM				(1 << 14)#define		SOFT_RESET_SEM				(1 << 15)#define		SOFT_RESET_VMC				(1 << 17)#define		SOFT_RESET_DMA				(1 << 20)#define		SOFT_RESET_TST				(1 << 21)#define		SOFT_RESET_REGBB			(1 << 22)#define		SOFT_RESET_ORB				(1 << 23) #define	CC_SYS_RB_BACKEND_DISABLE			0x3A0#define	GC_USER_SYS_RB_BACKEND_DISABLE			0x3A1 #define SRBM_READ_ERROR					0x3A6#define SRBM_INT_CNTL					0x3A8#define SRBM_INT_ACK					0x3AA #define	SRBM_STATUS2				        0x3B1#define		DMA_BUSY 				(1 << 5)#define		DMA1_BUSY 				(1 << 6) #define VM_L2_CNTL					0x500#define		ENABLE_L2_CACHE					(1 << 0)#define		ENABLE_L2_FRAGMENT_PROCESSING			(1 << 1)#define		L2_CACHE_PTE_ENDIAN_SWAP_MODE(x)		((x) << 2)#define		L2_CACHE_PDE_ENDIAN_SWAP_MODE(x)		((x) << 4)#define		ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE		(1 << 9)#define		ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE	(1 << 10)#define		EFFECTIVE_L2_QUEUE_SIZE(x)			(((x) & 7) << 15)#define		CONTEXT1_IDENTITY_ACCESS_MODE(x)		(((x) & 3) << 19)#define VM_L2_CNTL2					0x501#define		INVALIDATE_ALL_L1_TLBS				(1 << 0)#define		INVALIDATE_L2_CACHE				(1 << 1)#define		INVALIDATE_CACHE_MODE(x)			((x) << 26)#define			INVALIDATE_PTE_AND_PDE_CACHES		0#define			INVALIDATE_ONLY_PTE_CACHES		1#define			INVALIDATE_ONLY_PDE_CACHES		2#define VM_L2_CNTL3					0x502#define		BANK_SELECT(x)					((x) << 0)#define		L2_CACHE_UPDATE_MODE(x)				((x) << 6)#define		L2_CACHE_BIGK_FRAGMENT_SIZE(x)			((x) << 15)#define		L2_CACHE_BIGK_ASSOCIATIVITY			(1 << 20)#define	VM_L2_STATUS					0x503#define		L2_BUSY						(1 << 0)#define VM_CONTEXT0_CNTL				0x504#define		ENABLE_CONTEXT					(1 << 0)#define		PAGE_TABLE_DEPTH(x)				(((x) & 3) << 1)#define		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 3)#define		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 4)#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT	(1 << 6)#define		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT	(1 << 7)#define		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 9)#define		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 10)#define		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 12)#define		VALID_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 13)#define		READ_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 15)#define		READ_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 16)#define		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT		(1 << 18)#define		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT		(1 << 19)#define		PAGE_TABLE_BLOCK_SIZE(x)			(((x) & 0xF) << 24)#define VM_CONTEXT1_CNTL				0x505#define VM_CONTEXT0_CNTL2				0x50C#define VM_CONTEXT1_CNTL2				0x50D#define	VM_CONTEXT8_PAGE_TABLE_BASE_ADDR		0x50E#define	VM_CONTEXT9_PAGE_TABLE_BASE_ADDR		0x50F#define	VM_CONTEXT10_PAGE_TABLE_BASE_ADDR		0x510#define	VM_CONTEXT11_PAGE_TABLE_BASE_ADDR		0x511#define	VM_CONTEXT12_PAGE_TABLE_BASE_ADDR		0x512#define	VM_CONTEXT13_PAGE_TABLE_BASE_ADDR		0x513#define	VM_CONTEXT14_PAGE_TABLE_BASE_ADDR		0x514#define	VM_CONTEXT15_PAGE_TABLE_BASE_ADDR		0x515 #define	VM_CONTEXT1_PROTECTION_FAULT_ADDR		0x53f#define	VM_CONTEXT1_PROTECTION_FAULT_STATUS		0x537#define		PROTECTIONS_MASK			(0xf << 0)#define		PROTECTIONS_SHIFT			0		/* bit 0: range		 * bit 1: pde0		 * bit 2: valid		 * bit 3: read		 * bit 4: write		 */#define		MEMORY_CLIENT_ID_MASK			(0xff << 12)#define		MEMORY_CLIENT_ID_SHIFT			12#define		MEMORY_CLIENT_RW_MASK			(1 << 24)#define		MEMORY_CLIENT_RW_SHIFT			24#define		FAULT_VMID_MASK				(0xf << 25)#define		FAULT_VMID_SHIFT			25 #define VM_INVALIDATE_REQUEST				0x51E#define VM_INVALIDATE_RESPONSE				0x51F #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR	0x546#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR	0x547 #define	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR		0x54F#define	VM_CONTEXT1_PAGE_TABLE_BASE_ADDR		0x550#define	VM_CONTEXT2_PAGE_TABLE_BASE_ADDR		0x551#define	VM_CONTEXT3_PAGE_TABLE_BASE_ADDR		0x552#define	VM_CONTEXT4_PAGE_TABLE_BASE_ADDR		0x553#define	VM_CONTEXT5_PAGE_TABLE_BASE_ADDR		0x554#define	VM_CONTEXT6_PAGE_TABLE_BASE_ADDR		0x555#define	VM_CONTEXT7_PAGE_TABLE_BASE_ADDR		0x556#define	VM_CONTEXT0_PAGE_TABLE_START_ADDR		0x557#define	VM_CONTEXT1_PAGE_TABLE_START_ADDR		0x558 #define	VM_CONTEXT0_PAGE_TABLE_END_ADDR			0x55F#define	VM_CONTEXT1_PAGE_TABLE_END_ADDR			0x560 #define VM_L2_CG           				0x570#define		MC_CG_ENABLE				(1 << 18)#define		MC_LS_ENABLE				(1 << 19) #define MC_SHARED_CHMAP						0x801#define		NOOFCHAN_SHIFT					12#define		NOOFCHAN_MASK					0x0000f000#define MC_SHARED_CHREMAP					0x802 #define	MC_VM_FB_LOCATION				0x809#define	MC_VM_AGP_TOP					0x80A#define	MC_VM_AGP_BOT					0x80B#define	MC_VM_AGP_BASE					0x80C#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x80D#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x80E#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x80F #define	MC_VM_MX_L1_TLB_CNTL				0x819#define		ENABLE_L1_TLB					(1 << 0)#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6) #define MC_SHARED_BLACKOUT_CNTL           		0x82B #define MC_HUB_MISC_HUB_CG           			0x82E#define MC_HUB_MISC_VM_CG           			0x82F #define MC_HUB_MISC_SIP_CG           			0x830 #define MC_XPB_CLK_GAT           			0x91E #define MC_CITF_MISC_RD_CG           			0x992#define MC_CITF_MISC_WR_CG           			0x993#define MC_CITF_MISC_VM_CG           			0x994 #define	MC_ARB_RAMCFG					0x9D8#define		NOOFBANK_SHIFT					0

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