/* * Processor capabilities determination functions. * * Copyright (C) xxxx  the Anonymous * Copyright (C) 1994 - 2006 Ralf Baechle * Copyright (C) 2003, 2004  Maciej W. Rozycki * Copyright (C) 2001, 2004, 2011, 2012	 MIPS Technologies, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */#include <linux/init.h>#include <linux/kernel.h>#include <linux/ptrace.h>#include <linux/smp.h>#include <linux/stddef.h>#include <linux/export.h> #include <asm/bugs.h>#include <asm/cpu.h>#include <asm/cpu-features.h>#include <asm/cpu-type.h>#include <asm/fpu.h>#include <asm/mipsregs.h>#include <asm/mipsmtregs.h>#include <asm/msa.h>#include <asm/watch.h>#include <asm/elf.h>#include <asm/pgtable-bits.h>#include <asm/spram.h>#include <asm/uaccess.h> /* * Get the FPU Implementation/Revision. */static inline unsigned long cpu_get_fpu_id(void){	unsigned long tmp, fpu_id; 	tmp = read_c0_status();	__enable_fpu(FPU_AS_IS);	fpu_id = read_32bit_cp1_register(CP1_REVISION);	write_c0_status(tmp);	return fpu_id;} /* * Check if the CPU has an external FPU. */static inline int __cpu_has_fpu(void){	return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;} static inline unsigned long cpu_get_msa_id(void){	unsigned long status, msa_id; 	status = read_c0_status();	__enable_fpu(FPU_64BIT);	enable_msa();	msa_id = read_msa_ir();	disable_msa();	write_c0_status(status);	return msa_id;} /* * Determine the FCSR mask for FPU hardware. */static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c){	unsigned long sr, mask, fcsr, fcsr0, fcsr1; 	fcsr = c->fpu_csr31;	mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 	sr = read_c0_status();	__enable_fpu(FPU_AS_IS); 	fcsr0 = fcsr & mask;	write_32bit_cp1_register(CP1_STATUS, fcsr0);	fcsr0 = read_32bit_cp1_register(CP1_STATUS); 	fcsr1 = fcsr | ~mask;	write_32bit_cp1_register(CP1_STATUS, fcsr1);	fcsr1 = read_32bit_cp1_register(CP1_STATUS); 	write_32bit_cp1_register(CP1_STATUS, fcsr); 	write_c0_status(sr); 	c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;} /* * Set the FIR feature flags for the FPU emulator. */static void cpu_set_nofpu_id(struct cpuinfo_mips *c){	u32 value; 	value = 0;	if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |			    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))		value |= MIPS_FPIR_D | MIPS_FPIR_S;	if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))		value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;	c->fpu_id = value;} /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */static unsigned int mips_nofpu_msk31; /* * Set options for FPU hardware. */static void cpu_set_fpu_opts(struct cpuinfo_mips *c){	c->fpu_id = cpu_get_fpu_id();	mips_nofpu_msk31 = c->fpu_msk31; 	if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |			    MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {		if (c->fpu_id & MIPS_FPIR_3D)			c->ases |= MIPS_ASE_MIPS3D;		if (c->fpu_id & MIPS_FPIR_FREP)			c->options |= MIPS_CPU_FRE;	} 	cpu_set_fpu_fcsr_mask(c);} /* * Set options for the FPU emulator. */static void cpu_set_nofpu_opts(struct cpuinfo_mips *c){	c->options &= ~MIPS_CPU_FPU;	c->fpu_msk31 = mips_nofpu_msk31; 	cpu_set_nofpu_id(c);} static int mips_fpu_disabled; static int __init fpu_disable(char *s){	cpu_set_nofpu_opts(&boot_cpu_data);	mips_fpu_disabled = 1; 	return 1;} __setup("nofpu", fpu_disable); int mips_dsp_disabled; static int __init dsp_disable(char *s){	cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);	mips_dsp_disabled = 1; 	return 1;} __setup("nodsp", dsp_disable); static int mips_htw_disabled; static int __init htw_disable(char *s){	mips_htw_disabled = 1;	cpu_data[0].options &= ~MIPS_CPU_HTW;	write_c0_pwctl(read_c0_pwctl() &		       ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 	return 1;} __setup("nohtw", htw_disable); static int mips_ftlb_disabled;static int mips_has_ftlb_configured; static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); static int __init ftlb_disable(char *s){	unsigned int config4, mmuextdef; 	/*	 * If the core hasn't done any FTLB configuration, there is nothing	 * for us to do here.	 */	if (!mips_has_ftlb_configured)		return 1; 	/* Disable it in the boot cpu */	set_ftlb_enable(&cpu_data[0], 0); 	back_to_back_c0_hazard(); 	config4 = read_c0_config4(); 	/* Check that FTLB has been disabled */	mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;	/* MMUSIZEEXT == VTLB ON, FTLB OFF */	if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {		/* This should never happen */		pr_warn("FTLB could not be disabled!\n");		return 1;	} 	mips_ftlb_disabled = 1;	mips_has_ftlb_configured = 0; 	/*	 * noftlb is mainly used for debug purposes so print	 * an informative message instead of using pr_debug()	 */	pr_info("FTLB has been disabled\n"); 	/*	 * Some of these bits are duplicated in the decode_config4.	 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case	 * once FTLB has been disabled so undo what decode_config4 did.	 */	cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *			       cpu_data[0].tlbsizeftlbsets;	cpu_data[0].tlbsizeftlbsets = 0;	cpu_data[0].tlbsizeftlbways = 0; 	return 1;} __setup("noftlb", ftlb_disable);  static inline void check_errata(void){	struct cpuinfo_mips *c = &current_cpu_data; 	switch (current_cpu_type()) {	case CPU_34K:		/*		 * Erratum "RPS May Cause Incorrect Instruction Execution"		 * This code only handles VPE0, any SMP/RTOS code		 * making use of VPE1 will be responsable for that VPE.		 */		if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)			write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);		break;	default:		break;	}} void __init check_bugs32(void){	check_errata();} /* * Probe whether cpu has config register by trying to play with * alternate cache bit and see whether it matters. * It's used by cpu_probe to distinguish between R3000A and R3081. */static inline int cpu_has_confreg(void){#ifdef CONFIG_CPU_R3000	extern unsigned long r3k_cache_size(unsigned long);	unsigned long size1, size2;	unsigned long cfg = read_c0_conf(); 	size1 = r3k_cache_size(ST0_ISC);	write_c0_conf(cfg ^ R30XX_CONF_AC);	size2 = r3k_cache_size(ST0_ISC);	write_c0_conf(cfg);	return size1 != size2;#else	return 0;#endif} static inline void set_elf_platform(int cpu, const char *plat){	if (cpu == 0)		__elf_platform = plat;} static inline void cpu_probe_vmbits(struct cpuinfo_mips *c){#ifdef __NEED_VMBITS_PROBE	write_c0_entryhi(0x3fffffffffffe000ULL);	back_to_back_c0_hazard();	c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);#endif} static void set_isa(struct cpuinfo_mips *c, unsigned int isa){	switch (isa) {	case MIPS_CPU_ISA_M64R2:		c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;	case MIPS_CPU_ISA_M64R1:		c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;	case MIPS_CPU_ISA_V:		c->isa_level |= MIPS_CPU_ISA_V;	case MIPS_CPU_ISA_IV:		c->isa_level |= MIPS_CPU_ISA_IV;	case MIPS_CPU_ISA_III:		c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;		break; 	/* R6 incompatible with everything else */	case MIPS_CPU_ISA_M64R6:		c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;	case MIPS_CPU_ISA_M32R6:		c->isa_level |= MIPS_CPU_ISA_M32R6;		/* Break here so we don't add incompatible ISAs */		break;	case MIPS_CPU_ISA_M32R2:		c->isa_level |= MIPS_CPU_ISA_M32R2;	case MIPS_CPU_ISA_M32R1:		c->isa_level |= MIPS_CPU_ISA_M32R1;	case MIPS_CPU_ISA_II:		c->isa_level |= MIPS_CPU_ISA_II;		break;	}} static char unknown_isa[] = KERN_ERR \	"Unsupported ISA type, c0.config0: %d."; static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c){ 	unsigned int probability = c->tlbsize / c->tlbsizevtlb; 	/*	 * 0 = All TLBWR instructions go to FTLB	 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the	 * FTLB and 1 goes to the VTLB.	 * 2 = 7:1: As above with 7:1 ratio.	 * 3 = 3:1: As above with 3:1 ratio.	 *	 * Use the linear midpoint as the probability threshold.	 */	if (probability >= 12)		return 1;	else if (probability >= 6)		return 2;	else		/*		 * So FTLB is less than 4 times bigger than VTLB.		 * A 3:1 ratio can still be useful though.		 */		return 3;} static void set_ftlb_enable(struct cpuinfo_mips *c, int enable){	unsigned int config6; 	/* It's implementation dependent how the FTLB can be enabled */	switch (c->cputype) {	case CPU_PROAPTIV:	case CPU_P5600:		/* proAptiv & related cores use Config6 to enable the FTLB */		config6 = read_c0_config6();		/* Clear the old probability value */		config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);		if (enable)			/* Enable FTLB */			write_c0_config6(config6 |					 (calculate_ftlb_probability(c)					  << MIPS_CONF6_FTLBP_SHIFT)					 | MIPS_CONF6_FTLBEN);		else			/* Disable FTLB */			write_c0_config6(config6 &  ~MIPS_CONF6_FTLBEN);		back_to_back_c0_hazard();		break;	}} static inline unsigned int decode_config0(struct cpuinfo_mips *c){	unsigned int config0;	int isa; 	config0 = read_c0_config(); 	/*	 * Look for Standard TLB or Dual VTLB and FTLB	 */	if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||	    (((config0 & MIPS_CONF_MT) >> 7) == 4))		c->options |= MIPS_CPU_TLB; 	isa = (config0 & MIPS_CONF_AT) >> 13;	switch (isa) {	case 0:		switch ((config0 & MIPS_CONF_AR) >> 10) {		case 0:			set_isa(c, MIPS_CPU_ISA_M32R1);			break;		case 1:			set_isa(c, MIPS_CPU_ISA_M32R2);			break;		case 2:			set_isa(c, MIPS_CPU_ISA_M32R6);			break;		default:			goto unknown;		}		break;	case 2:		switch ((config0 & MIPS_CONF_AR) >> 10) {		case 0:			set_isa(c, MIPS_CPU_ISA_M64R1);			break;		case 1:			set_isa(c, MIPS_CPU_ISA_M64R2);			break;		case 2:			set_isa(c, MIPS_CPU_ISA_M64R6);			break;		default:			goto unknown;		}		break;	default:		goto unknown;	} 	return config0 & MIPS_CONF_M; unknown:	panic(unknown_isa, config0);} static inline unsigned int decode_config1(struct cpuinfo_mips *c){	unsigned int config1; 	config1 = read_c0_config1(); 	if (config1 & MIPS_CONF1_MD)		c->ases |= MIPS_ASE_MDMX;	if (config1 & MIPS_CONF1_WR)		c->options |= MIPS_CPU_WATCH;	if (config1 & MIPS_CONF1_CA)		c->ases |= MIPS_ASE_MIPS16;	if (config1 & MIPS_CONF1_EP)		c->options |= MIPS_CPU_EJTAG;	if (config1 & MIPS_CONF1_FP) {		c->options |= MIPS_CPU_FPU;		c->options |= MIPS_CPU_32FPR;	}	if (cpu_has_tlb) {		c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;		c->tlbsizevtlb = c->tlbsize;		c->tlbsizeftlbsets = 0;	} 	return config1 & MIPS_CONF_M;} static inline unsigned int decode_config2(struct cpuinfo_mips *c){	unsigned int config2; 	config2 = read_c0_config2(); 	if (config2 & MIPS_CONF2_SL)		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 	return config2 & MIPS_CONF_M;} static inline unsigned int decode_config3(struct cpuinfo_mips *c){	unsigned int config3; 	config3 = read_c0_config3(); 	if (config3 & MIPS_CONF3_SM) {		c->ases |= MIPS_ASE_SMARTMIPS;		c->options |= MIPS_CPU_RIXI;	}	if (config3 & MIPS_CONF3_RXI)		c->options |= MIPS_CPU_RIXI;	if (config3 & MIPS_CONF3_DSP)

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