/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#ifndef __AMDGPU_H__#define __AMDGPU_H__ #include "amdgpu_ctx.h" #include <linux/atomic.h>#include <linux/wait.h>#include <linux/list.h>#include <linux/kref.h>#include <linux/rbtree.h>#include <linux/hashtable.h>#include <linux/dma-fence.h> #include <drm/ttm/ttm_bo_api.h>#include <drm/ttm/ttm_bo_driver.h>#include <drm/ttm/ttm_placement.h>#include <drm/ttm/ttm_module.h>#include <drm/ttm/ttm_execbuf_util.h> #include <drm/drmP.h>#include <drm/drm_gem.h>#include <drm/amdgpu_drm.h>#include <drm/gpu_scheduler.h> #include <kgd_kfd_interface.h>#include "dm_pp_interface.h"#include "kgd_pp_interface.h" #include "amd_shared.h"#include "amdgpu_mode.h"#include "amdgpu_ih.h"#include "amdgpu_irq.h"#include "amdgpu_ucode.h"#include "amdgpu_ttm.h"#include "amdgpu_psp.h"#include "amdgpu_gds.h"#include "amdgpu_sync.h"#include "amdgpu_ring.h"#include "amdgpu_vm.h"#include "amdgpu_dpm.h"#include "amdgpu_acp.h"#include "amdgpu_uvd.h"#include "amdgpu_vce.h"#include "amdgpu_vcn.h"#include "amdgpu_mn.h"#include "amdgpu_gmc.h"#include "amdgpu_gfx.h"#include "amdgpu_sdma.h"#include "amdgpu_dm.h"#include "amdgpu_virt.h"#include "amdgpu_gart.h"#include "amdgpu_debugfs.h"#include "amdgpu_job.h"#include "amdgpu_bo_list.h"#include "amdgpu_gem.h" #define MAX_GPU_INSTANCE		16 struct amdgpu_gpu_instance{	struct amdgpu_device		*adev;	int				mgpu_fan_enabled;}; struct amdgpu_mgpu_info{	struct amdgpu_gpu_instance	gpu_ins[MAX_GPU_INSTANCE];	struct mutex			mutex;	uint32_t			num_gpu;	uint32_t			num_dgpu;	uint32_t			num_apu;}; /* * Modules parameters. */extern int amdgpu_modeset;extern int amdgpu_vram_limit;extern int amdgpu_vis_vram_limit;extern int amdgpu_gart_size;extern int amdgpu_gtt_size;extern int amdgpu_moverate;extern int amdgpu_benchmarking;extern int amdgpu_testing;extern int amdgpu_audio;extern int amdgpu_disp_priority;extern int amdgpu_hw_i2c;extern int amdgpu_pcie_gen2;extern int amdgpu_msi;extern int amdgpu_lockup_timeout;extern int amdgpu_dpm;extern int amdgpu_fw_load_type;extern int amdgpu_aspm;extern int amdgpu_runtime_pm;extern uint amdgpu_ip_block_mask;extern int amdgpu_bapm;extern int amdgpu_deep_color;extern int amdgpu_vm_size;extern int amdgpu_vm_block_size;extern int amdgpu_vm_fragment_size;extern int amdgpu_vm_fault_stop;extern int amdgpu_vm_debug;extern int amdgpu_vm_update_mode;extern int amdgpu_dc;extern int amdgpu_sched_jobs;extern int amdgpu_sched_hw_submission;extern uint amdgpu_pcie_gen_cap;extern uint amdgpu_pcie_lane_cap;extern uint amdgpu_cg_mask;extern uint amdgpu_pg_mask;extern uint amdgpu_sdma_phase_quantum;extern char *amdgpu_disable_cu;extern char *amdgpu_virtual_display;extern uint amdgpu_pp_feature_mask;extern int amdgpu_vram_page_split;extern int amdgpu_ngg;extern int amdgpu_prim_buf_per_se;extern int amdgpu_pos_buf_per_se;extern int amdgpu_cntl_sb_buf_per_se;extern int amdgpu_param_buf_per_se;extern int amdgpu_job_hang_limit;extern int amdgpu_lbpw;extern int amdgpu_compute_multipipe;extern int amdgpu_gpu_recovery;extern int amdgpu_emu_mode;extern uint amdgpu_smu_memory_pool_size;extern uint amdgpu_dc_feature_mask;extern struct amdgpu_mgpu_info mgpu_info; #ifdef CONFIG_DRM_AMDGPU_SIextern int amdgpu_si_support;#endif#ifdef CONFIG_DRM_AMDGPU_CIKextern int amdgpu_cik_support;#endif #define AMDGPU_SG_THRESHOLD			(256*1024*1024)#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)/* AMDGPU_IB_POOL_SIZE must be a power of 2 */#define AMDGPU_IB_POOL_SIZE			16#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32#define AMDGPUFB_CONN_LIMIT			4#define AMDGPU_BIOS_NUM_SCRATCH			16 /* hard reset data */#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b /* reset flags */#define AMDGPU_RESET_GFX			(1 << 0)#define AMDGPU_RESET_COMPUTE			(1 << 1)#define AMDGPU_RESET_DMA			(1 << 2)#define AMDGPU_RESET_CP				(1 << 3)#define AMDGPU_RESET_GRBM			(1 << 4)#define AMDGPU_RESET_DMA1			(1 << 5)#define AMDGPU_RESET_RLC			(1 << 6)#define AMDGPU_RESET_SEM			(1 << 7)#define AMDGPU_RESET_IH				(1 << 8)#define AMDGPU_RESET_VMC			(1 << 9)#define AMDGPU_RESET_MC				(1 << 10)#define AMDGPU_RESET_DISPLAY			(1 << 11)#define AMDGPU_RESET_UVD			(1 << 12)#define AMDGPU_RESET_VCE			(1 << 13)#define AMDGPU_RESET_VCE1			(1 << 14) /* max cursor sizes (in pixels) */#define CIK_CURSOR_WIDTH 128#define CIK_CURSOR_HEIGHT 128 struct amdgpu_device;struct amdgpu_ib;struct amdgpu_cs_parser;struct amdgpu_job;struct amdgpu_irq_src;struct amdgpu_fpriv;struct amdgpu_bo_va_mapping;struct amdgpu_atif; enum amdgpu_cp_irq {	AMDGPU_CP_IRQ_GFX_EOP = 0,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 	AMDGPU_CP_IRQ_LAST}; enum amdgpu_thermal_irq {	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 	AMDGPU_THERMAL_IRQ_LAST}; enum amdgpu_kiq_irq {	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,	AMDGPU_CP_KIQ_IRQ_LAST}; #define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ int amdgpu_device_ip_set_clockgating_state(void *dev,					   enum amd_ip_block_type block_type,					   enum amd_clockgating_state state);int amdgpu_device_ip_set_powergating_state(void *dev,					   enum amd_ip_block_type block_type,					   enum amd_powergating_state state);void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,					    u32 *flags);int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,				   enum amd_ip_block_type block_type);bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,			      enum amd_ip_block_type block_type); #define AMDGPU_MAX_IP_NUM 16 struct amdgpu_ip_block_status {	bool valid;	bool sw;	bool hw;	bool late_initialized;	bool hang;}; struct amdgpu_ip_block_version {	const enum amd_ip_block_type type;	const u32 major;	const u32 minor;	const u32 rev;	const struct amd_ip_funcs *funcs;}; struct amdgpu_ip_block {	struct amdgpu_ip_block_status status;	const struct amdgpu_ip_block_version *version;}; int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,				       enum amd_ip_block_type type,				       u32 major, u32 minor); struct amdgpu_ip_block *amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,			      enum amd_ip_block_type type); int amdgpu_device_ip_block_add(struct amdgpu_device *adev,			       const struct amdgpu_ip_block_version *ip_block_version); /* * BIOS. */bool amdgpu_get_bios(struct amdgpu_device *adev);bool amdgpu_read_bios(struct amdgpu_device *adev); /* * Clocks */ #define AMDGPU_MAX_PPLL 3 struct amdgpu_clock {	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];	struct amdgpu_pll spll;	struct amdgpu_pll mpll;	/* 10 Khz units */	uint32_t default_mclk;	uint32_t default_sclk;	uint32_t default_dispclk;	uint32_t current_dispclk;	uint32_t dp_extclk;	uint32_t max_pixel_clock;}; /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their * locking. * * Principe is simple, we keep a list of sub allocation in offset * order (first entry has offset == 0, last entry has the highest * offset). * * When allocating new object we first check if there is room at * the end total_size - (last_object_offset + last_object_size) >= * alloc_size. If so we allocate new object there. * * When there is not enough room at the end, we start waiting for * each sub object until we reach object_offset+object_size >= * alloc_size, this object then become the sub object we return. * * Alignment can't be bigger than page size. * * Hole are not considered for allocation to keep things simple. * Assumption is that there won't be hole (all object on same * alignment). */ #define AMDGPU_SA_NUM_FENCE_LISTS	32 struct amdgpu_sa_manager {	wait_queue_head_t	wq;	struct amdgpu_bo	*bo;	struct list_head	*hole;	struct list_head	flist[AMDGPU_SA_NUM_FENCE_LISTS];	struct list_head	olist;	unsigned		size;	uint64_t		gpu_addr;	void			*cpu_ptr;	uint32_t		domain;	uint32_t		align;}; /* sub-allocation buffer */struct amdgpu_sa_bo {	struct list_head		olist;	struct list_head		flist;	struct amdgpu_sa_manager	*manager;	unsigned			soffset;	unsigned			eoffset;	struct dma_fence	        *fence;}; int amdgpu_fence_slab_init(void);void amdgpu_fence_slab_fini(void); /* * GPU doorbell structures, functions & helpers */typedef enum _AMDGPU_DOORBELL_ASSIGNMENT{	AMDGPU_DOORBELL_KIQ                     = 0x000,	AMDGPU_DOORBELL_HIQ                     = 0x001,	AMDGPU_DOORBELL_DIQ                     = 0x002,	AMDGPU_DOORBELL_MEC_RING0               = 0x010,	AMDGPU_DOORBELL_MEC_RING1               = 0x011,	AMDGPU_DOORBELL_MEC_RING2               = 0x012,	AMDGPU_DOORBELL_MEC_RING3               = 0x013,	AMDGPU_DOORBELL_MEC_RING4               = 0x014,	AMDGPU_DOORBELL_MEC_RING5               = 0x015,	AMDGPU_DOORBELL_MEC_RING6               = 0x016,	AMDGPU_DOORBELL_MEC_RING7               = 0x017,	AMDGPU_DOORBELL_GFX_RING0               = 0x020,	AMDGPU_DOORBELL_sDMA_ENGINE0            = 0x1E0,	AMDGPU_DOORBELL_sDMA_ENGINE1            = 0x1E1,	AMDGPU_DOORBELL_IH                      = 0x1E8,	AMDGPU_DOORBELL_MAX_ASSIGNMENT          = 0x3FF,	AMDGPU_DOORBELL_INVALID                 = 0xFFFF} AMDGPU_DOORBELL_ASSIGNMENT; struct amdgpu_doorbell {	/* doorbell mmio */	resource_size_t		base;	resource_size_t		size;	u32 __iomem		*ptr;	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */}; /* * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space */typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT{	/*	 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in	 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.	 *  Compute related doorbells are allocated from 0x00 to 0x8a	 */  	/* kernel scheduling */	AMDGPU_DOORBELL64_KIQ                     = 0x00, 	/* HSA interface queue and debug queue */	AMDGPU_DOORBELL64_HIQ                     = 0x01,	AMDGPU_DOORBELL64_DIQ                     = 0x02, 	/* Compute engines */	AMDGPU_DOORBELL64_MEC_RING0               = 0x03,	AMDGPU_DOORBELL64_MEC_RING1               = 0x04,	AMDGPU_DOORBELL64_MEC_RING2               = 0x05,	AMDGPU_DOORBELL64_MEC_RING3               = 0x06,	AMDGPU_DOORBELL64_MEC_RING4               = 0x07,	AMDGPU_DOORBELL64_MEC_RING5               = 0x08,	AMDGPU_DOORBELL64_MEC_RING6               = 0x09,	AMDGPU_DOORBELL64_MEC_RING7               = 0x0a, 	/* User queue doorbell range (128 doorbells) */	AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,	AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a, 	/* Graphics engine */	AMDGPU_DOORBELL64_GFX_RING0               = 0x8b, 	/*	 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf	 * Graphics voltage island aperture 1	 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive	 */ 	/* sDMA engines  reserved from 0xe0 -oxef  */	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xE0,	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xE1,	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xE8,	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xE9, 	/* For vega10 sriov, the sdma doorbell must be fixed as follow	 * to keep the same setting with host driver, or it will	 * happen conflicts	 */	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0            = 0xF0,	AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,	AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1            = 0xF2,	AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3, 	/* Interrupt handler */	AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */	AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */	AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */ 	/* VCN engine use 32 bits doorbell  */	AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */	AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,	AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,	AMDGPU_DOORBELL64_VCN6_7                  = 0xFB, 	/* overlap the doorbell assignment with VCN as they are  mutually exclusive	 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD	 */	AMDGPU_DOORBELL64_UVD_RING0_1             = 0xF8,	AMDGPU_DOORBELL64_UVD_RING2_3             = 0xF9,	AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFA,	AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFB, 	AMDGPU_DOORBELL64_VCE_RING0_1             = 0xFC,	AMDGPU_DOORBELL64_VCE_RING2_3             = 0xFD,	AMDGPU_DOORBELL64_VCE_RING4_5             = 0xFE,	AMDGPU_DOORBELL64_VCE_RING6_7             = 0xFF, 	AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,	AMDGPU_DOORBELL64_INVALID                 = 0xFFFF} AMDGPU_DOORBELL64_ASSIGNMENT; /* * IRQS. */ struct amdgpu_flip_work {	struct delayed_work		flip_work;	struct work_struct		unpin_work;	struct amdgpu_device		*adev;	int				crtc_id;	u32				target_vblank;	uint64_t			base;	struct drm_pending_vblank_event *event;	struct amdgpu_bo		*old_abo;	struct dma_fence		*excl;	unsigned			shared_count;	struct dma_fence		**shared;	struct dma_fence_cb		cb;	bool				async;};  /*

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