/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */#include <drm/drmP.h>#include <drm/amdgpu_drm.h>#include "amdgpu.h"#include "amdgpu_trace.h" /* * GPUVM * GPUVM is similar to the legacy gart on older asics, however * rather than there being a single global gart table * for the entire GPU, there are multiple VM page tables active * at any given time. The VM page tables can contain a mix * vram pages and system memory pages and system memory pages * can be mapped as snooped (cached system pages) or unsnooped * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID. When execting a command buffer, * the kernel tells the the ring what VMID to use for that command * buffer. VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their * command buffers and a VMID is assigned. * Cayman/Trinity support up to 8 active VMs at any given time; * SI supports 16. */ /** * amdgpu_vm_num_pde - return the number of page directory entries * * @adev: amdgpu_device pointer * * Calculate the number of page directory entries (cayman+). */static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev){ return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;} /** * amdgpu_vm_directory_size - returns the size of the page directory in bytes * * @adev: amdgpu_device pointer * * Calculate the size of the page directory in bytes (cayman+). */static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev){ return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);} /** * amdgpu_vm_get_bos - add the vm BOs to a validation list * * @vm: vm providing the BOs * @head: head of validation list * * Add the page directory to the list of BOs to * validate for command submission (cayman+). */struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct list_head *head){ struct amdgpu_bo_list_entry *list; unsigned i, idx; list = drm_malloc_ab(vm->max_pde_used + 2, sizeof(struct amdgpu_bo_list_entry)); if (!list) { return NULL; } /* add the vm page table to the list */ list[0].robj = vm->page_directory; list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; list[0].priority = 0; list[0].tv.bo = &vm->page_directory->tbo; list[0].tv.shared = true; list_add(&list[0].tv.head, head); for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { if (!vm->page_tables[i].bo) continue; list[idx].robj = vm->page_tables[i].bo; list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; list[idx].priority = 0; list[idx].tv.bo = &list[idx].robj->tbo; list[idx].tv.shared = true; list_add(&list[idx++].tv.head, head); } return list;} /** * amdgpu_vm_grab_id - allocate the next free VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to * @sync: sync object where we add dependencies * * Allocate an id for the vm, adding fences to the sync obj as necessary. * * Global mutex must be locked! */int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync){ struct fence *best[AMDGPU_MAX_RINGS] = {}; struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; struct amdgpu_device *adev = ring->adev; unsigned choices[2] = {}; unsigned i; /* check if the id is still valid */ if (vm_id->id) { unsigned id = vm_id->id; long owner; owner = atomic_long_read(&adev->vm_manager.ids[id].owner); if (owner == (long)vm) { trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); return 0; } } /* we definately need to flush */ vm_id->pd_gpu_addr = ~0ll; /* skip over VMID 0, since it is the system VM */ for (i = 1; i < adev->vm_manager.nvm; ++i) { struct fence *fence = adev->vm_manager.ids[i].active; struct amdgpu_ring *fring; if (fence == NULL) { /* found a free one */ vm_id->id = i; trace_amdgpu_vm_grab_id(i, ring->idx); return 0; } fring = amdgpu_ring_from_fence(fence); if (best[fring->idx] == NULL || fence_is_later(best[fring->idx], fence)) { best[fring->idx] = fence; choices[fring == ring ? 0 : 1] = i; } } for (i = 0; i < 2; ++i) { if (choices[i]) { struct fence *fence; fence = adev->vm_manager.ids[choices[i]].active; vm_id->id = choices[i]; trace_amdgpu_vm_grab_id(choices[i], ring->idx); return amdgpu_sync_fence(ring->adev, sync, fence); } } /* should never happen */ BUG(); return -EINVAL;} /** * amdgpu_vm_flush - hardware flush the vm * * @ring: ring to use for flush * @vm: vm we want to flush * @updates: last vm update that we waited for * * Flush the vm (cayman+). * * Global and local mutex must be locked! */void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_vm *vm, struct fence *updates){ uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; struct fence *flushed_updates = vm_id->flushed_updates; bool is_later; if (!flushed_updates) is_later = true; else if (!updates) is_later = false; else is_later = fence_is_later(updates, flushed_updates); if (pd_addr != vm_id->pd_gpu_addr || is_later) { trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); if (is_later) { vm_id->flushed_updates = fence_get(updates); fence_put(flushed_updates); } vm_id->pd_gpu_addr = pd_addr; amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); }} /** * amdgpu_vm_fence - remember fence for vm * * @adev: amdgpu_device pointer * @vm: vm we want to fence * @fence: fence to remember * * Fence the vm (cayman+). * Set the fence used to protect page table and id. * * Global and local mutex must be locked! */void amdgpu_vm_fence(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct fence *fence){ struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence); unsigned vm_id = vm->ids[ring->idx].id; fence_put(adev->vm_manager.ids[vm_id].active); adev->vm_manager.ids[vm_id].active = fence_get(fence); atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm);} /** * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo * * @vm: requested vm * @bo: requested buffer object * * Find @bo inside the requested vm (cayman+). * Search inside the @bos vm list for the requested vm * Returns the found bo_va or NULL if none is found * * Object has to be reserved! */struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, struct amdgpu_bo *bo){ struct amdgpu_bo_va *bo_va; list_for_each_entry(bo_va, &bo->va, bo_list) { if (bo_va->vm == vm) { return bo_va; } } return NULL;} /** * amdgpu_vm_update_pages - helper to call the right asic function * * @adev: amdgpu_device pointer * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: hw access flags * @gtt_flags: GTT hw access flags * * Traces the parameters and calls the right asic functions * to setup the page table using the DMA. */static void amdgpu_vm_update_pages(struct amdgpu_device *adev, struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags, uint32_t gtt_flags){ trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; amdgpu_vm_copy_pte(adev, ib, pe, src, count); } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags); } else { amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags); }} int amdgpu_vm_free_job(struct amdgpu_job *job){ int i; for (i = 0; i < job->num_ibs; i++) amdgpu_ib_free(job->adev, &job->ibs[i]); kfree(job->ibs); return 0;} /** * amdgpu_vm_clear_bo - initially clear the page dir/table * * @adev: amdgpu_device pointer * @bo: bo to clear * * need to reserve bo first before calling it. */static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, struct amdgpu_bo *bo){ struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; struct fence *fence = NULL; struct amdgpu_ib *ib; unsigned entries; uint64_t addr; int r; r = reservation_object_reserve_shared(bo->tbo.resv); if (r) return r; r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); if (r) goto error; addr = amdgpu_bo_gpu_offset(bo); entries = amdgpu_bo_size(bo) / 8; ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); if (!ib) goto error; r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); if (r) goto error_free; ib->length_dw = 0; amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0); amdgpu_vm_pad_ib(adev, ib); WARN_ON(ib->length_dw > 64); r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, &amdgpu_vm_free_job, AMDGPU_FENCE_OWNER_VM, &fence); if (!r) amdgpu_bo_fence(bo, fence, true); fence_put(fence); if (amdgpu_enable_scheduler) return 0; error_free: amdgpu_ib_free(adev, ib); kfree(ib); error: return r;} /** * amdgpu_vm_map_gart - get the physical address of a gart page * * @adev: amdgpu_device pointer * @addr: the unmapped addr * * Look up the physical address of the page that the pte resolves * to (cayman+). * Returns the physical address of the page. */uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr){ uint64_t result; /* page table offset */ result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; /* in case cpu page size != gpu page size*/ result |= addr & (~PAGE_MASK); return result;} /** * amdgpu_vm_update_pdes - make sure that page directory is valid * * @adev: amdgpu_device pointer * @vm: requested vm * @start: start of GPU address range * @end: end of GPU address range * * Allocates new page tables if necessary * and updates the page directory (cayman+). * Returns 0 for success, error for failure. * * Global and local mutex must be locked! */int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, struct amdgpu_vm *vm){ struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; struct amdgpu_bo *pd = vm->page_directory; uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; uint64_t last_pde = ~0, last_pt = ~0; unsigned count = 0, pt_idx, ndw; struct amdgpu_ib *ib; struct fence *fence = NULL; int r; /* padding, etc. */ ndw = 64; /* assume the worst case */ ndw += vm->max_pde_used * 6; /* update too big for an IB */ if (ndw > 0xfffff) return -ENOMEM; ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); if (!ib) return -ENOMEM; r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); if (r) { kfree(ib); return r; } ib->length_dw = 0; /* walk over the address space and update the page directory */ for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; uint64_t pde, pt; if (bo == NULL) continue; pt = amdgpu_bo_gpu_offset(bo); if (vm->page_tables[pt_idx].addr == pt) continue; vm->page_tables[pt_idx].addr = pt; pde = pd_addr + pt_idx * 8; if (((last_pde + 8 * count) != pde) || ((last_pt + incr * count) != pt)) { if (count) { amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID, 0); } count = 1; last_pde = pde; last_pt = pt; } else { ++count; } } if (count) amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID, 0); if (ib->length_dw != 0) { amdgpu_vm_pad_ib(adev, ib); amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); WARN_ON(ib->length_dw > ndw);Lines 1–500 of 1357. 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/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include <drm/drmP.h> #include <drm/amdgpu_drm.h> #include "amdgpu.h" #include "amdgpu_trace.h" /* * GPUVM * GPUVM is similar to the legacy gart on older asics, however * rather than there being a single global gart table * for the entire GPU, there are multiple VM page tables active * at any given time. The VM page tables can contain a mix * vram pages and system memory pages and system memory pages * can be mapped as snooped (cached system pages) or unsnooped * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID. When execting a command buffer, * the kernel tells the the ring what VMID to use for that command * buffer. VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their * command buffers and a VMID is assigned. * Cayman/Trinity support up to 8 active VMs at any given time; * SI supports 16. */ /** * amdgpu_vm_num_pde - return the number of page directory entries * * @adev: amdgpu_device pointer * * Calculate the number of page directory entries (cayman+). */ static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev) { return adev->vm_manager.max_pfn >> amdgpu_vm_block_size; } /** * amdgpu_vm_directory_size - returns the size of the page directory in bytes * * @adev: amdgpu_device pointer * * Calculate the size of the page directory in bytes (cayman+). */ static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev) { return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8); } /** * amdgpu_vm_get_bos - add the vm BOs to a validation list * * @vm: vm providing the BOs * @head: head of validation list * * Add the page directory to the list of BOs to * validate for command submission (cayman+). */ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct list_head *head) { struct amdgpu_bo_list_entry *list; unsigned i, idx; list = drm_malloc_ab(vm->max_pde_used + 2, sizeof(struct amdgpu_bo_list_entry)); if (!list) { return NULL; } /* add the vm page table to the list */ list[0].robj = vm->page_directory; list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; list[0].priority = 0; list[0].tv.bo = &vm->page_directory->tbo; list[0].tv.shared = true; list_add(&list[0].tv.head, head); for (i = 0, idx = 1; i <= vm->max_pde_used; i++) { if (!vm->page_tables[i].bo) continue; list[idx].robj = vm->page_tables[i].bo; list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM; list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM; list[idx].priority = 0; list[idx].tv.bo = &list[idx].robj->tbo; list[idx].tv.shared = true; list_add(&list[idx++].tv.head, head); } return list; } /** * amdgpu_vm_grab_id - allocate the next free VMID * * @vm: vm to allocate id for * @ring: ring we want to submit job to * @sync: sync object where we add dependencies * * Allocate an id for the vm, adding fences to the sync obj as necessary. * * Global mutex must be locked! */ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync) { struct fence *best[AMDGPU_MAX_RINGS] = {}; struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; struct amdgpu_device *adev = ring->adev; unsigned choices[2] = {}; unsigned i; /* check if the id is still valid */ if (vm_id->id) { unsigned id = vm_id->id; long owner; owner = atomic_long_read(&adev->vm_manager.ids[id].owner); if (owner == (long)vm) { trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); return 0; } } /* we definately need to flush */ vm_id->pd_gpu_addr = ~0ll; /* skip over VMID 0, since it is the system VM */ for (i = 1; i < adev->vm_manager.nvm; ++i) { struct fence *fence = adev->vm_manager.ids[i].active; struct amdgpu_ring *fring; if (fence == NULL) { /* found a free one */ vm_id->id = i; trace_amdgpu_vm_grab_id(i, ring->idx); return 0; } fring = amdgpu_ring_from_fence(fence); if (best[fring->idx] == NULL || fence_is_later(best[fring->idx], fence)) { best[fring->idx] = fence; choices[fring == ring ? 0 : 1] = i; } } for (i = 0; i < 2; ++i) { if (choices[i]) { struct fence *fence; fence = adev->vm_manager.ids[choices[i]].active; vm_id->id = choices[i]; trace_amdgpu_vm_grab_id(choices[i], ring->idx); return amdgpu_sync_fence(ring->adev, sync, fence); } } /* should never happen */ BUG(); return -EINVAL; } /** * amdgpu_vm_flush - hardware flush the vm * * @ring: ring to use for flush * @vm: vm we want to flush * @updates: last vm update that we waited for * * Flush the vm (cayman+). * * Global and local mutex must be locked! */ void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_vm *vm, struct fence *updates) { uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; struct fence *flushed_updates = vm_id->flushed_updates; bool is_later; if (!flushed_updates) is_later = true; else if (!updates) is_later = false; else is_later = fence_is_later(updates, flushed_updates); if (pd_addr != vm_id->pd_gpu_addr || is_later) { trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); if (is_later) { vm_id->flushed_updates = fence_get(updates); fence_put(flushed_updates); } vm_id->pd_gpu_addr = pd_addr; amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); } } /** * amdgpu_vm_fence - remember fence for vm * * @adev: amdgpu_device pointer * @vm: vm we want to fence * @fence: fence to remember * * Fence the vm (cayman+). * Set the fence used to protect page table and id. * * Global and local mutex must be locked! */ void amdgpu_vm_fence(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct fence *fence) { struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence); unsigned vm_id = vm->ids[ring->idx].id; fence_put(adev->vm_manager.ids[vm_id].active); adev->vm_manager.ids[vm_id].active = fence_get(fence); atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm); } /** * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo * * @vm: requested vm * @bo: requested buffer object * * Find @bo inside the requested vm (cayman+). * Search inside the @bos vm list for the requested vm * Returns the found bo_va or NULL if none is found * * Object has to be reserved! */ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, struct amdgpu_bo *bo) { struct amdgpu_bo_va *bo_va; list_for_each_entry(bo_va, &bo->va, bo_list) { if (bo_va->vm == vm) { return bo_va; } } return NULL; } /** * amdgpu_vm_update_pages - helper to call the right asic function * * @adev: amdgpu_device pointer * @ib: indirect buffer to fill with commands * @pe: addr of the page entry * @addr: dst addr to write into pe * @count: number of page entries to update * @incr: increase next addr by incr bytes * @flags: hw access flags * @gtt_flags: GTT hw access flags * * Traces the parameters and calls the right asic functions * to setup the page table using the DMA. */ static void amdgpu_vm_update_pages(struct amdgpu_device *adev, struct amdgpu_ib *ib, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags, uint32_t gtt_flags) { trace_amdgpu_vm_set_page(pe, addr, count, incr, flags); if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) { uint64_t src = adev->gart.table_addr + (addr >> 12) * 8; amdgpu_vm_copy_pte(adev, ib, pe, src, count); } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) { amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags); } else { amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags); } } int amdgpu_vm_free_job(struct amdgpu_job *job) { int i; for (i = 0; i < job->num_ibs; i++) amdgpu_ib_free(job->adev, &job->ibs[i]); kfree(job->ibs); return 0; } /** * amdgpu_vm_clear_bo - initially clear the page dir/table * * @adev: amdgpu_device pointer * @bo: bo to clear * * need to reserve bo first before calling it. */ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, struct amdgpu_bo *bo) { struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; struct fence *fence = NULL; struct amdgpu_ib *ib; unsigned entries; uint64_t addr; int r; r = reservation_object_reserve_shared(bo->tbo.resv); if (r) return r; r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); if (r) goto error; addr = amdgpu_bo_gpu_offset(bo); entries = amdgpu_bo_size(bo) / 8; ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); if (!ib) goto error; r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); if (r) goto error_free; ib->length_dw = 0; amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0); amdgpu_vm_pad_ib(adev, ib); WARN_ON(ib->length_dw > 64); r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, &amdgpu_vm_free_job, AMDGPU_FENCE_OWNER_VM, &fence); if (!r) amdgpu_bo_fence(bo, fence, true); fence_put(fence); if (amdgpu_enable_scheduler) return 0; error_free: amdgpu_ib_free(adev, ib); kfree(ib); error: return r; } /** * amdgpu_vm_map_gart - get the physical address of a gart page * * @adev: amdgpu_device pointer * @addr: the unmapped addr * * Look up the physical address of the page that the pte resolves * to (cayman+). * Returns the physical address of the page. */ uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr) { uint64_t result; /* page table offset */ result = adev->gart.pages_addr[addr >> PAGE_SHIFT]; /* in case cpu page size != gpu page size*/ result |= addr & (~PAGE_MASK); return result; } /** * amdgpu_vm_update_pdes - make sure that page directory is valid * * @adev: amdgpu_device pointer * @vm: requested vm * @start: start of GPU address range * @end: end of GPU address range * * Allocates new page tables if necessary * and updates the page directory (cayman+). * Returns 0 for success, error for failure. * * Global and local mutex must be locked! */ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, struct amdgpu_vm *vm) { struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring; struct amdgpu_bo *pd = vm->page_directory; uint64_t pd_addr = amdgpu_bo_gpu_offset(pd); uint32_t incr = AMDGPU_VM_PTE_COUNT * 8; uint64_t last_pde = ~0, last_pt = ~0; unsigned count = 0, pt_idx, ndw; struct amdgpu_ib *ib; struct fence *fence = NULL; int r; /* padding, etc. */ ndw = 64; /* assume the worst case */ ndw += vm->max_pde_used * 6; /* update too big for an IB */ if (ndw > 0xfffff) return -ENOMEM; ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); if (!ib) return -ENOMEM; r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); if (r) { kfree(ib); return r; } ib->length_dw = 0; /* walk over the address space and update the page directory */ for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) { struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo; uint64_t pde, pt; if (bo == NULL) continue; pt = amdgpu_bo_gpu_offset(bo); if (vm->page_tables[pt_idx].addr == pt) continue; vm->page_tables[pt_idx].addr = pt; pde = pd_addr + pt_idx * 8; if (((last_pde + 8 * count) != pde) || ((last_pt + incr * count) != pt)) { if (count) { amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID, 0); } count = 1; last_pde = pde; last_pt = pt; } else { ++count; } } if (count) amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count, incr, AMDGPU_PTE_VALID, 0); if (ib->length_dw != 0) { amdgpu_vm_pad_ib(adev, ib); amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM); WARN_ON(ib->length_dw > ndw);