/* * Derived from "arch/i386/kernel/process.c" * Copyright (C) 1995 Linus Torvalds * * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and * Paul Mackerras (paulus@cs.anu.edu.au) * * PowerPC version * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #include <linux/errno.h>#include <linux/sched.h>#include <linux/kernel.h>#include <linux/mm.h>#include <linux/smp.h>#include <linux/stddef.h>#include <linux/unistd.h>#include <linux/ptrace.h>#include <linux/slab.h>#include <linux/user.h>#include <linux/elf.h>#include <linux/prctl.h>#include <linux/init_task.h>#include <linux/export.h>#include <linux/kallsyms.h>#include <linux/mqueue.h>#include <linux/hardirq.h>#include <linux/utsname.h>#include <linux/ftrace.h>#include <linux/kernel_stat.h>#include <linux/personality.h>#include <linux/random.h>#include <linux/hw_breakpoint.h>#include <linux/uaccess.h> #include <asm/pgtable.h>#include <asm/io.h>#include <asm/processor.h>#include <asm/mmu.h>#include <asm/prom.h>#include <asm/machdep.h>#include <asm/time.h>#include <asm/runlatch.h>#include <asm/syscalls.h>#include <asm/switch_to.h>#include <asm/tm.h>#include <asm/debug.h>#ifdef CONFIG_PPC64#include <asm/firmware.h>#endif#include <asm/code-patching.h>#include <linux/kprobes.h>#include <linux/kdebug.h> /* Transactional Memory debug */#ifdef TM_DEBUG_SW#define TM_DEBUG(x...) printk(KERN_INFO x)#else#define TM_DEBUG(x...) do { } while(0)#endif extern unsigned long _get_SP(void); #ifdef CONFIG_PPC_TRANSACTIONAL_MEMstatic void check_if_tm_restore_required(struct task_struct *tsk){ /* * If we are saving the current thread's registers, and the * thread is in a transactional state, set the TIF_RESTORE_TM * bit so that we know to restore the registers before * returning to userspace. */ if (tsk == current && tsk->thread.regs && MSR_TM_ACTIVE(tsk->thread.regs->msr) && !test_thread_flag(TIF_RESTORE_TM)) { tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; set_thread_flag(TIF_RESTORE_TM); }}#elsestatic inline void check_if_tm_restore_required(struct task_struct *tsk) { }#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ bool strict_msr_control;EXPORT_SYMBOL(strict_msr_control); static int __init enable_strict_msr_control(char *str){ strict_msr_control = true; pr_info("Enabling strict facility control\n"); return 0;}early_param("ppc_strict_facility_enable", enable_strict_msr_control); void msr_check_and_set(unsigned long bits){ unsigned long oldmsr = mfmsr(); unsigned long newmsr; newmsr = oldmsr | bits; #ifdef CONFIG_VSX if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) newmsr |= MSR_VSX;#endif if (oldmsr != newmsr) mtmsr_isync(newmsr);} void __msr_check_and_clear(unsigned long bits){ unsigned long oldmsr = mfmsr(); unsigned long newmsr; newmsr = oldmsr & ~bits; #ifdef CONFIG_VSX if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) newmsr &= ~MSR_VSX;#endif if (oldmsr != newmsr) mtmsr_isync(newmsr);}EXPORT_SYMBOL(__msr_check_and_clear); #ifdef CONFIG_PPC_FPUvoid giveup_fpu(struct task_struct *tsk){ check_if_tm_restore_required(tsk); msr_check_and_set(MSR_FP); __giveup_fpu(tsk); msr_check_and_clear(MSR_FP);}EXPORT_SYMBOL(giveup_fpu); /* * Make sure the floating-point register state in the * the thread_struct is up to date for task tsk. */void flush_fp_to_thread(struct task_struct *tsk){ if (tsk->thread.regs) { /* * We need to disable preemption here because if we didn't, * another process could get scheduled after the regs->msr * test but before we have finished saving the FP registers * to the thread_struct. That process could take over the * FPU, and then when we get scheduled again we would store * bogus values for the remaining FP registers. */ preempt_disable(); if (tsk->thread.regs->msr & MSR_FP) { /* * This should only ever be called for current or * for a stopped child process. Since we save away * the FP register state on context switch, * there is something wrong if a stopped child appears * to still have its FP state in the CPU registers. */ BUG_ON(tsk != current); giveup_fpu(tsk); } preempt_enable(); }}EXPORT_SYMBOL_GPL(flush_fp_to_thread); void enable_kernel_fp(void){ WARN_ON(preemptible()); msr_check_and_set(MSR_FP); if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { check_if_tm_restore_required(current); __giveup_fpu(current); }}EXPORT_SYMBOL(enable_kernel_fp);#endif /* CONFIG_PPC_FPU */ #ifdef CONFIG_ALTIVECvoid giveup_altivec(struct task_struct *tsk){ check_if_tm_restore_required(tsk); msr_check_and_set(MSR_VEC); __giveup_altivec(tsk); msr_check_and_clear(MSR_VEC);}EXPORT_SYMBOL(giveup_altivec); void enable_kernel_altivec(void){ WARN_ON(preemptible()); msr_check_and_set(MSR_VEC); if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { check_if_tm_restore_required(current); __giveup_altivec(current); }}EXPORT_SYMBOL(enable_kernel_altivec); /* * Make sure the VMX/Altivec register state in the * the thread_struct is up to date for task tsk. */void flush_altivec_to_thread(struct task_struct *tsk){ if (tsk->thread.regs) { preempt_disable(); if (tsk->thread.regs->msr & MSR_VEC) { BUG_ON(tsk != current); giveup_altivec(tsk); } preempt_enable(); }}EXPORT_SYMBOL_GPL(flush_altivec_to_thread);#endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_VSXvoid giveup_vsx(struct task_struct *tsk){ check_if_tm_restore_required(tsk); msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); if (tsk->thread.regs->msr & MSR_FP) __giveup_fpu(tsk); if (tsk->thread.regs->msr & MSR_VEC) __giveup_altivec(tsk); __giveup_vsx(tsk); msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);}EXPORT_SYMBOL(giveup_vsx); void enable_kernel_vsx(void){ WARN_ON(preemptible()); msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { check_if_tm_restore_required(current); if (current->thread.regs->msr & MSR_FP) __giveup_fpu(current); if (current->thread.regs->msr & MSR_VEC) __giveup_altivec(current); __giveup_vsx(current); }}EXPORT_SYMBOL(enable_kernel_vsx); void flush_vsx_to_thread(struct task_struct *tsk){ if (tsk->thread.regs) { preempt_disable(); if (tsk->thread.regs->msr & MSR_VSX) { BUG_ON(tsk != current); giveup_vsx(tsk); } preempt_enable(); }}EXPORT_SYMBOL_GPL(flush_vsx_to_thread);#endif /* CONFIG_VSX */ #ifdef CONFIG_SPEvoid giveup_spe(struct task_struct *tsk){ check_if_tm_restore_required(tsk); msr_check_and_set(MSR_SPE); __giveup_spe(tsk); msr_check_and_clear(MSR_SPE);}EXPORT_SYMBOL(giveup_spe); void enable_kernel_spe(void){ WARN_ON(preemptible()); msr_check_and_set(MSR_SPE); if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { check_if_tm_restore_required(current); __giveup_spe(current); }}EXPORT_SYMBOL(enable_kernel_spe); void flush_spe_to_thread(struct task_struct *tsk){ if (tsk->thread.regs) { preempt_disable(); if (tsk->thread.regs->msr & MSR_SPE) { BUG_ON(tsk != current); tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); giveup_spe(tsk); } preempt_enable(); }}#endif /* CONFIG_SPE */ static unsigned long msr_all_available; static int __init init_msr_all_available(void){#ifdef CONFIG_PPC_FPU msr_all_available |= MSR_FP;#endif#ifdef CONFIG_ALTIVEC if (cpu_has_feature(CPU_FTR_ALTIVEC)) msr_all_available |= MSR_VEC;#endif#ifdef CONFIG_VSX if (cpu_has_feature(CPU_FTR_VSX)) msr_all_available |= MSR_VSX;#endif#ifdef CONFIG_SPE if (cpu_has_feature(CPU_FTR_SPE)) msr_all_available |= MSR_SPE;#endif return 0;}early_initcall(init_msr_all_available); void giveup_all(struct task_struct *tsk){ unsigned long usermsr; if (!tsk->thread.regs) return; usermsr = tsk->thread.regs->msr; if ((usermsr & msr_all_available) == 0) return; msr_check_and_set(msr_all_available); #ifdef CONFIG_PPC_FPU if (usermsr & MSR_FP) __giveup_fpu(tsk);#endif#ifdef CONFIG_ALTIVEC if (usermsr & MSR_VEC) __giveup_altivec(tsk);#endif#ifdef CONFIG_VSX if (usermsr & MSR_VSX) __giveup_vsx(tsk);#endif#ifdef CONFIG_SPE if (usermsr & MSR_SPE) __giveup_spe(tsk);#endif msr_check_and_clear(msr_all_available);}EXPORT_SYMBOL(giveup_all); void flush_all_to_thread(struct task_struct *tsk){ if (tsk->thread.regs) { preempt_disable(); BUG_ON(tsk != current); giveup_all(tsk); #ifdef CONFIG_SPE if (tsk->thread.regs->msr & MSR_SPE) tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);#endif preempt_enable(); }}EXPORT_SYMBOL(flush_all_to_thread); #ifdef CONFIG_PPC_ADV_DEBUG_REGSvoid do_send_trap(struct pt_regs *regs, unsigned long address, unsigned long error_code, int signal_code, int breakpt){ siginfo_t info; current->thread.trap_nr = signal_code; if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 11, SIGSEGV) == NOTIFY_STOP) return; /* Deliver the signal to userspace */ info.si_signo = SIGTRAP; info.si_errno = breakpt; /* breakpoint or watchpoint id */ info.si_code = signal_code; info.si_addr = (void __user *)address; force_sig_info(SIGTRAP, &info, current);}#else /* !CONFIG_PPC_ADV_DEBUG_REGS */void do_break (struct pt_regs *regs, unsigned long address, unsigned long error_code){ siginfo_t info; current->thread.trap_nr = TRAP_HWBKPT; if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 11, SIGSEGV) == NOTIFY_STOP) return; if (debugger_break_match(regs)) return; /* Clear the breakpoint */ hw_breakpoint_disable(); /* Deliver the signal to userspace */ info.si_signo = SIGTRAP; info.si_errno = 0; info.si_code = TRAP_HWBKPT; info.si_addr = (void __user *)address; force_sig_info(SIGTRAP, &info, current);}#endif /* CONFIG_PPC_ADV_DEBUG_REGS */ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); #ifdef CONFIG_PPC_ADV_DEBUG_REGS/* * Set the debug registers back to their default "safe" values. */static void set_debug_reg_defaults(struct thread_struct *thread){ thread->debug.iac1 = thread->debug.iac2 = 0;#if CONFIG_PPC_ADV_DEBUG_IACS > 2 thread->debug.iac3 = thread->debug.iac4 = 0;#endif thread->debug.dac1 = thread->debug.dac2 = 0;#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 thread->debug.dvc1 = thread->debug.dvc2 = 0;#endif thread->debug.dbcr0 = 0;#ifdef CONFIG_BOOKE /* * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) */ thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US | DBCR1_IAC4US; /* * Force Data Address Compare User/Supervisor bits to be User-only * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. */ thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;#else thread->debug.dbcr1 = 0;#endif} static void prime_debug_regs(struct debug_reg *debug){ /* * We could have inherited MSR_DE from userspace, since * it doesn't get cleared on exception entry. Make sure * MSR_DE is clear before we enable any debug events. */ mtmsr(mfmsr() & ~MSR_DE); mtspr(SPRN_IAC1, debug->iac1); mtspr(SPRN_IAC2, debug->iac2);#if CONFIG_PPC_ADV_DEBUG_IACS > 2 mtspr(SPRN_IAC3, debug->iac3); mtspr(SPRN_IAC4, debug->iac4);#endif mtspr(SPRN_DAC1, debug->dac1); mtspr(SPRN_DAC2, debug->dac2);#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 mtspr(SPRN_DVC1, debug->dvc1); mtspr(SPRN_DVC2, debug->dvc2);#endif mtspr(SPRN_DBCR0, debug->dbcr0); mtspr(SPRN_DBCR1, debug->dbcr1);#ifdef CONFIG_BOOKE mtspr(SPRN_DBCR2, debug->dbcr2);#endif}/* * Unless neither the old or new thread are making use of the * debug registers, set the debug registers from the valuesLines 1–500 of 1802. Load more
/* * Derived from "arch/i386/kernel/process.c" * Copyright (C) 1995 Linus Torvalds * * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and * Paul Mackerras (paulus@cs.anu.edu.au) * * PowerPC version * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #include <linux/errno.h> #include <linux/sched.h> #include <linux/kernel.h> #include <linux/mm.h> #include <linux/smp.h> #include <linux/stddef.h> #include <linux/unistd.h> #include <linux/ptrace.h> #include <linux/slab.h> #include <linux/user.h> #include <linux/elf.h> #include <linux/prctl.h> #include <linux/init_task.h> #include <linux/export.h> #include <linux/kallsyms.h> #include <linux/mqueue.h> #include <linux/hardirq.h> #include <linux/utsname.h> #include <linux/ftrace.h> #include <linux/kernel_stat.h> #include <linux/personality.h> #include <linux/random.h> #include <linux/hw_breakpoint.h> #include <linux/uaccess.h> #include <asm/pgtable.h> #include <asm/io.h> #include <asm/processor.h> #include <asm/mmu.h> #include <asm/prom.h> #include <asm/machdep.h> #include <asm/time.h> #include <asm/runlatch.h> #include <asm/syscalls.h> #include <asm/switch_to.h> #include <asm/tm.h> #include <asm/debug.h> #ifdef CONFIG_PPC64 #include <asm/firmware.h> #endif #include <asm/code-patching.h> #include <linux/kprobes.h> #include <linux/kdebug.h> /* Transactional Memory debug */ #ifdef TM_DEBUG_SW #define TM_DEBUG(x...) printk(KERN_INFO x) #else #define TM_DEBUG(x...) do { } while(0) #endif extern unsigned long _get_SP(void); #ifdef CONFIG_PPC_TRANSACTIONAL_MEM static void check_if_tm_restore_required(struct task_struct *tsk) { /* * If we are saving the current thread's registers, and the * thread is in a transactional state, set the TIF_RESTORE_TM * bit so that we know to restore the registers before * returning to userspace. */ if (tsk == current && tsk->thread.regs && MSR_TM_ACTIVE(tsk->thread.regs->msr) && !test_thread_flag(TIF_RESTORE_TM)) { tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; set_thread_flag(TIF_RESTORE_TM); } } #else static inline void check_if_tm_restore_required(struct task_struct *tsk) { } #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ bool strict_msr_control; EXPORT_SYMBOL(strict_msr_control); static int __init enable_strict_msr_control(char *str) { strict_msr_control = true; pr_info("Enabling strict facility control\n"); return 0; } early_param("ppc_strict_facility_enable", enable_strict_msr_control); void msr_check_and_set(unsigned long bits) { unsigned long oldmsr = mfmsr(); unsigned long newmsr; newmsr = oldmsr | bits; #ifdef CONFIG_VSX if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) newmsr |= MSR_VSX; #endif if (oldmsr != newmsr) mtmsr_isync(newmsr); } void __msr_check_and_clear(unsigned long bits) { unsigned long oldmsr = mfmsr(); unsigned long newmsr; newmsr = oldmsr & ~bits; #ifdef CONFIG_VSX if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) newmsr &= ~MSR_VSX; #endif if (oldmsr != newmsr) mtmsr_isync(newmsr); } EXPORT_SYMBOL(__msr_check_and_clear); #ifdef CONFIG_PPC_FPU void giveup_fpu(struct task_struct *tsk) { check_if_tm_restore_required(tsk); msr_check_and_set(MSR_FP); __giveup_fpu(tsk); msr_check_and_clear(MSR_FP); } EXPORT_SYMBOL(giveup_fpu); /* * Make sure the floating-point register state in the * the thread_struct is up to date for task tsk. */ void flush_fp_to_thread(struct task_struct *tsk) { if (tsk->thread.regs) { /* * We need to disable preemption here because if we didn't, * another process could get scheduled after the regs->msr * test but before we have finished saving the FP registers * to the thread_struct. That process could take over the * FPU, and then when we get scheduled again we would store * bogus values for the remaining FP registers. */ preempt_disable(); if (tsk->thread.regs->msr & MSR_FP) { /* * This should only ever be called for current or * for a stopped child process. Since we save away * the FP register state on context switch, * there is something wrong if a stopped child appears * to still have its FP state in the CPU registers. */ BUG_ON(tsk != current); giveup_fpu(tsk); } preempt_enable(); } } EXPORT_SYMBOL_GPL(flush_fp_to_thread); void enable_kernel_fp(void) { WARN_ON(preemptible()); msr_check_and_set(MSR_FP); if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { check_if_tm_restore_required(current); __giveup_fpu(current); } } EXPORT_SYMBOL(enable_kernel_fp); #endif /* CONFIG_PPC_FPU */ #ifdef CONFIG_ALTIVEC void giveup_altivec(struct task_struct *tsk) { check_if_tm_restore_required(tsk); msr_check_and_set(MSR_VEC); __giveup_altivec(tsk); msr_check_and_clear(MSR_VEC); } EXPORT_SYMBOL(giveup_altivec); void enable_kernel_altivec(void) { WARN_ON(preemptible()); msr_check_and_set(MSR_VEC); if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { check_if_tm_restore_required(current); __giveup_altivec(current); } } EXPORT_SYMBOL(enable_kernel_altivec); /* * Make sure the VMX/Altivec register state in the * the thread_struct is up to date for task tsk. */ void flush_altivec_to_thread(struct task_struct *tsk) { if (tsk->thread.regs) { preempt_disable(); if (tsk->thread.regs->msr & MSR_VEC) { BUG_ON(tsk != current); giveup_altivec(tsk); } preempt_enable(); } } EXPORT_SYMBOL_GPL(flush_altivec_to_thread); #endif /* CONFIG_ALTIVEC */ #ifdef CONFIG_VSX void giveup_vsx(struct task_struct *tsk) { check_if_tm_restore_required(tsk); msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); if (tsk->thread.regs->msr & MSR_FP) __giveup_fpu(tsk); if (tsk->thread.regs->msr & MSR_VEC) __giveup_altivec(tsk); __giveup_vsx(tsk); msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); } EXPORT_SYMBOL(giveup_vsx); void enable_kernel_vsx(void) { WARN_ON(preemptible()); msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { check_if_tm_restore_required(current); if (current->thread.regs->msr & MSR_FP) __giveup_fpu(current); if (current->thread.regs->msr & MSR_VEC) __giveup_altivec(current); __giveup_vsx(current); } } EXPORT_SYMBOL(enable_kernel_vsx); void flush_vsx_to_thread(struct task_struct *tsk) { if (tsk->thread.regs) { preempt_disable(); if (tsk->thread.regs->msr & MSR_VSX) { BUG_ON(tsk != current); giveup_vsx(tsk); } preempt_enable(); } } EXPORT_SYMBOL_GPL(flush_vsx_to_thread); #endif /* CONFIG_VSX */ #ifdef CONFIG_SPE void giveup_spe(struct task_struct *tsk) { check_if_tm_restore_required(tsk); msr_check_and_set(MSR_SPE); __giveup_spe(tsk); msr_check_and_clear(MSR_SPE); } EXPORT_SYMBOL(giveup_spe); void enable_kernel_spe(void) { WARN_ON(preemptible()); msr_check_and_set(MSR_SPE); if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { check_if_tm_restore_required(current); __giveup_spe(current); } } EXPORT_SYMBOL(enable_kernel_spe); void flush_spe_to_thread(struct task_struct *tsk) { if (tsk->thread.regs) { preempt_disable(); if (tsk->thread.regs->msr & MSR_SPE) { BUG_ON(tsk != current); tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); giveup_spe(tsk); } preempt_enable(); } } #endif /* CONFIG_SPE */ static unsigned long msr_all_available; static int __init init_msr_all_available(void) { #ifdef CONFIG_PPC_FPU msr_all_available |= MSR_FP; #endif #ifdef CONFIG_ALTIVEC if (cpu_has_feature(CPU_FTR_ALTIVEC)) msr_all_available |= MSR_VEC; #endif #ifdef CONFIG_VSX if (cpu_has_feature(CPU_FTR_VSX)) msr_all_available |= MSR_VSX; #endif #ifdef CONFIG_SPE if (cpu_has_feature(CPU_FTR_SPE)) msr_all_available |= MSR_SPE; #endif return 0; } early_initcall(init_msr_all_available); void giveup_all(struct task_struct *tsk) { unsigned long usermsr; if (!tsk->thread.regs) return; usermsr = tsk->thread.regs->msr; if ((usermsr & msr_all_available) == 0) return; msr_check_and_set(msr_all_available); #ifdef CONFIG_PPC_FPU if (usermsr & MSR_FP) __giveup_fpu(tsk); #endif #ifdef CONFIG_ALTIVEC if (usermsr & MSR_VEC) __giveup_altivec(tsk); #endif #ifdef CONFIG_VSX if (usermsr & MSR_VSX) __giveup_vsx(tsk); #endif #ifdef CONFIG_SPE if (usermsr & MSR_SPE) __giveup_spe(tsk); #endif msr_check_and_clear(msr_all_available); } EXPORT_SYMBOL(giveup_all); void flush_all_to_thread(struct task_struct *tsk) { if (tsk->thread.regs) { preempt_disable(); BUG_ON(tsk != current); giveup_all(tsk); #ifdef CONFIG_SPE if (tsk->thread.regs->msr & MSR_SPE) tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); #endif preempt_enable(); } } EXPORT_SYMBOL(flush_all_to_thread); #ifdef CONFIG_PPC_ADV_DEBUG_REGS void do_send_trap(struct pt_regs *regs, unsigned long address, unsigned long error_code, int signal_code, int breakpt) { siginfo_t info; current->thread.trap_nr = signal_code; if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 11, SIGSEGV) == NOTIFY_STOP) return; /* Deliver the signal to userspace */ info.si_signo = SIGTRAP; info.si_errno = breakpt; /* breakpoint or watchpoint id */ info.si_code = signal_code; info.si_addr = (void __user *)address; force_sig_info(SIGTRAP, &info, current); } #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ void do_break (struct pt_regs *regs, unsigned long address, unsigned long error_code) { siginfo_t info; current->thread.trap_nr = TRAP_HWBKPT; if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, 11, SIGSEGV) == NOTIFY_STOP) return; if (debugger_break_match(regs)) return; /* Clear the breakpoint */ hw_breakpoint_disable(); /* Deliver the signal to userspace */ info.si_signo = SIGTRAP; info.si_errno = 0; info.si_code = TRAP_HWBKPT; info.si_addr = (void __user *)address; force_sig_info(SIGTRAP, &info, current); } #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); #ifdef CONFIG_PPC_ADV_DEBUG_REGS /* * Set the debug registers back to their default "safe" values. */ static void set_debug_reg_defaults(struct thread_struct *thread) { thread->debug.iac1 = thread->debug.iac2 = 0; #if CONFIG_PPC_ADV_DEBUG_IACS > 2 thread->debug.iac3 = thread->debug.iac4 = 0; #endif thread->debug.dac1 = thread->debug.dac2 = 0; #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 thread->debug.dvc1 = thread->debug.dvc2 = 0; #endif thread->debug.dbcr0 = 0; #ifdef CONFIG_BOOKE /* * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) */ thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | DBCR1_IAC3US | DBCR1_IAC4US; /* * Force Data Address Compare User/Supervisor bits to be User-only * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. */ thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; #else thread->debug.dbcr1 = 0; #endif } static void prime_debug_regs(struct debug_reg *debug) { /* * We could have inherited MSR_DE from userspace, since * it doesn't get cleared on exception entry. Make sure * MSR_DE is clear before we enable any debug events. */ mtmsr(mfmsr() & ~MSR_DE); mtspr(SPRN_IAC1, debug->iac1); mtspr(SPRN_IAC2, debug->iac2); #if CONFIG_PPC_ADV_DEBUG_IACS > 2 mtspr(SPRN_IAC3, debug->iac3); mtspr(SPRN_IAC4, debug->iac4); #endif mtspr(SPRN_DAC1, debug->dac1); mtspr(SPRN_DAC2, debug->dac2); #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 mtspr(SPRN_DVC1, debug->dvc1); mtspr(SPRN_DVC2, debug->dvc2); #endif mtspr(SPRN_DBCR0, debug->dbcr0); mtspr(SPRN_DBCR1, debug->dbcr1); #ifdef CONFIG_BOOKE mtspr(SPRN_DBCR2, debug->dbcr2); #endif } /* * Unless neither the old or new thread are making use of the * debug registers, set the debug registers from the values