#include <linux/delay.h>#include <linux/dmaengine.h>#include <linux/dma-mapping.h>#include <linux/platform_device.h>#include <linux/module.h>#include <linux/of.h>#include <linux/slab.h>#include <linux/of_dma.h>#include <linux/of_irq.h>#include <linux/dmapool.h>#include <linux/interrupt.h>#include <linux/of_address.h>#include <linux/pm_runtime.h>#include "dmaengine.h" #define DESC_TYPE 27#define DESC_TYPE_HOST 0x10#define DESC_TYPE_TEARD 0x13 #define TD_DESC_IS_RX (1 << 16)#define TD_DESC_DMA_NUM 10 #define DESC_LENGTH_BITS_NUM 21 #define DESC_TYPE_USB (5 << 26)#define DESC_PD_COMPLETE (1 << 31) /* DMA engine */#define DMA_TDFDQ 4#define DMA_TXGCR(x) (0x800 + (x) * 0x20)#define DMA_RXGCR(x) (0x808 + (x) * 0x20)#define RXHPCRA0 4 #define GCR_CHAN_ENABLE (1 << 31)#define GCR_TEARDOWN (1 << 30)#define GCR_STARV_RETRY (1 << 24)#define GCR_DESC_TYPE_HOST (1 << 14) /* DMA scheduler */#define DMA_SCHED_CTRL 0#define DMA_SCHED_CTRL_EN (1 << 31)#define DMA_SCHED_WORD(x) ((x) * 4 + 0x800) #define SCHED_ENTRY0_CHAN(x) ((x) << 0)#define SCHED_ENTRY0_IS_RX (1 << 7) #define SCHED_ENTRY1_CHAN(x) ((x) << 8)#define SCHED_ENTRY1_IS_RX (1 << 15) #define SCHED_ENTRY2_CHAN(x) ((x) << 16)#define SCHED_ENTRY2_IS_RX (1 << 23) #define SCHED_ENTRY3_CHAN(x) ((x) << 24)#define SCHED_ENTRY3_IS_RX (1 << 31) /* Queue manager *//* 4 KiB of memory for descriptors, 2 for each endpoint */#define ALLOC_DECS_NUM 128#define DESCS_AREAS 1#define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS)#define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4) #define QMGR_LRAM0_BASE 0x80#define QMGR_LRAM_SIZE 0x84#define QMGR_LRAM1_BASE 0x88#define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10)#define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10)#define QMGR_MEMCTRL_IDX_SH 16#define QMGR_MEMCTRL_DESC_SH 8 #define QMGR_NUM_PEND 5#define QMGR_PEND(x) (0x90 + (x) * 4) #define QMGR_PENDING_SLOT_Q(x) (x / 32)#define QMGR_PENDING_BIT_Q(x) (x % 32) #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)#define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)#define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)#define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10) /* Glue layer specific *//* USBSS / USB AM335x */#define USBSS_IRQ_STATUS 0x28#define USBSS_IRQ_ENABLER 0x2c#define USBSS_IRQ_CLEARR 0x30 #define USBSS_IRQ_PD_COMP (1 << 2) /* Packet Descriptor */#define PD2_ZERO_LENGTH (1 << 19) struct cppi41_channel { struct dma_chan chan; struct dma_async_tx_descriptor txd; struct cppi41_dd *cdd; struct cppi41_desc *desc; dma_addr_t desc_phys; void __iomem *gcr_reg; int is_tx; u32 residue; unsigned int q_num; unsigned int q_comp_num; unsigned int port_num; unsigned td_retry; unsigned td_queued:1; unsigned td_seen:1; unsigned td_desc_seen:1; struct list_head node; /* Node for pending list */}; struct cppi41_desc { u32 pd0; u32 pd1; u32 pd2; u32 pd3; u32 pd4; u32 pd5; u32 pd6; u32 pd7;} __aligned(32); struct chan_queues { u16 submit; u16 complete;}; struct cppi41_dd { struct dma_device ddev; void *qmgr_scratch; dma_addr_t scratch_phys; struct cppi41_desc *cd; dma_addr_t descs_phys; u32 first_td_desc; struct cppi41_channel *chan_busy[ALLOC_DECS_NUM]; void __iomem *usbss_mem; void __iomem *ctrl_mem; void __iomem *sched_mem; void __iomem *qmgr_mem; unsigned int irq; const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; struct list_head pending; /* Pending queued transfers */ spinlock_t lock; /* Lock for pending list */ /* context for suspend/resume */ unsigned int dma_tdfdq;}; #define FIST_COMPLETION_QUEUE 93static struct chan_queues usb_queues_tx[] = { /* USB0 ENDP 1 */ [ 0] = { .submit = 32, .complete = 93}, [ 1] = { .submit = 34, .complete = 94}, [ 2] = { .submit = 36, .complete = 95}, [ 3] = { .submit = 38, .complete = 96}, [ 4] = { .submit = 40, .complete = 97}, [ 5] = { .submit = 42, .complete = 98}, [ 6] = { .submit = 44, .complete = 99}, [ 7] = { .submit = 46, .complete = 100}, [ 8] = { .submit = 48, .complete = 101}, [ 9] = { .submit = 50, .complete = 102}, [10] = { .submit = 52, .complete = 103}, [11] = { .submit = 54, .complete = 104}, [12] = { .submit = 56, .complete = 105}, [13] = { .submit = 58, .complete = 106}, [14] = { .submit = 60, .complete = 107}, /* USB1 ENDP1 */ [15] = { .submit = 62, .complete = 125}, [16] = { .submit = 64, .complete = 126}, [17] = { .submit = 66, .complete = 127}, [18] = { .submit = 68, .complete = 128}, [19] = { .submit = 70, .complete = 129}, [20] = { .submit = 72, .complete = 130}, [21] = { .submit = 74, .complete = 131}, [22] = { .submit = 76, .complete = 132}, [23] = { .submit = 78, .complete = 133}, [24] = { .submit = 80, .complete = 134}, [25] = { .submit = 82, .complete = 135}, [26] = { .submit = 84, .complete = 136}, [27] = { .submit = 86, .complete = 137}, [28] = { .submit = 88, .complete = 138}, [29] = { .submit = 90, .complete = 139},}; static const struct chan_queues usb_queues_rx[] = { /* USB0 ENDP 1 */ [ 0] = { .submit = 1, .complete = 109}, [ 1] = { .submit = 2, .complete = 110}, [ 2] = { .submit = 3, .complete = 111}, [ 3] = { .submit = 4, .complete = 112}, [ 4] = { .submit = 5, .complete = 113}, [ 5] = { .submit = 6, .complete = 114}, [ 6] = { .submit = 7, .complete = 115}, [ 7] = { .submit = 8, .complete = 116}, [ 8] = { .submit = 9, .complete = 117}, [ 9] = { .submit = 10, .complete = 118}, [10] = { .submit = 11, .complete = 119}, [11] = { .submit = 12, .complete = 120}, [12] = { .submit = 13, .complete = 121}, [13] = { .submit = 14, .complete = 122}, [14] = { .submit = 15, .complete = 123}, /* USB1 ENDP 1 */ [15] = { .submit = 16, .complete = 141}, [16] = { .submit = 17, .complete = 142}, [17] = { .submit = 18, .complete = 143}, [18] = { .submit = 19, .complete = 144}, [19] = { .submit = 20, .complete = 145}, [20] = { .submit = 21, .complete = 146}, [21] = { .submit = 22, .complete = 147}, [22] = { .submit = 23, .complete = 148}, [23] = { .submit = 24, .complete = 149}, [24] = { .submit = 25, .complete = 150}, [25] = { .submit = 26, .complete = 151}, [26] = { .submit = 27, .complete = 152}, [27] = { .submit = 28, .complete = 153}, [28] = { .submit = 29, .complete = 154}, [29] = { .submit = 30, .complete = 155},}; struct cppi_glue_infos { irqreturn_t (*isr)(int irq, void *data); const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue;}; static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c){ return container_of(c, struct cppi41_channel, chan);} static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc){ struct cppi41_channel *c; u32 descs_size; u32 desc_num; descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM; if (!((desc >= cdd->descs_phys) && (desc < (cdd->descs_phys + descs_size)))) { return NULL; } desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc); BUG_ON(desc_num >= ALLOC_DECS_NUM); c = cdd->chan_busy[desc_num]; cdd->chan_busy[desc_num] = NULL; return c;} static void cppi_writel(u32 val, void *__iomem *mem){ __raw_writel(val, mem);} static u32 cppi_readl(void *__iomem *mem){ return __raw_readl(mem);} static u32 pd_trans_len(u32 val){ return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);} static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num){ u32 desc; desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num)); desc &= ~0x1f; return desc;} static irqreturn_t cppi41_irq(int irq, void *data){ struct cppi41_dd *cdd = data; struct cppi41_channel *c; u32 status; int i; status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS); if (!(status & USBSS_IRQ_PD_COMP)) return IRQ_NONE; cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS); for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND; i++) { u32 val; u32 q_num; val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i)); if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) { u32 mask; /* set corresponding bit for completetion Q 93 */ mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE); /* not set all bits for queues less than Q 93 */ mask--; /* now invert and keep only Q 93+ set */ val &= ~mask; } if (val) __iormb(); while (val) { u32 desc, len; int error; error = pm_runtime_get(cdd->ddev.dev); if (error < 0) dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n", __func__, error); q_num = __fls(val); val &= ~(1 << q_num); q_num += 32 * i; desc = cppi41_pop_desc(cdd, q_num); c = desc_to_chan(cdd, desc); if (WARN_ON(!c)) { pr_err("%s() q %d desc %08x\n", __func__, q_num, desc); continue; } if (c->desc->pd2 & PD2_ZERO_LENGTH) len = 0; else len = pd_trans_len(c->desc->pd0); c->residue = pd_trans_len(c->desc->pd6) - len; dma_cookie_complete(&c->txd); dmaengine_desc_get_callback_invoke(&c->txd, NULL); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); } } return IRQ_HANDLED;} static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx){ dma_cookie_t cookie; cookie = dma_cookie_assign(tx); return cookie;} static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan){ struct cppi41_channel *c = to_cpp41_chan(chan); struct cppi41_dd *cdd = c->cdd; int error; error = pm_runtime_get_sync(cdd->ddev.dev); if (error < 0) { dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n", __func__, error); pm_runtime_put_noidle(cdd->ddev.dev); return error; } dma_cookie_init(chan); dma_async_tx_descriptor_init(&c->txd, chan); c->txd.tx_submit = cppi41_tx_submit; if (!c->is_tx) cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); return 0;} static void cppi41_dma_free_chan_resources(struct dma_chan *chan){ struct cppi41_channel *c = to_cpp41_chan(chan); struct cppi41_dd *cdd = c->cdd; int error; error = pm_runtime_get_sync(cdd->ddev.dev); if (error < 0) { pm_runtime_put_noidle(cdd->ddev.dev); return; } WARN_ON(!list_empty(&cdd->pending)); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev);} static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate){ struct cppi41_channel *c = to_cpp41_chan(chan); enum dma_status ret; /* lock */ ret = dma_cookie_status(chan, cookie, txstate); if (txstate && ret == DMA_COMPLETE) txstate->residue = c->residue; /* unlock */ return ret;} static void push_desc_queue(struct cppi41_channel *c){ struct cppi41_dd *cdd = c->cdd; u32 desc_num; u32 desc_phys; u32 reg; c->residue = 0; reg = GCR_CHAN_ENABLE; if (!c->is_tx) { reg |= GCR_STARV_RETRY; reg |= GCR_DESC_TYPE_HOST; reg |= c->q_comp_num; } cppi_writel(reg, c->gcr_reg); /* * We don't use writel() but __raw_writel() so we have to make sure * that the DMA descriptor in coherent memory made to the main memory * before starting the dma engine. */ __iowmb(); desc_phys = lower_32_bits(c->desc_phys); desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc); WARN_ON(cdd->chan_busy[desc_num]); cdd->chan_busy[desc_num] = c; reg = (sizeof(struct cppi41_desc) - 24) / 4; reg |= desc_phys; cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));} static void pending_desc(struct cppi41_channel *c){ struct cppi41_dd *cdd = c->cdd; unsigned long flags; spin_lock_irqsave(&cdd->lock, flags); list_add_tail(&c->node, &cdd->pending); spin_unlock_irqrestore(&cdd->lock, flags);} static void cppi41_dma_issue_pending(struct dma_chan *chan){ struct cppi41_channel *c = to_cpp41_chan(chan); struct cppi41_dd *cdd = c->cdd; int error; error = pm_runtime_get(cdd->ddev.dev); if ((error != -EINPROGRESS) && error < 0) { pm_runtime_put_noidle(cdd->ddev.dev); dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n", error); return; } if (likely(pm_runtime_active(cdd->ddev.dev))) push_desc_queue(c); else pending_desc(c); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev);} static u32 get_host_pd0(u32 length){ u32 reg; reg = DESC_TYPE_HOST << DESC_TYPE; reg |= length; Lines 1–500 of 1194. Load more
#include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/module.h> #include <linux/of.h> #include <linux/slab.h> #include <linux/of_dma.h> #include <linux/of_irq.h> #include <linux/dmapool.h> #include <linux/interrupt.h> #include <linux/of_address.h> #include <linux/pm_runtime.h> #include "dmaengine.h" #define DESC_TYPE 27 #define DESC_TYPE_HOST 0x10 #define DESC_TYPE_TEARD 0x13 #define TD_DESC_IS_RX (1 << 16) #define TD_DESC_DMA_NUM 10 #define DESC_LENGTH_BITS_NUM 21 #define DESC_TYPE_USB (5 << 26) #define DESC_PD_COMPLETE (1 << 31) /* DMA engine */ #define DMA_TDFDQ 4 #define DMA_TXGCR(x) (0x800 + (x) * 0x20) #define DMA_RXGCR(x) (0x808 + (x) * 0x20) #define RXHPCRA0 4 #define GCR_CHAN_ENABLE (1 << 31) #define GCR_TEARDOWN (1 << 30) #define GCR_STARV_RETRY (1 << 24) #define GCR_DESC_TYPE_HOST (1 << 14) /* DMA scheduler */ #define DMA_SCHED_CTRL 0 #define DMA_SCHED_CTRL_EN (1 << 31) #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800) #define SCHED_ENTRY0_CHAN(x) ((x) << 0) #define SCHED_ENTRY0_IS_RX (1 << 7) #define SCHED_ENTRY1_CHAN(x) ((x) << 8) #define SCHED_ENTRY1_IS_RX (1 << 15) #define SCHED_ENTRY2_CHAN(x) ((x) << 16) #define SCHED_ENTRY2_IS_RX (1 << 23) #define SCHED_ENTRY3_CHAN(x) ((x) << 24) #define SCHED_ENTRY3_IS_RX (1 << 31) /* Queue manager */ /* 4 KiB of memory for descriptors, 2 for each endpoint */ #define ALLOC_DECS_NUM 128 #define DESCS_AREAS 1 #define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS) #define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4) #define QMGR_LRAM0_BASE 0x80 #define QMGR_LRAM_SIZE 0x84 #define QMGR_LRAM1_BASE 0x88 #define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10) #define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10) #define QMGR_MEMCTRL_IDX_SH 16 #define QMGR_MEMCTRL_DESC_SH 8 #define QMGR_NUM_PEND 5 #define QMGR_PEND(x) (0x90 + (x) * 4) #define QMGR_PENDING_SLOT_Q(x) (x / 32) #define QMGR_PENDING_BIT_Q(x) (x % 32) #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10) #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10) #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10) #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10) /* Glue layer specific */ /* USBSS / USB AM335x */ #define USBSS_IRQ_STATUS 0x28 #define USBSS_IRQ_ENABLER 0x2c #define USBSS_IRQ_CLEARR 0x30 #define USBSS_IRQ_PD_COMP (1 << 2) /* Packet Descriptor */ #define PD2_ZERO_LENGTH (1 << 19) struct cppi41_channel { struct dma_chan chan; struct dma_async_tx_descriptor txd; struct cppi41_dd *cdd; struct cppi41_desc *desc; dma_addr_t desc_phys; void __iomem *gcr_reg; int is_tx; u32 residue; unsigned int q_num; unsigned int q_comp_num; unsigned int port_num; unsigned td_retry; unsigned td_queued:1; unsigned td_seen:1; unsigned td_desc_seen:1; struct list_head node; /* Node for pending list */ }; struct cppi41_desc { u32 pd0; u32 pd1; u32 pd2; u32 pd3; u32 pd4; u32 pd5; u32 pd6; u32 pd7; } __aligned(32); struct chan_queues { u16 submit; u16 complete; }; struct cppi41_dd { struct dma_device ddev; void *qmgr_scratch; dma_addr_t scratch_phys; struct cppi41_desc *cd; dma_addr_t descs_phys; u32 first_td_desc; struct cppi41_channel *chan_busy[ALLOC_DECS_NUM]; void __iomem *usbss_mem; void __iomem *ctrl_mem; void __iomem *sched_mem; void __iomem *qmgr_mem; unsigned int irq; const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; struct list_head pending; /* Pending queued transfers */ spinlock_t lock; /* Lock for pending list */ /* context for suspend/resume */ unsigned int dma_tdfdq; }; #define FIST_COMPLETION_QUEUE 93 static struct chan_queues usb_queues_tx[] = { /* USB0 ENDP 1 */ [ 0] = { .submit = 32, .complete = 93}, [ 1] = { .submit = 34, .complete = 94}, [ 2] = { .submit = 36, .complete = 95}, [ 3] = { .submit = 38, .complete = 96}, [ 4] = { .submit = 40, .complete = 97}, [ 5] = { .submit = 42, .complete = 98}, [ 6] = { .submit = 44, .complete = 99}, [ 7] = { .submit = 46, .complete = 100}, [ 8] = { .submit = 48, .complete = 101}, [ 9] = { .submit = 50, .complete = 102}, [10] = { .submit = 52, .complete = 103}, [11] = { .submit = 54, .complete = 104}, [12] = { .submit = 56, .complete = 105}, [13] = { .submit = 58, .complete = 106}, [14] = { .submit = 60, .complete = 107}, /* USB1 ENDP1 */ [15] = { .submit = 62, .complete = 125}, [16] = { .submit = 64, .complete = 126}, [17] = { .submit = 66, .complete = 127}, [18] = { .submit = 68, .complete = 128}, [19] = { .submit = 70, .complete = 129}, [20] = { .submit = 72, .complete = 130}, [21] = { .submit = 74, .complete = 131}, [22] = { .submit = 76, .complete = 132}, [23] = { .submit = 78, .complete = 133}, [24] = { .submit = 80, .complete = 134}, [25] = { .submit = 82, .complete = 135}, [26] = { .submit = 84, .complete = 136}, [27] = { .submit = 86, .complete = 137}, [28] = { .submit = 88, .complete = 138}, [29] = { .submit = 90, .complete = 139}, }; static const struct chan_queues usb_queues_rx[] = { /* USB0 ENDP 1 */ [ 0] = { .submit = 1, .complete = 109}, [ 1] = { .submit = 2, .complete = 110}, [ 2] = { .submit = 3, .complete = 111}, [ 3] = { .submit = 4, .complete = 112}, [ 4] = { .submit = 5, .complete = 113}, [ 5] = { .submit = 6, .complete = 114}, [ 6] = { .submit = 7, .complete = 115}, [ 7] = { .submit = 8, .complete = 116}, [ 8] = { .submit = 9, .complete = 117}, [ 9] = { .submit = 10, .complete = 118}, [10] = { .submit = 11, .complete = 119}, [11] = { .submit = 12, .complete = 120}, [12] = { .submit = 13, .complete = 121}, [13] = { .submit = 14, .complete = 122}, [14] = { .submit = 15, .complete = 123}, /* USB1 ENDP 1 */ [15] = { .submit = 16, .complete = 141}, [16] = { .submit = 17, .complete = 142}, [17] = { .submit = 18, .complete = 143}, [18] = { .submit = 19, .complete = 144}, [19] = { .submit = 20, .complete = 145}, [20] = { .submit = 21, .complete = 146}, [21] = { .submit = 22, .complete = 147}, [22] = { .submit = 23, .complete = 148}, [23] = { .submit = 24, .complete = 149}, [24] = { .submit = 25, .complete = 150}, [25] = { .submit = 26, .complete = 151}, [26] = { .submit = 27, .complete = 152}, [27] = { .submit = 28, .complete = 153}, [28] = { .submit = 29, .complete = 154}, [29] = { .submit = 30, .complete = 155}, }; struct cppi_glue_infos { irqreturn_t (*isr)(int irq, void *data); const struct chan_queues *queues_rx; const struct chan_queues *queues_tx; struct chan_queues td_queue; }; static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c) { return container_of(c, struct cppi41_channel, chan); } static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc) { struct cppi41_channel *c; u32 descs_size; u32 desc_num; descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM; if (!((desc >= cdd->descs_phys) && (desc < (cdd->descs_phys + descs_size)))) { return NULL; } desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc); BUG_ON(desc_num >= ALLOC_DECS_NUM); c = cdd->chan_busy[desc_num]; cdd->chan_busy[desc_num] = NULL; return c; } static void cppi_writel(u32 val, void *__iomem *mem) { __raw_writel(val, mem); } static u32 cppi_readl(void *__iomem *mem) { return __raw_readl(mem); } static u32 pd_trans_len(u32 val) { return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1); } static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num) { u32 desc; desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num)); desc &= ~0x1f; return desc; } static irqreturn_t cppi41_irq(int irq, void *data) { struct cppi41_dd *cdd = data; struct cppi41_channel *c; u32 status; int i; status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS); if (!(status & USBSS_IRQ_PD_COMP)) return IRQ_NONE; cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS); for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND; i++) { u32 val; u32 q_num; val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i)); if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) { u32 mask; /* set corresponding bit for completetion Q 93 */ mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE); /* not set all bits for queues less than Q 93 */ mask--; /* now invert and keep only Q 93+ set */ val &= ~mask; } if (val) __iormb(); while (val) { u32 desc, len; int error; error = pm_runtime_get(cdd->ddev.dev); if (error < 0) dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n", __func__, error); q_num = __fls(val); val &= ~(1 << q_num); q_num += 32 * i; desc = cppi41_pop_desc(cdd, q_num); c = desc_to_chan(cdd, desc); if (WARN_ON(!c)) { pr_err("%s() q %d desc %08x\n", __func__, q_num, desc); continue; } if (c->desc->pd2 & PD2_ZERO_LENGTH) len = 0; else len = pd_trans_len(c->desc->pd0); c->residue = pd_trans_len(c->desc->pd6) - len; dma_cookie_complete(&c->txd); dmaengine_desc_get_callback_invoke(&c->txd, NULL); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); } } return IRQ_HANDLED; } static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx) { dma_cookie_t cookie; cookie = dma_cookie_assign(tx); return cookie; } static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan) { struct cppi41_channel *c = to_cpp41_chan(chan); struct cppi41_dd *cdd = c->cdd; int error; error = pm_runtime_get_sync(cdd->ddev.dev); if (error < 0) { dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n", __func__, error); pm_runtime_put_noidle(cdd->ddev.dev); return error; } dma_cookie_init(chan); dma_async_tx_descriptor_init(&c->txd, chan); c->txd.tx_submit = cppi41_tx_submit; if (!c->is_tx) cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); return 0; } static void cppi41_dma_free_chan_resources(struct dma_chan *chan) { struct cppi41_channel *c = to_cpp41_chan(chan); struct cppi41_dd *cdd = c->cdd; int error; error = pm_runtime_get_sync(cdd->ddev.dev); if (error < 0) { pm_runtime_put_noidle(cdd->ddev.dev); return; } WARN_ON(!list_empty(&cdd->pending)); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); } static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct cppi41_channel *c = to_cpp41_chan(chan); enum dma_status ret; /* lock */ ret = dma_cookie_status(chan, cookie, txstate); if (txstate && ret == DMA_COMPLETE) txstate->residue = c->residue; /* unlock */ return ret; } static void push_desc_queue(struct cppi41_channel *c) { struct cppi41_dd *cdd = c->cdd; u32 desc_num; u32 desc_phys; u32 reg; c->residue = 0; reg = GCR_CHAN_ENABLE; if (!c->is_tx) { reg |= GCR_STARV_RETRY; reg |= GCR_DESC_TYPE_HOST; reg |= c->q_comp_num; } cppi_writel(reg, c->gcr_reg); /* * We don't use writel() but __raw_writel() so we have to make sure * that the DMA descriptor in coherent memory made to the main memory * before starting the dma engine. */ __iowmb(); desc_phys = lower_32_bits(c->desc_phys); desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc); WARN_ON(cdd->chan_busy[desc_num]); cdd->chan_busy[desc_num] = c; reg = (sizeof(struct cppi41_desc) - 24) / 4; reg |= desc_phys; cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num)); } static void pending_desc(struct cppi41_channel *c) { struct cppi41_dd *cdd = c->cdd; unsigned long flags; spin_lock_irqsave(&cdd->lock, flags); list_add_tail(&c->node, &cdd->pending); spin_unlock_irqrestore(&cdd->lock, flags); } static void cppi41_dma_issue_pending(struct dma_chan *chan) { struct cppi41_channel *c = to_cpp41_chan(chan); struct cppi41_dd *cdd = c->cdd; int error; error = pm_runtime_get(cdd->ddev.dev); if ((error != -EINPROGRESS) && error < 0) { pm_runtime_put_noidle(cdd->ddev.dev); dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n", error); return; } if (likely(pm_runtime_active(cdd->ddev.dev))) push_desc_queue(c); else pending_desc(c); pm_runtime_mark_last_busy(cdd->ddev.dev); pm_runtime_put_autosuspend(cdd->ddev.dev); } static u32 get_host_pd0(u32 length) { u32 reg; reg = DESC_TYPE_HOST << DESC_TYPE; reg |= length;