// SPDX-License-Identifier: GPL-2.0#include <linux/kernel.h>#include <linux/pgtable.h> #include <linux/string.h>#include <linux/bitops.h>#include <linux/smp.h>#include <linux/sched.h>#include <linux/sched/clock.h>#include <linux/thread_info.h>#include <linux/init.h>#include <linux/uaccess.h> #include <asm/cpufeature.h>#include <asm/msr.h>#include <asm/bugs.h>#include <asm/cpu.h>#include <asm/intel-family.h>#include <asm/microcode_intel.h>#include <asm/hwcap2.h>#include <asm/elf.h>#include <asm/cpu_device_id.h>#include <asm/cmdline.h>#include <asm/traps.h>#include <asm/resctrl.h>#include <asm/numa.h>#include <asm/thermal.h> #ifdef CONFIG_X86_64#include <linux/topology.h>#endif #include "cpu.h" #ifdef CONFIG_X86_LOCAL_APIC#include <asm/mpspec.h>#include <asm/apic.h>#endif enum split_lock_detect_state {	sld_off = 0,	sld_warn,	sld_fatal,}; /* * Default to sld_off because most systems do not support split lock detection. * sld_state_setup() will switch this to sld_warn on systems that support * split lock/bus lock detect, unless there is a command line override. */static enum split_lock_detect_state sld_state __ro_after_init = sld_off;static u64 msr_test_ctrl_cache __ro_after_init; /* * With a name like MSR_TEST_CTL it should go without saying, but don't touch * MSR_TEST_CTL unless the CPU is one of the whitelisted models.  Writing it * on CPUs that do not support SLD can cause fireworks, even when writing '0'. */static bool cpu_model_supports_sld __ro_after_init; /* * Processors which have self-snooping capability can handle conflicting * memory type across CPUs by snooping its own cache. However, there exists * CPU models in which having conflicting memory types still leads to * unpredictable behavior, machine check errors, or hangs. Clear this * feature to prevent its use on machines with known erratas. */static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c){	switch (c->x86_model) {	case INTEL_FAM6_CORE_YONAH:	case INTEL_FAM6_CORE2_MEROM:	case INTEL_FAM6_CORE2_MEROM_L:	case INTEL_FAM6_CORE2_PENRYN:	case INTEL_FAM6_CORE2_DUNNINGTON:	case INTEL_FAM6_NEHALEM:	case INTEL_FAM6_NEHALEM_G:	case INTEL_FAM6_NEHALEM_EP:	case INTEL_FAM6_NEHALEM_EX:	case INTEL_FAM6_WESTMERE:	case INTEL_FAM6_WESTMERE_EP:	case INTEL_FAM6_SANDYBRIDGE:		setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);	}} static bool ring3mwait_disabled __read_mostly; static int __init ring3mwait_disable(char *__unused){	ring3mwait_disabled = true;	return 0;}__setup("ring3mwait=disable", ring3mwait_disable); static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c){	/*	 * Ring 3 MONITOR/MWAIT feature cannot be detected without	 * cpu model and family comparison.	 */	if (c->x86 != 6)		return;	switch (c->x86_model) {	case INTEL_FAM6_XEON_PHI_KNL:	case INTEL_FAM6_XEON_PHI_KNM:		break;	default:		return;	} 	if (ring3mwait_disabled)		return; 	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);	this_cpu_or(msr_misc_features_shadow,		    1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); 	if (c == &boot_cpu_data)		ELF_HWCAP2 |= HWCAP2_RING3MWAIT;} /* * Early microcode releases for the Spectre v2 mitigation were broken. * Information taken from; * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf * - https://kb.vmware.com/s/article/52345 * - Microcode revisions observed in the wild * - Release note from 20180108 microcode release */struct sku_microcode {	u8 model;	u8 stepping;	u32 microcode;};static const struct sku_microcode spectre_bad_microcodes[] = {	{ INTEL_FAM6_KABYLAKE,		0x0B,	0x80 },	{ INTEL_FAM6_KABYLAKE,		0x0A,	0x80 },	{ INTEL_FAM6_KABYLAKE,		0x09,	0x80 },	{ INTEL_FAM6_KABYLAKE_L,	0x0A,	0x80 },	{ INTEL_FAM6_KABYLAKE_L,	0x09,	0x80 },	{ INTEL_FAM6_SKYLAKE_X,		0x03,	0x0100013e },	{ INTEL_FAM6_SKYLAKE_X,		0x04,	0x0200003c },	{ INTEL_FAM6_BROADWELL,		0x04,	0x28 },	{ INTEL_FAM6_BROADWELL_G,	0x01,	0x1b },	{ INTEL_FAM6_BROADWELL_D,	0x02,	0x14 },	{ INTEL_FAM6_BROADWELL_D,	0x03,	0x07000011 },	{ INTEL_FAM6_BROADWELL_X,	0x01,	0x0b000025 },	{ INTEL_FAM6_HASWELL_L,		0x01,	0x21 },	{ INTEL_FAM6_HASWELL_G,		0x01,	0x18 },	{ INTEL_FAM6_HASWELL,		0x03,	0x23 },	{ INTEL_FAM6_HASWELL_X,		0x02,	0x3b },	{ INTEL_FAM6_HASWELL_X,		0x04,	0x10 },	{ INTEL_FAM6_IVYBRIDGE_X,	0x04,	0x42a },	/* Observed in the wild */	{ INTEL_FAM6_SANDYBRIDGE_X,	0x06,	0x61b },	{ INTEL_FAM6_SANDYBRIDGE_X,	0x07,	0x712 },}; static bool bad_spectre_microcode(struct cpuinfo_x86 *c){	int i; 	/*	 * We know that the hypervisor lie to us on the microcode version so	 * we may as well hope that it is running the correct version.	 */	if (cpu_has(c, X86_FEATURE_HYPERVISOR))		return false; 	if (c->x86 != 6)		return false; 	for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {		if (c->x86_model == spectre_bad_microcodes[i].model &&		    c->x86_stepping == spectre_bad_microcodes[i].stepping)			return (c->microcode <= spectre_bad_microcodes[i].microcode);	}	return false;} static void early_init_intel(struct cpuinfo_x86 *c){	u64 misc_enable; 	/* Unmask CPUID levels if masked: */	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {		if (msr_clear_bit(MSR_IA32_MISC_ENABLE,				  MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {			c->cpuid_level = cpuid_eax(0);			get_cpu_cap(c);		}	} 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||		(c->x86 == 0x6 && c->x86_model >= 0x0e))		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))		c->microcode = intel_get_microcode_revision(); 	/* Now if any of them are set, check the blacklist and clear the lot */	if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||	     cpu_has(c, X86_FEATURE_INTEL_STIBP) ||	     cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||	     cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {		pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");		setup_clear_cpu_cap(X86_FEATURE_IBRS);		setup_clear_cpu_cap(X86_FEATURE_IBPB);		setup_clear_cpu_cap(X86_FEATURE_STIBP);		setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);		setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);		setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);		setup_clear_cpu_cap(X86_FEATURE_SSBD);		setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);	} 	/*	 * Atom erratum AAE44/AAF40/AAG38/AAH41:	 *	 * A race condition between speculative fetches and invalidating	 * a large page.  This is worked around in microcode, but we	 * need the microcode to have already been loaded... so if it is	 * not, recommend a BIOS update and disable large pages.	 */	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&	    c->microcode < 0x20e) {		pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");		clear_cpu_cap(c, X86_FEATURE_PSE);	} #ifdef CONFIG_X86_64	set_cpu_cap(c, X86_FEATURE_SYSENTER32);#else	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */	if (c->x86 == 15 && c->x86_cache_alignment == 64)		c->x86_cache_alignment = 128;#endif 	/* CPUID workaround for 0F33/0F34 CPU */	if (c->x86 == 0xF && c->x86_model == 0x3	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))		c->x86_phys_bits = 36; 	/*	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate	 * with P/T states and does not stop in deep C-states.	 *	 * It is also reliable across cores and sockets. (but not across	 * cabinets - we turn it off in that case explicitly.)	 */	if (c->x86_power & (1 << 8)) {		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);	} 	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */	if (c->x86 == 6) {		switch (c->x86_model) {		case INTEL_FAM6_ATOM_SALTWELL_MID:		case INTEL_FAM6_ATOM_SALTWELL_TABLET:		case INTEL_FAM6_ATOM_SILVERMONT_MID:		case INTEL_FAM6_ATOM_AIRMONT_NP:			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);			break;		default:			break;		}	} 	/*	 * There is a known erratum on Pentium III and Core Solo	 * and Core Duo CPUs.	 * " Page with PAT set to WC while associated MTRR is UC	 *   may consolidate to UC "	 * Because of this erratum, it is better to stick with	 * setting WC in MTRR rather than using PAT on these CPUs.	 *	 * Enable PAT WC only on P4, Core 2 or later CPUs.	 */	if (c->x86 == 6 && c->x86_model < 15)		clear_cpu_cap(c, X86_FEATURE_PAT); 	/*	 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,	 * clear the fast string and enhanced fast string CPU capabilities.	 */	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);		if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {			pr_info("Disabled fast string operations\n");			setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);			setup_clear_cpu_cap(X86_FEATURE_ERMS);		}	} 	/*	 * Intel Quark Core DevMan_001.pdf section 6.4.11	 * "The operating system also is required to invalidate (i.e., flush)	 *  the TLB when any changes are made to any of the page table entries.	 *  The operating system must reload CR3 to cause the TLB to be flushed"	 *	 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h	 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE	 * to be modified.	 */	if (c->x86 == 5 && c->x86_model == 9) {		pr_info("Disabling PGE capability bit\n");		setup_clear_cpu_cap(X86_FEATURE_PGE);	} 	if (c->cpuid_level >= 0x00000001) {		u32 eax, ebx, ecx, edx; 		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);		/*		 * If HTT (EDX[28]) is set EBX[16:23] contain the number of		 * apicids which are reserved per package. Store the resulting		 * shift value for the package management code.		 */		if (edx & (1U << 28))			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);	} 	check_memory_type_self_snoop_errata(c); 	/*	 * Get the number of SMT siblings early from the extended topology	 * leaf, if available. Otherwise try the legacy SMT detection.	 */	if (detect_extended_topology_early(c) < 0)		detect_ht_early(c);} static void bsp_init_intel(struct cpuinfo_x86 *c){	resctrl_cpu_detect(c);} #ifdef CONFIG_X86_32/* *	Early probe support logic for ppro memory erratum #50 * *	This is called before we do cpu ident work */ int ppro_with_ram_bug(void){	/* Uses data from early_cpu_detect now */	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&	    boot_cpu_data.x86 == 6 &&	    boot_cpu_data.x86_model == 1 &&	    boot_cpu_data.x86_stepping < 8) {		pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");		return 1;	}	return 0;} static void intel_smp_check(struct cpuinfo_x86 *c){	/* calling is from identify_secondary_cpu() ? */	if (!c->cpu_index)		return; 	/*	 * Mask B, Pentium, but not Pentium MMX	 */	if (c->x86 == 5 &&	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&	    c->x86_model <= 3) {		/*		 * Remember we have B step Pentia with bugs		 */		WARN_ONCE(1, "WARNING: SMP operation may be unreliable"				    "with B stepping processors.\n");	}} static int forcepae;static int __init forcepae_setup(char *__unused){	forcepae = 1;	return 1;}__setup("forcepae", forcepae_setup); static void intel_workarounds(struct cpuinfo_x86 *c){#ifdef CONFIG_X86_F00F_BUG	/*	 * All models of Pentium and Pentium with MMX technology CPUs	 * have the F0 0F bug, which lets nonprivileged users lock up the	 * system. Announce that the fault handler will be checking for it.	 * The Quark is also family 5, but does not have the same bug.	 */	clear_cpu_bug(c, X86_BUG_F00F);	if (c->x86 == 5 && c->x86_model < 9) {		static int f00f_workaround_enabled; 		set_cpu_bug(c, X86_BUG_F00F);		if (!f00f_workaround_enabled) {			pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");			f00f_workaround_enabled = 1;		}	}#endif 	/*	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until	 * model 3 mask 3	 */	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)		clear_cpu_cap(c, X86_FEATURE_SEP); 	/*	 * PAE CPUID issue: many Pentium M report no PAE but may have a	 * functionally usable PAE implementation.	 * Forcefully enable PAE if kernel parameter "forcepae" is present.	 */	if (forcepae) {		pr_warn("PAE forced!\n");		set_cpu_cap(c, X86_FEATURE_PAE);		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);	} 	/*	 * P4 Xeon erratum 037 workaround.	 * Hardware prefetcher may cause stale data to be loaded into the cache.	 */	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {		if (msr_set_bit(MSR_IA32_MISC_ENABLE,				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {			pr_info("CPU: C0 stepping P4 Xeon detected.\n");			pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");		}	} 	/*	 * See if we have a good local APIC by checking for buggy Pentia,	 * i.e. all B steppings and the C2 stepping of P54C when using their	 * integrated APIC (see 11AP erratum in "Pentium Processor	 * Specification Update").	 */	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))		set_cpu_bug(c, X86_BUG_11AP);  #ifdef CONFIG_X86_INTEL_USERCOPY	/*	 * Set up the preferred alignment for movsl bulk memory moves	 */	switch (c->x86) {	case 4:		/* 486: untested */		break;	case 5:		/* Old Pentia: untested */		break;	case 6:		/* PII/PIII only like movsl with 8-byte alignment */		movsl_mask.mask = 7;		break;	case 15:	/* P4 is OK down to 8-byte alignment */		movsl_mask.mask = 7;		break;	}#endif 	intel_smp_check(c);}#elsestatic void intel_workarounds(struct cpuinfo_x86 *c){}#endif static void srat_detect_node(struct cpuinfo_x86 *c){#ifdef CONFIG_NUMA	unsigned node;	int cpu = smp_processor_id(); 	/* Don't do the funky fallback heuristics the AMD version employs	   for now. */	node = numa_cpu_node(cpu);	if (node == NUMA_NO_NODE || !node_online(node)) {		/* reuse the value from init_cpu_to_node() */		node = cpu_to_node(cpu);	}	numa_set_node(cpu, node);#endif} #define MSR_IA32_TME_ACTIVATE		0x982 /* Helpers to access TME_ACTIVATE MSR */#define TME_ACTIVATE_LOCKED(x)		(x & 0x1)#define TME_ACTIVATE_ENABLED(x)		(x & 0x2) #define TME_ACTIVATE_POLICY(x)		((x >> 4) & 0xf)	/* Bits 7:4 */#define TME_ACTIVATE_POLICY_AES_XTS_128	0

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