/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: monk liu <monk.liu@amd.com> */ #include <drm/drm_auth.h>#include "amdgpu.h"#include "amdgpu_sched.h"#include "amdgpu_ras.h"#include <linux/nospec.h> #define to_amdgpu_ctx_entity(e)	\	container_of((e), struct amdgpu_ctx_entity, entity) const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = {	[AMDGPU_HW_IP_GFX]	=	1,	[AMDGPU_HW_IP_COMPUTE]	=	4,	[AMDGPU_HW_IP_DMA]	=	2,	[AMDGPU_HW_IP_UVD]	=	1,	[AMDGPU_HW_IP_VCE]	=	1,	[AMDGPU_HW_IP_UVD_ENC]	=	1,	[AMDGPU_HW_IP_VCN_DEC]	=	1,	[AMDGPU_HW_IP_VCN_ENC]	=	1,	[AMDGPU_HW_IP_VCN_JPEG]	=	1,}; bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio){	switch (ctx_prio) {	case AMDGPU_CTX_PRIORITY_UNSET:	case AMDGPU_CTX_PRIORITY_VERY_LOW:	case AMDGPU_CTX_PRIORITY_LOW:	case AMDGPU_CTX_PRIORITY_NORMAL:	case AMDGPU_CTX_PRIORITY_HIGH:	case AMDGPU_CTX_PRIORITY_VERY_HIGH:		return true;	default:		return false;	}} static enum drm_sched_priorityamdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio){	switch (ctx_prio) {	case AMDGPU_CTX_PRIORITY_UNSET:		return DRM_SCHED_PRIORITY_UNSET; 	case AMDGPU_CTX_PRIORITY_VERY_LOW:		return DRM_SCHED_PRIORITY_MIN; 	case AMDGPU_CTX_PRIORITY_LOW:		return DRM_SCHED_PRIORITY_MIN; 	case AMDGPU_CTX_PRIORITY_NORMAL:		return DRM_SCHED_PRIORITY_NORMAL; 	case AMDGPU_CTX_PRIORITY_HIGH:		return DRM_SCHED_PRIORITY_HIGH; 	case AMDGPU_CTX_PRIORITY_VERY_HIGH:		return DRM_SCHED_PRIORITY_HIGH; 	/* This should not happen as we sanitized userspace provided priority	 * already, WARN if this happens.	 */	default:		WARN(1, "Invalid context priority %d\n", ctx_prio);		return DRM_SCHED_PRIORITY_NORMAL;	} } static int amdgpu_ctx_priority_permit(struct drm_file *filp,				      int32_t priority){	if (!amdgpu_ctx_priority_is_valid(priority))		return -EINVAL; 	/* NORMAL and below are accessible by everyone */	if (priority <= AMDGPU_CTX_PRIORITY_NORMAL)		return 0; 	if (capable(CAP_SYS_NICE))		return 0; 	if (drm_is_current_master(filp))		return 0; 	return -EACCES;} static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio){	switch (prio) {	case AMDGPU_CTX_PRIORITY_HIGH:	case AMDGPU_CTX_PRIORITY_VERY_HIGH:		return AMDGPU_GFX_PIPE_PRIO_HIGH;	default:		return AMDGPU_GFX_PIPE_PRIO_NORMAL;	}} static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio){	switch (prio) {	case AMDGPU_CTX_PRIORITY_HIGH:		return AMDGPU_RING_PRIO_1;	case AMDGPU_CTX_PRIORITY_VERY_HIGH:		return AMDGPU_RING_PRIO_2;	default:		return AMDGPU_RING_PRIO_0;	}} static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip){	struct amdgpu_device *adev = ctx->adev;	int32_t ctx_prio;	unsigned int hw_prio; 	ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ?			ctx->init_priority : ctx->override_priority; 	switch (hw_ip) {	case AMDGPU_HW_IP_COMPUTE:		hw_prio = amdgpu_ctx_prio_to_compute_prio(ctx_prio);		break;	case AMDGPU_HW_IP_VCE:	case AMDGPU_HW_IP_VCN_ENC:		hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio);		break;	default:		hw_prio = AMDGPU_RING_PRIO_DEFAULT;		break;	} 	hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM);	if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0)		hw_prio = AMDGPU_RING_PRIO_DEFAULT; 	return hw_prio;}  static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip,				  const u32 ring){	struct amdgpu_device *adev = ctx->adev;	struct amdgpu_ctx_entity *entity;	struct drm_gpu_scheduler **scheds = NULL, *sched = NULL;	unsigned num_scheds = 0;	int32_t ctx_prio;	unsigned int hw_prio;	enum drm_sched_priority drm_prio;	int r; 	entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs),			 GFP_KERNEL);	if (!entity)		return  -ENOMEM; 	ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ?			ctx->init_priority : ctx->override_priority;	entity->sequence = 1;	hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip);	drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 	hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM);	scheds = adev->gpu_sched[hw_ip][hw_prio].sched;	num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 	/* disable load balance if the hw engine retains context among dependent jobs */	if (hw_ip == AMDGPU_HW_IP_VCN_ENC ||	    hw_ip == AMDGPU_HW_IP_VCN_DEC ||	    hw_ip == AMDGPU_HW_IP_UVD_ENC ||	    hw_ip == AMDGPU_HW_IP_UVD) {		sched = drm_sched_pick_best(scheds, num_scheds);		scheds = &sched;		num_scheds = 1;	} 	r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds,				  &ctx->guilty);	if (r)		goto error_free_entity; 	ctx->entities[hw_ip][ring] = entity;	return 0; error_free_entity:	kfree(entity); 	return r;} static int amdgpu_ctx_init(struct amdgpu_device *adev,			   int32_t priority,			   struct drm_file *filp,			   struct amdgpu_ctx *ctx){	int r; 	r = amdgpu_ctx_priority_permit(filp, priority);	if (r)		return r; 	memset(ctx, 0, sizeof(*ctx)); 	ctx->adev = adev; 	kref_init(&ctx->refcount);	spin_lock_init(&ctx->ring_lock);	mutex_init(&ctx->lock); 	ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);	ctx->reset_counter_query = ctx->reset_counter;	ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);	ctx->init_priority = priority;	ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 	return 0;} static void amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity){ 	int i; 	if (!entity)		return; 	for (i = 0; i < amdgpu_sched_jobs; ++i)		dma_fence_put(entity->fences[i]); 	kfree(entity);} static void amdgpu_ctx_fini(struct kref *ref){	struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);	struct amdgpu_device *adev = ctx->adev;	unsigned i, j; 	if (!adev)		return; 	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {		for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) {			amdgpu_ctx_fini_entity(ctx->entities[i][j]);			ctx->entities[i][j] = NULL;		}	} 	mutex_destroy(&ctx->lock);	kfree(ctx);} int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,			  u32 ring, struct drm_sched_entity **entity){	int r; 	if (hw_ip >= AMDGPU_HW_IP_NUM) {		DRM_ERROR("unknown HW IP type: %d\n", hw_ip);		return -EINVAL;	} 	/* Right now all IPs have only one instance - multiple rings. */	if (instance != 0) {		DRM_DEBUG("invalid ip instance: %d\n", instance);		return -EINVAL;	} 	if (ring >= amdgpu_ctx_num_entities[hw_ip]) {		DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring);		return -EINVAL;	} 	if (ctx->entities[hw_ip][ring] == NULL) {		r = amdgpu_ctx_init_entity(ctx, hw_ip, ring);		if (r)			return r;	} 	*entity = &ctx->entities[hw_ip][ring]->entity;	return 0;} static int amdgpu_ctx_alloc(struct amdgpu_device *adev,			    struct amdgpu_fpriv *fpriv,			    struct drm_file *filp,			    int32_t priority,			    uint32_t *id){	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;	struct amdgpu_ctx *ctx;	int r; 	ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);	if (!ctx)		return -ENOMEM; 	mutex_lock(&mgr->lock);	r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL);	if (r < 0) {		mutex_unlock(&mgr->lock);		kfree(ctx);		return r;	} 	*id = (uint32_t)r;	r = amdgpu_ctx_init(adev, priority, filp, ctx);	if (r) {		idr_remove(&mgr->ctx_handles, *id);		*id = 0;		kfree(ctx);	}	mutex_unlock(&mgr->lock);	return r;} static void amdgpu_ctx_do_release(struct kref *ref){	struct amdgpu_ctx *ctx;	u32 i, j; 	ctx = container_of(ref, struct amdgpu_ctx, refcount);	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {		for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {			if (!ctx->entities[i][j])				continue; 			drm_sched_entity_destroy(&ctx->entities[i][j]->entity);		}	} 	amdgpu_ctx_fini(ref);} static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id){	struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;	struct amdgpu_ctx *ctx; 	mutex_lock(&mgr->lock);	ctx = idr_remove(&mgr->ctx_handles, id);	if (ctx)		kref_put(&ctx->refcount, amdgpu_ctx_do_release);	mutex_unlock(&mgr->lock);	return ctx ? 0 : -EINVAL;} static int amdgpu_ctx_query(struct amdgpu_device *adev,			    struct amdgpu_fpriv *fpriv, uint32_t id,			    union drm_amdgpu_ctx_out *out){	struct amdgpu_ctx *ctx;	struct amdgpu_ctx_mgr *mgr;	unsigned reset_counter; 	if (!fpriv)		return -EINVAL; 	mgr = &fpriv->ctx_mgr;	mutex_lock(&mgr->lock);	ctx = idr_find(&mgr->ctx_handles, id);	if (!ctx) {		mutex_unlock(&mgr->lock);		return -EINVAL;	} 	/* TODO: these two are always zero */	out->state.flags = 0x0;	out->state.hangs = 0x0; 	/* determine if a GPU reset has occured since the last call */	reset_counter = atomic_read(&adev->gpu_reset_counter);	/* TODO: this should ideally return NO, GUILTY, or INNOCENT. */	if (ctx->reset_counter_query == reset_counter)		out->state.reset_status = AMDGPU_CTX_NO_RESET;	else		out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;	ctx->reset_counter_query = reset_counter; 	mutex_unlock(&mgr->lock);	return 0;} #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 static int amdgpu_ctx_query2(struct amdgpu_device *adev,			     struct amdgpu_fpriv *fpriv, uint32_t id,			     union drm_amdgpu_ctx_out *out){	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	struct amdgpu_ctx *ctx;	struct amdgpu_ctx_mgr *mgr; 	if (!fpriv)		return -EINVAL; 	mgr = &fpriv->ctx_mgr;	mutex_lock(&mgr->lock);	ctx = idr_find(&mgr->ctx_handles, id);	if (!ctx) {		mutex_unlock(&mgr->lock);		return -EINVAL;	} 	out->state.flags = 0x0;	out->state.hangs = 0x0; 	if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter))		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 	if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter))		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 	if (atomic_read(&ctx->guilty))		out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 	if (adev->ras_enabled && con) {		/* Return the cached values in O(1),		 * and schedule delayed work to cache		 * new vaues.		 */		int ce_count, ue_count; 		ce_count = atomic_read(&con->ras_ce_count);		ue_count = atomic_read(&con->ras_ue_count); 		if (ce_count != ctx->ras_counter_ce) {			ctx->ras_counter_ce = ce_count;			out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;		} 		if (ue_count != ctx->ras_counter_ue) {			ctx->ras_counter_ue = ue_count;			out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;		} 		schedule_delayed_work(&con->ras_counte_delay_work,				      msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));	} 	mutex_unlock(&mgr->lock);	return 0;} int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,		     struct drm_file *filp){	int r;	uint32_t id;	int32_t priority; 	union drm_amdgpu_ctx *args = data;	struct amdgpu_device *adev = drm_to_adev(dev);	struct amdgpu_fpriv *fpriv = filp->driver_priv; 	id = args->in.ctx_id;	priority = args->in.priority; 	/* For backwards compatibility reasons, we need to accept	 * ioctls with garbage in the priority field */	if (!amdgpu_ctx_priority_is_valid(priority))		priority = AMDGPU_CTX_PRIORITY_NORMAL; 	switch (args->in.op) {	case AMDGPU_CTX_OP_ALLOC_CTX:		r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);		args->out.alloc.ctx_id = id;		break;	case AMDGPU_CTX_OP_FREE_CTX:		r = amdgpu_ctx_free(fpriv, id);		break;	case AMDGPU_CTX_OP_QUERY_STATE:		r = amdgpu_ctx_query(adev, fpriv, id, &args->out);		break;	case AMDGPU_CTX_OP_QUERY_STATE2:

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