/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h>#include <linux/slab.h>#include <linux/module.h> #include "amdgpu.h"#include "amdgpu_ucode.h" static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr){ DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); DRM_DEBUG("ucode_array_offset_bytes: %u\n", le32_to_cpu(hdr->ucode_array_offset_bytes)); DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));} void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("MC\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct mc_firmware_header_v1_0 *mc_hdr = container_of(hdr, struct mc_firmware_header_v1_0, header); DRM_DEBUG("io_debug_size_bytes: %u\n", le32_to_cpu(mc_hdr->io_debug_size_bytes)); DRM_DEBUG("io_debug_array_offset_bytes: %u\n", le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); } else { DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); }} void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); const struct smc_firmware_header_v1_0 *v1_0_hdr; const struct smc_firmware_header_v2_0 *v2_0_hdr; const struct smc_firmware_header_v2_1 *v2_1_hdr; DRM_DEBUG("SMC\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); } else if (version_major == 2) { switch (version_minor) { case 0: v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); break; case 1: v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); break; default: break; } } else { DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); }} void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("GFX\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct gfx_firmware_header_v1_0 *gfx_hdr = container_of(hdr, struct gfx_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(gfx_hdr->ucode_feature_version)); DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); } else { DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); }} void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("RLC\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct rlc_firmware_header_v1_0 *rlc_hdr = container_of(hdr, struct rlc_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(rlc_hdr->ucode_feature_version)); DRM_DEBUG("save_and_restore_offset: %u\n", le32_to_cpu(rlc_hdr->save_and_restore_offset)); DRM_DEBUG("clear_state_descriptor_offset: %u\n", le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); DRM_DEBUG("avail_scratch_ram_locations: %u\n", le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); DRM_DEBUG("master_pkt_description_offset: %u\n", le32_to_cpu(rlc_hdr->master_pkt_description_offset)); } else if (version_major == 2) { const struct rlc_firmware_header_v2_0 *rlc_hdr = container_of(hdr, struct rlc_firmware_header_v2_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(rlc_hdr->ucode_feature_version)); DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); DRM_DEBUG("save_and_restore_offset: %u\n", le32_to_cpu(rlc_hdr->save_and_restore_offset)); DRM_DEBUG("clear_state_descriptor_offset: %u\n", le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); DRM_DEBUG("avail_scratch_ram_locations: %u\n", le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); DRM_DEBUG("reg_restore_list_size: %u\n", le32_to_cpu(rlc_hdr->reg_restore_list_size)); DRM_DEBUG("reg_list_format_start: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_start)); DRM_DEBUG("reg_list_format_separate_start: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); DRM_DEBUG("starting_offsets_start: %u\n", le32_to_cpu(rlc_hdr->starting_offsets_start)); DRM_DEBUG("reg_list_format_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); DRM_DEBUG("reg_list_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_size_bytes)); DRM_DEBUG("reg_list_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); DRM_DEBUG("reg_list_separate_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); if (version_minor == 1) { const struct rlc_firmware_header_v2_1 *v2_1 = container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); } } else { DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); }} void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("SDMA\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct sdma_firmware_header_v1_0 *sdma_hdr = container_of(hdr, struct sdma_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(sdma_hdr->ucode_feature_version)); DRM_DEBUG("ucode_change_version: %u\n", le32_to_cpu(sdma_hdr->ucode_change_version)); DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); if (version_minor >= 1) { const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); } } else { DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", version_major, version_minor); }} void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("PSP\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct psp_firmware_header_v1_0 *psp_hdr = container_of(hdr, struct psp_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(psp_hdr->sos.fw_version)); DRM_DEBUG("sos_offset_bytes: %u\n", le32_to_cpu(psp_hdr->sos.offset_bytes)); DRM_DEBUG("sos_size_bytes: %u\n", le32_to_cpu(psp_hdr->sos.size_bytes)); if (version_minor == 1) { const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); DRM_DEBUG("toc_header_version: %u\n", le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); DRM_DEBUG("toc_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); DRM_DEBUG("kdb_header_version: %u\n", le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); } if (version_minor == 2) { const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); DRM_DEBUG("kdb_header_version: %u\n", le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); } if (version_minor == 3) { const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); DRM_DEBUG("toc_header_version: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); DRM_DEBUG("toc_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); DRM_DEBUG("kdb_header_version: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); DRM_DEBUG("spl_header_version: %u\n", le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); DRM_DEBUG("spl_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); DRM_DEBUG("spl_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); } } else { DRM_ERROR("Unknown PSP ucode version: %u.%u\n", version_major, version_minor); }} void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr){ uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("GPU_INFO\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = container_of(hdr, struct gpu_info_firmware_header_v1_0, header); DRM_DEBUG("version_major: %u\n", le16_to_cpu(gpu_info_hdr->version_major)); DRM_DEBUG("version_minor: %u\n", le16_to_cpu(gpu_info_hdr->version_minor)); } else { DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); }} int amdgpu_ucode_validate(const struct firmware *fw){ const struct common_firmware_header *hdr = (const struct common_firmware_header *)fw->data; if (fw->size == le32_to_cpu(hdr->size_bytes)) return 0; return -EINVAL;} bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, uint16_t hdr_major, uint16_t hdr_minor){ if ((hdr->common.header_version_major == hdr_major) && (hdr->common.header_version_minor == hdr_minor)) return false; return true;} enum amdgpu_firmware_load_typeamdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type){ switch (adev->asic_type) {#ifdef CONFIG_DRM_AMDGPU_SI case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: return AMDGPU_FW_LOAD_DIRECT;#endif#ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: case CHIP_KAVERI: case CHIP_KABINI: case CHIP_HAWAII: case CHIP_MULLINS: return AMDGPU_FW_LOAD_DIRECT;#endif case CHIP_TOPAZ: case CHIP_TONGA: case CHIP_FIJI: case CHIP_CARRIZO: case CHIP_STONEY: case CHIP_POLARIS10: case CHIP_POLARIS11: case CHIP_POLARIS12: case CHIP_VEGAM: return AMDGPU_FW_LOAD_SMU; case CHIP_VEGA10: case CHIP_RAVEN: case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_ARCTURUS: case CHIP_RENOIR: case CHIP_NAVI10: case CHIP_NAVI14: case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: case CHIP_ALDEBARAN: case CHIP_BEIGE_GOBY: case CHIP_YELLOW_CARP: if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; case CHIP_CYAN_SKILLFISH: if (!(load_type && adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; default: if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; }} const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id){ switch (ucode_id) { case AMDGPU_UCODE_ID_SDMA0: return "SDMA0"; case AMDGPU_UCODE_ID_SDMA1: return "SDMA1"; case AMDGPU_UCODE_ID_SDMA2: return "SDMA2"; case AMDGPU_UCODE_ID_SDMA3: return "SDMA3"; case AMDGPU_UCODE_ID_SDMA4: return "SDMA4"; case AMDGPU_UCODE_ID_SDMA5: return "SDMA5"; case AMDGPU_UCODE_ID_SDMA6: return "SDMA6"; case AMDGPU_UCODE_ID_SDMA7: return "SDMA7"; case AMDGPU_UCODE_ID_CP_CE: return "CP_CE"; case AMDGPU_UCODE_ID_CP_PFP: return "CP_PFP"; case AMDGPU_UCODE_ID_CP_ME: return "CP_ME"; case AMDGPU_UCODE_ID_CP_MEC1: return "CP_MEC1"; case AMDGPU_UCODE_ID_CP_MEC1_JT: return "CP_MEC1_JT"; case AMDGPU_UCODE_ID_CP_MEC2: return "CP_MEC2"; case AMDGPU_UCODE_ID_CP_MEC2_JT: return "CP_MEC2_JT"; case AMDGPU_UCODE_ID_CP_MES: return "CP_MES"; case AMDGPU_UCODE_ID_CP_MES_DATA: return "CP_MES_DATA"; case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: return "RLC_RESTORE_LIST_CNTL"; case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: return "RLC_RESTORE_LIST_GPM_MEM"; case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: return "RLC_RESTORE_LIST_SRM_MEM"; case AMDGPU_UCODE_ID_RLC_IRAM: return "RLC_IRAM"; case AMDGPU_UCODE_ID_RLC_DRAM: return "RLC_DRAM"; case AMDGPU_UCODE_ID_RLC_G: return "RLC_G"; case AMDGPU_UCODE_ID_STORAGE: return "STORAGE"; case AMDGPU_UCODE_ID_SMC: return "SMC"; case AMDGPU_UCODE_ID_UVD: return "UVD"; case AMDGPU_UCODE_ID_UVD1: return "UVD1"; case AMDGPU_UCODE_ID_VCE: return "VCE"; case AMDGPU_UCODE_ID_VCN: return "VCN"; case AMDGPU_UCODE_ID_VCN1: return "VCN1"; case AMDGPU_UCODE_ID_DMCU_ERAM: return "DMCU_ERAM"; case AMDGPU_UCODE_ID_DMCU_INTV: return "DMCU_INTV"; case AMDGPU_UCODE_ID_VCN0_RAM: return "VCN0_RAM"; case AMDGPU_UCODE_ID_VCN1_RAM: return "VCN1_RAM"; case AMDGPU_UCODE_ID_DMCUB: return "DMCUB"; default: return "UNKNOWN UCODE";Lines 1–500 of 762. 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/* * Copyright 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include <linux/slab.h> #include <linux/module.h> #include "amdgpu.h" #include "amdgpu_ucode.h" static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) { DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); DRM_DEBUG("ucode_array_offset_bytes: %u\n", le32_to_cpu(hdr->ucode_array_offset_bytes)); DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); } void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("MC\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct mc_firmware_header_v1_0 *mc_hdr = container_of(hdr, struct mc_firmware_header_v1_0, header); DRM_DEBUG("io_debug_size_bytes: %u\n", le32_to_cpu(mc_hdr->io_debug_size_bytes)); DRM_DEBUG("io_debug_array_offset_bytes: %u\n", le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); } else { DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); } } void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); const struct smc_firmware_header_v1_0 *v1_0_hdr; const struct smc_firmware_header_v2_0 *v2_0_hdr; const struct smc_firmware_header_v2_1 *v2_1_hdr; DRM_DEBUG("SMC\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header); DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); } else if (version_major == 2) { switch (version_minor) { case 0: v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header); DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); break; case 1: v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header); DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); break; default: break; } } else { DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); } } void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("GFX\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct gfx_firmware_header_v1_0 *gfx_hdr = container_of(hdr, struct gfx_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(gfx_hdr->ucode_feature_version)); DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); } else { DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); } } void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("RLC\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct rlc_firmware_header_v1_0 *rlc_hdr = container_of(hdr, struct rlc_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(rlc_hdr->ucode_feature_version)); DRM_DEBUG("save_and_restore_offset: %u\n", le32_to_cpu(rlc_hdr->save_and_restore_offset)); DRM_DEBUG("clear_state_descriptor_offset: %u\n", le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); DRM_DEBUG("avail_scratch_ram_locations: %u\n", le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); DRM_DEBUG("master_pkt_description_offset: %u\n", le32_to_cpu(rlc_hdr->master_pkt_description_offset)); } else if (version_major == 2) { const struct rlc_firmware_header_v2_0 *rlc_hdr = container_of(hdr, struct rlc_firmware_header_v2_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(rlc_hdr->ucode_feature_version)); DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); DRM_DEBUG("save_and_restore_offset: %u\n", le32_to_cpu(rlc_hdr->save_and_restore_offset)); DRM_DEBUG("clear_state_descriptor_offset: %u\n", le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); DRM_DEBUG("avail_scratch_ram_locations: %u\n", le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); DRM_DEBUG("reg_restore_list_size: %u\n", le32_to_cpu(rlc_hdr->reg_restore_list_size)); DRM_DEBUG("reg_list_format_start: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_start)); DRM_DEBUG("reg_list_format_separate_start: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); DRM_DEBUG("starting_offsets_start: %u\n", le32_to_cpu(rlc_hdr->starting_offsets_start)); DRM_DEBUG("reg_list_format_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); DRM_DEBUG("reg_list_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_size_bytes)); DRM_DEBUG("reg_list_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); DRM_DEBUG("reg_list_separate_size_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); if (version_minor == 1) { const struct rlc_firmware_header_v2_1 *v2_1 = container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); } } else { DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); } } void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("SDMA\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct sdma_firmware_header_v1_0 *sdma_hdr = container_of(hdr, struct sdma_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(sdma_hdr->ucode_feature_version)); DRM_DEBUG("ucode_change_version: %u\n", le32_to_cpu(sdma_hdr->ucode_change_version)); DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); if (version_minor >= 1) { const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); } } else { DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", version_major, version_minor); } } void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("PSP\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct psp_firmware_header_v1_0 *psp_hdr = container_of(hdr, struct psp_firmware_header_v1_0, header); DRM_DEBUG("ucode_feature_version: %u\n", le32_to_cpu(psp_hdr->sos.fw_version)); DRM_DEBUG("sos_offset_bytes: %u\n", le32_to_cpu(psp_hdr->sos.offset_bytes)); DRM_DEBUG("sos_size_bytes: %u\n", le32_to_cpu(psp_hdr->sos.size_bytes)); if (version_minor == 1) { const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); DRM_DEBUG("toc_header_version: %u\n", le32_to_cpu(psp_hdr_v1_1->toc.fw_version)); DRM_DEBUG("toc_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->toc.size_bytes)); DRM_DEBUG("kdb_header_version: %u\n", le32_to_cpu(psp_hdr_v1_1->kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes)); } if (version_minor == 2) { const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); DRM_DEBUG("kdb_header_version: %u\n", le32_to_cpu(psp_hdr_v1_2->kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes)); } if (version_minor == 3) { const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 = container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1); DRM_DEBUG("toc_header_version: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version)); DRM_DEBUG("toc_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes)); DRM_DEBUG("toc_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes)); DRM_DEBUG("kdb_header_version: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version)); DRM_DEBUG("kdb_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes)); DRM_DEBUG("kdb_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes)); DRM_DEBUG("spl_header_version: %u\n", le32_to_cpu(psp_hdr_v1_3->spl.fw_version)); DRM_DEBUG("spl_offset_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes)); DRM_DEBUG("spl_size_bytes: %u\n", le32_to_cpu(psp_hdr_v1_3->spl.size_bytes)); } } else { DRM_ERROR("Unknown PSP ucode version: %u.%u\n", version_major, version_minor); } } void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) { uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); DRM_DEBUG("GPU_INFO\n"); amdgpu_ucode_print_common_hdr(hdr); if (version_major == 1) { const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = container_of(hdr, struct gpu_info_firmware_header_v1_0, header); DRM_DEBUG("version_major: %u\n", le16_to_cpu(gpu_info_hdr->version_major)); DRM_DEBUG("version_minor: %u\n", le16_to_cpu(gpu_info_hdr->version_minor)); } else { DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); } } int amdgpu_ucode_validate(const struct firmware *fw) { const struct common_firmware_header *hdr = (const struct common_firmware_header *)fw->data; if (fw->size == le32_to_cpu(hdr->size_bytes)) return 0; return -EINVAL; } bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, uint16_t hdr_major, uint16_t hdr_minor) { if ((hdr->common.header_version_major == hdr_major) && (hdr->common.header_version_minor == hdr_minor)) return false; return true; } enum amdgpu_firmware_load_type amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) { switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_SI case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: return AMDGPU_FW_LOAD_DIRECT; #endif #ifdef CONFIG_DRM_AMDGPU_CIK case CHIP_BONAIRE: case CHIP_KAVERI: case CHIP_KABINI: case CHIP_HAWAII: case CHIP_MULLINS: return AMDGPU_FW_LOAD_DIRECT; #endif case CHIP_TOPAZ: case CHIP_TONGA: case CHIP_FIJI: case CHIP_CARRIZO: case CHIP_STONEY: case CHIP_POLARIS10: case CHIP_POLARIS11: case CHIP_POLARIS12: case CHIP_VEGAM: return AMDGPU_FW_LOAD_SMU; case CHIP_VEGA10: case CHIP_RAVEN: case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_ARCTURUS: case CHIP_RENOIR: case CHIP_NAVI10: case CHIP_NAVI14: case CHIP_NAVI12: case CHIP_SIENNA_CICHLID: case CHIP_NAVY_FLOUNDER: case CHIP_VANGOGH: case CHIP_DIMGREY_CAVEFISH: case CHIP_ALDEBARAN: case CHIP_BEIGE_GOBY: case CHIP_YELLOW_CARP: if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; case CHIP_CYAN_SKILLFISH: if (!(load_type && adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; default: if (!load_type) return AMDGPU_FW_LOAD_DIRECT; else return AMDGPU_FW_LOAD_PSP; } } const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) { switch (ucode_id) { case AMDGPU_UCODE_ID_SDMA0: return "SDMA0"; case AMDGPU_UCODE_ID_SDMA1: return "SDMA1"; case AMDGPU_UCODE_ID_SDMA2: return "SDMA2"; case AMDGPU_UCODE_ID_SDMA3: return "SDMA3"; case AMDGPU_UCODE_ID_SDMA4: return "SDMA4"; case AMDGPU_UCODE_ID_SDMA5: return "SDMA5"; case AMDGPU_UCODE_ID_SDMA6: return "SDMA6"; case AMDGPU_UCODE_ID_SDMA7: return "SDMA7"; case AMDGPU_UCODE_ID_CP_CE: return "CP_CE"; case AMDGPU_UCODE_ID_CP_PFP: return "CP_PFP"; case AMDGPU_UCODE_ID_CP_ME: return "CP_ME"; case AMDGPU_UCODE_ID_CP_MEC1: return "CP_MEC1"; case AMDGPU_UCODE_ID_CP_MEC1_JT: return "CP_MEC1_JT"; case AMDGPU_UCODE_ID_CP_MEC2: return "CP_MEC2"; case AMDGPU_UCODE_ID_CP_MEC2_JT: return "CP_MEC2_JT"; case AMDGPU_UCODE_ID_CP_MES: return "CP_MES"; case AMDGPU_UCODE_ID_CP_MES_DATA: return "CP_MES_DATA"; case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: return "RLC_RESTORE_LIST_CNTL"; case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: return "RLC_RESTORE_LIST_GPM_MEM"; case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: return "RLC_RESTORE_LIST_SRM_MEM"; case AMDGPU_UCODE_ID_RLC_IRAM: return "RLC_IRAM"; case AMDGPU_UCODE_ID_RLC_DRAM: return "RLC_DRAM"; case AMDGPU_UCODE_ID_RLC_G: return "RLC_G"; case AMDGPU_UCODE_ID_STORAGE: return "STORAGE"; case AMDGPU_UCODE_ID_SMC: return "SMC"; case AMDGPU_UCODE_ID_UVD: return "UVD"; case AMDGPU_UCODE_ID_UVD1: return "UVD1"; case AMDGPU_UCODE_ID_VCE: return "VCE"; case AMDGPU_UCODE_ID_VCN: return "VCN"; case AMDGPU_UCODE_ID_VCN1: return "VCN1"; case AMDGPU_UCODE_ID_DMCU_ERAM: return "DMCU_ERAM"; case AMDGPU_UCODE_ID_DMCU_INTV: return "DMCU_INTV"; case AMDGPU_UCODE_ID_VCN0_RAM: return "VCN0_RAM"; case AMDGPU_UCODE_ID_VCN1_RAM: return "VCN1_RAM"; case AMDGPU_UCODE_ID_DMCUB: return "DMCUB"; default: return "UNKNOWN UCODE";