/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004 Thiemo Seufer * Copyright (C) 2013 Imagination Technologies Ltd. */#include <linux/cpu.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/kallsyms.h>#include <linux/kernel.h>#include <linux/nmi.h>#include <linux/personality.h>#include <linux/prctl.h>#include <linux/random.h>#include <linux/sched.h>#include <linux/sched/debug.h>#include <linux/sched/task_stack.h> #include <asm/abi.h>#include <asm/asm.h>#include <asm/dsemul.h>#include <asm/dsp.h>#include <asm/exec.h>#include <asm/fpu.h>#include <asm/inst.h>#include <asm/irq.h>#include <asm/irq_regs.h>#include <asm/isadep.h>#include <asm/msa.h>#include <asm/mips-cps.h>#include <asm/mipsregs.h>#include <asm/processor.h>#include <asm/reg.h>#include <asm/stacktrace.h> #ifdef CONFIG_HOTPLUG_CPUvoid arch_cpu_idle_dead(void){ play_dead();}#endif asmlinkage void ret_from_fork(void);asmlinkage void ret_from_kernel_thread(void); void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp){ unsigned long status; /* New thread loses kernel privileges. */ status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK); status |= KU_USER; regs->cp0_status = status; lose_fpu(0); clear_thread_flag(TIF_MSA_CTX_LIVE); clear_used_math();#ifdef CONFIG_MIPS_FP_SUPPORT atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE);#endif init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp;} void exit_thread(struct task_struct *tsk){ /* * User threads may have allocated a delay slot emulation frame. * If so, clean up that allocation. */ if (!(current->flags & PF_KTHREAD)) dsemul_thread_cleanup(tsk);} int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src){ /* * Save any process state which is live in hardware registers to the * parent context prior to duplication. This prevents the new child * state becoming stale if the parent is preempted before copy_thread() * gets a chance to save the parent's live hardware registers to the * child context. */ preempt_disable(); if (is_msa_enabled()) save_msa(current); else if (is_fpu_owner()) _save_fp(current); save_dsp(current); preempt_enable(); *dst = *src; return 0;} /* * Copy architecture-specific thread state */int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned long kthread_arg, struct task_struct *p, unsigned long tls){ struct thread_info *ti = task_thread_info(p); struct pt_regs *childregs, *regs = current_pt_regs(); unsigned long childksp; childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; /* set up new TSS. */ childregs = (struct pt_regs *) childksp - 1; /* Put the stack after the struct pt_regs. */ childksp = (unsigned long) childregs; p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK; if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) { /* kernel thread */ unsigned long status = p->thread.cp0_status; memset(childregs, 0, sizeof(struct pt_regs)); p->thread.reg16 = usp; /* fn */ p->thread.reg17 = kthread_arg; p->thread.reg29 = childksp; p->thread.reg31 = (unsigned long) ret_from_kernel_thread;#if defined(CONFIG_CPU_R3000) status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | ((status & (ST0_KUC | ST0_IEC)) << 2);#else status |= ST0_EXL;#endif childregs->cp0_status = status; return 0; } /* user thread */ *childregs = *regs; childregs->regs[7] = 0; /* Clear error flag */ childregs->regs[2] = 0; /* Child gets zero as return value */ if (usp) childregs->regs[29] = usp; p->thread.reg29 = (unsigned long) childregs; p->thread.reg31 = (unsigned long) ret_from_fork; /* * New tasks lose permission to use the fpu. This accelerates context * switching for most programs since they don't use the fpu. */ childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); clear_tsk_thread_flag(p, TIF_USEDFPU); clear_tsk_thread_flag(p, TIF_USEDMSA); clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); #ifdef CONFIG_MIPS_MT_FPAFF clear_tsk_thread_flag(p, TIF_FPUBOUND);#endif /* CONFIG_MIPS_MT_FPAFF */ #ifdef CONFIG_MIPS_FP_SUPPORT atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);#endif if (clone_flags & CLONE_SETTLS) ti->tp_value = tls; return 0;} #ifdef CONFIG_STACKPROTECTOR#include <linux/stackprotector.h>unsigned long __stack_chk_guard __read_mostly;EXPORT_SYMBOL(__stack_chk_guard);#endif struct mips_frame_info { void *func; unsigned long func_size; int frame_size; int pc_offset;}; #define J_TARGET(pc,target) \ (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) static inline int is_jr_ra_ins(union mips_instruction *ip){#ifdef CONFIG_CPU_MICROMIPS /* * jr16 ra * jr ra */ if (mm_insn_16bit(ip->word >> 16)) { if (ip->mm16_r5_format.opcode == mm_pool16c_op && ip->mm16_r5_format.rt == mm_jr16_op && ip->mm16_r5_format.imm == 31) return 1; return 0; } if (ip->r_format.opcode == mm_pool32a_op && ip->r_format.func == mm_pool32axf_op && ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op && ip->r_format.rt == 31) return 1; return 0;#else if (ip->r_format.opcode == spec_op && ip->r_format.func == jr_op && ip->r_format.rs == 31) return 1; return 0;#endif} static inline int is_ra_save_ins(union mips_instruction *ip, int *poff){#ifdef CONFIG_CPU_MICROMIPS /* * swsp ra,offset * swm16 reglist,offset(sp) * swm32 reglist,offset(sp) * sw32 ra,offset(sp) * jradiussp - NOT SUPPORTED * * microMIPS is way more fun... */ if (mm_insn_16bit(ip->word >> 16)) { switch (ip->mm16_r5_format.opcode) { case mm_swsp16_op: if (ip->mm16_r5_format.rt != 31) return 0; *poff = ip->mm16_r5_format.imm; *poff = (*poff << 2) / sizeof(ulong); return 1; case mm_pool16c_op: switch (ip->mm16_m_format.func) { case mm_swm16_op: *poff = ip->mm16_m_format.imm; *poff += 1 + ip->mm16_m_format.rlist; *poff = (*poff << 2) / sizeof(ulong); return 1; default: return 0; } default: return 0; } } switch (ip->i_format.opcode) { case mm_sw32_op: if (ip->i_format.rs != 29) return 0; if (ip->i_format.rt != 31) return 0; *poff = ip->i_format.simmediate / sizeof(ulong); return 1; case mm_pool32b_op: switch (ip->mm_m_format.func) { case mm_swm32_func: if (ip->mm_m_format.rd < 0x10) return 0; if (ip->mm_m_format.base != 29) return 0; *poff = ip->mm_m_format.simmediate; *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); *poff /= sizeof(ulong); return 1; default: return 0; } default: return 0; }#else /* sw / sd $ra, offset($sp) */ if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && ip->i_format.rs == 29 && ip->i_format.rt == 31) { *poff = ip->i_format.simmediate / sizeof(ulong); return 1; }#ifdef CONFIG_CPU_LOONGSON64 if ((ip->loongson3_lswc2_format.opcode == swc2_op) && (ip->loongson3_lswc2_format.ls == 1) && (ip->loongson3_lswc2_format.fr == 0) && (ip->loongson3_lswc2_format.base == 29)) { if (ip->loongson3_lswc2_format.rt == 31) { *poff = ip->loongson3_lswc2_format.offset << 1; return 1; } if (ip->loongson3_lswc2_format.rq == 31) { *poff = (ip->loongson3_lswc2_format.offset << 1) + 1; return 1; } }#endif return 0;#endif} static inline int is_jump_ins(union mips_instruction *ip){#ifdef CONFIG_CPU_MICROMIPS /* * jr16,jrc,jalr16,jalr16 * jal * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb * jraddiusp - NOT SUPPORTED * * microMIPS is kind of more fun... */ if (mm_insn_16bit(ip->word >> 16)) { if ((ip->mm16_r5_format.opcode == mm_pool16c_op && (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) return 1; return 0; } if (ip->j_format.opcode == mm_j32_op) return 1; if (ip->j_format.opcode == mm_jal32_op) return 1; if (ip->r_format.opcode != mm_pool32a_op || ip->r_format.func != mm_pool32axf_op) return 0; return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;#else if (ip->j_format.opcode == j_op) return 1; if (ip->j_format.opcode == jal_op) return 1; if (ip->r_format.opcode != spec_op) return 0; return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;#endif} static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size){#ifdef CONFIG_CPU_MICROMIPS unsigned short tmp; /* * addiusp -imm * addius5 sp,-imm * addiu32 sp,sp,-imm * jradiussp - NOT SUPPORTED * * microMIPS is not more fun... */ if (mm_insn_16bit(ip->word >> 16)) { if (ip->mm16_r3_format.opcode == mm_pool16d_op && ip->mm16_r3_format.simmediate & mm_addiusp_func) { tmp = ip->mm_b0_format.simmediate >> 1; tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100; if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */ tmp ^= 0x100; *frame_size = -(signed short)(tmp << 2); return 1; } if (ip->mm16_r5_format.opcode == mm_pool16d_op && ip->mm16_r5_format.rt == 29) { tmp = ip->mm16_r5_format.imm >> 1; *frame_size = -(signed short)(tmp & 0xf); return 1; } return 0; } if (ip->mm_i_format.opcode == mm_addiu32_op && ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) { *frame_size = -ip->i_format.simmediate; return 1; }#else /* addiu/daddiu sp,sp,-imm */ if (ip->i_format.rs != 29 || ip->i_format.rt != 29) return 0; if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) { *frame_size = -ip->i_format.simmediate; return 1; }#endif return 0;} static int get_frame_info(struct mips_frame_info *info){ bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); union mips_instruction insn, *ip, *ip_end; unsigned int last_insn_size = 0; bool saw_jump = false; info->pc_offset = -1; info->frame_size = 0; ip = (void *)msk_isa16_mode((ulong)info->func); if (!ip) goto err; ip_end = (void *)ip + (info->func_size ? info->func_size : 512); while (ip < ip_end) { ip = (void *)ip + last_insn_size; if (is_mmips && mm_insn_16bit(ip->halfword[0])) { insn.word = ip->halfword[0] << 16; last_insn_size = 2; } else if (is_mmips) { insn.word = ip->halfword[0] << 16 | ip->halfword[1]; last_insn_size = 4; } else { insn.word = ip->word; last_insn_size = 4; } if (is_jr_ra_ins(ip)) { break; } else if (!info->frame_size) { is_sp_move_ins(&insn, &info->frame_size); continue; } else if (!saw_jump && is_jump_ins(ip)) { /* * If we see a jump instruction, we are finished * with the frame save. * * Some functions can have a shortcut return at * the beginning of the function, so don't start * looking for jump instruction until we see the * frame setup. * * The RA save instruction can get put into the * delay slot of the jump instruction, so look * at the next instruction, too. */ saw_jump = true; continue; } if (info->pc_offset == -1 && is_ra_save_ins(&insn, &info->pc_offset)) break; if (saw_jump) break; } if (info->frame_size && info->pc_offset >= 0) /* nested */ return 0; if (info->pc_offset < 0) /* leaf */ return 1; /* prologue seems bogus... */err: return -1;} static struct mips_frame_info schedule_mfi __read_mostly; #ifdef CONFIG_KALLSYMSstatic unsigned long get___schedule_addr(void){ return kallsyms_lookup_name("__schedule");}#elsestatic unsigned long get___schedule_addr(void){ union mips_instruction *ip = (void *)schedule; int max_insns = 8; int i; for (i = 0; i < max_insns; i++, ip++) { if (ip->j_format.opcode == j_op) return J_TARGET(ip, ip->j_format.target); } return 0;}#endif static int __init frame_info_init(void){ unsigned long size = 0;#ifdef CONFIG_KALLSYMS unsigned long ofs;#endif unsigned long addr; addr = get___schedule_addr();Lines 1–500 of 910. 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/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2004 Thiemo Seufer * Copyright (C) 2013 Imagination Technologies Ltd. */ #include <linux/cpu.h> #include <linux/errno.h> #include <linux/init.h> #include <linux/kallsyms.h> #include <linux/kernel.h> #include <linux/nmi.h> #include <linux/personality.h> #include <linux/prctl.h> #include <linux/random.h> #include <linux/sched.h> #include <linux/sched/debug.h> #include <linux/sched/task_stack.h> #include <asm/abi.h> #include <asm/asm.h> #include <asm/dsemul.h> #include <asm/dsp.h> #include <asm/exec.h> #include <asm/fpu.h> #include <asm/inst.h> #include <asm/irq.h> #include <asm/irq_regs.h> #include <asm/isadep.h> #include <asm/msa.h> #include <asm/mips-cps.h> #include <asm/mipsregs.h> #include <asm/processor.h> #include <asm/reg.h> #include <asm/stacktrace.h> #ifdef CONFIG_HOTPLUG_CPU void arch_cpu_idle_dead(void) { play_dead(); } #endif asmlinkage void ret_from_fork(void); asmlinkage void ret_from_kernel_thread(void); void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) { unsigned long status; /* New thread loses kernel privileges. */ status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK); status |= KU_USER; regs->cp0_status = status; lose_fpu(0); clear_thread_flag(TIF_MSA_CTX_LIVE); clear_used_math(); #ifdef CONFIG_MIPS_FP_SUPPORT atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); #endif init_dsp(); regs->cp0_epc = pc; regs->regs[29] = sp; } void exit_thread(struct task_struct *tsk) { /* * User threads may have allocated a delay slot emulation frame. * If so, clean up that allocation. */ if (!(current->flags & PF_KTHREAD)) dsemul_thread_cleanup(tsk); } int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { /* * Save any process state which is live in hardware registers to the * parent context prior to duplication. This prevents the new child * state becoming stale if the parent is preempted before copy_thread() * gets a chance to save the parent's live hardware registers to the * child context. */ preempt_disable(); if (is_msa_enabled()) save_msa(current); else if (is_fpu_owner()) _save_fp(current); save_dsp(current); preempt_enable(); *dst = *src; return 0; } /* * Copy architecture-specific thread state */ int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned long kthread_arg, struct task_struct *p, unsigned long tls) { struct thread_info *ti = task_thread_info(p); struct pt_regs *childregs, *regs = current_pt_regs(); unsigned long childksp; childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; /* set up new TSS. */ childregs = (struct pt_regs *) childksp - 1; /* Put the stack after the struct pt_regs. */ childksp = (unsigned long) childregs; p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK; if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) { /* kernel thread */ unsigned long status = p->thread.cp0_status; memset(childregs, 0, sizeof(struct pt_regs)); p->thread.reg16 = usp; /* fn */ p->thread.reg17 = kthread_arg; p->thread.reg29 = childksp; p->thread.reg31 = (unsigned long) ret_from_kernel_thread; #if defined(CONFIG_CPU_R3000) status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | ((status & (ST0_KUC | ST0_IEC)) << 2); #else status |= ST0_EXL; #endif childregs->cp0_status = status; return 0; } /* user thread */ *childregs = *regs; childregs->regs[7] = 0; /* Clear error flag */ childregs->regs[2] = 0; /* Child gets zero as return value */ if (usp) childregs->regs[29] = usp; p->thread.reg29 = (unsigned long) childregs; p->thread.reg31 = (unsigned long) ret_from_fork; /* * New tasks lose permission to use the fpu. This accelerates context * switching for most programs since they don't use the fpu. */ childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); clear_tsk_thread_flag(p, TIF_USEDFPU); clear_tsk_thread_flag(p, TIF_USEDMSA); clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); #ifdef CONFIG_MIPS_MT_FPAFF clear_tsk_thread_flag(p, TIF_FPUBOUND); #endif /* CONFIG_MIPS_MT_FPAFF */ #ifdef CONFIG_MIPS_FP_SUPPORT atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); #endif if (clone_flags & CLONE_SETTLS) ti->tp_value = tls; return 0; } #ifdef CONFIG_STACKPROTECTOR #include <linux/stackprotector.h> unsigned long __stack_chk_guard __read_mostly; EXPORT_SYMBOL(__stack_chk_guard); #endif struct mips_frame_info { void *func; unsigned long func_size; int frame_size; int pc_offset; }; #define J_TARGET(pc,target) \ (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) static inline int is_jr_ra_ins(union mips_instruction *ip) { #ifdef CONFIG_CPU_MICROMIPS /* * jr16 ra * jr ra */ if (mm_insn_16bit(ip->word >> 16)) { if (ip->mm16_r5_format.opcode == mm_pool16c_op && ip->mm16_r5_format.rt == mm_jr16_op && ip->mm16_r5_format.imm == 31) return 1; return 0; } if (ip->r_format.opcode == mm_pool32a_op && ip->r_format.func == mm_pool32axf_op && ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op && ip->r_format.rt == 31) return 1; return 0; #else if (ip->r_format.opcode == spec_op && ip->r_format.func == jr_op && ip->r_format.rs == 31) return 1; return 0; #endif } static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) { #ifdef CONFIG_CPU_MICROMIPS /* * swsp ra,offset * swm16 reglist,offset(sp) * swm32 reglist,offset(sp) * sw32 ra,offset(sp) * jradiussp - NOT SUPPORTED * * microMIPS is way more fun... */ if (mm_insn_16bit(ip->word >> 16)) { switch (ip->mm16_r5_format.opcode) { case mm_swsp16_op: if (ip->mm16_r5_format.rt != 31) return 0; *poff = ip->mm16_r5_format.imm; *poff = (*poff << 2) / sizeof(ulong); return 1; case mm_pool16c_op: switch (ip->mm16_m_format.func) { case mm_swm16_op: *poff = ip->mm16_m_format.imm; *poff += 1 + ip->mm16_m_format.rlist; *poff = (*poff << 2) / sizeof(ulong); return 1; default: return 0; } default: return 0; } } switch (ip->i_format.opcode) { case mm_sw32_op: if (ip->i_format.rs != 29) return 0; if (ip->i_format.rt != 31) return 0; *poff = ip->i_format.simmediate / sizeof(ulong); return 1; case mm_pool32b_op: switch (ip->mm_m_format.func) { case mm_swm32_func: if (ip->mm_m_format.rd < 0x10) return 0; if (ip->mm_m_format.base != 29) return 0; *poff = ip->mm_m_format.simmediate; *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); *poff /= sizeof(ulong); return 1; default: return 0; } default: return 0; } #else /* sw / sd $ra, offset($sp) */ if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && ip->i_format.rs == 29 && ip->i_format.rt == 31) { *poff = ip->i_format.simmediate / sizeof(ulong); return 1; } #ifdef CONFIG_CPU_LOONGSON64 if ((ip->loongson3_lswc2_format.opcode == swc2_op) && (ip->loongson3_lswc2_format.ls == 1) && (ip->loongson3_lswc2_format.fr == 0) && (ip->loongson3_lswc2_format.base == 29)) { if (ip->loongson3_lswc2_format.rt == 31) { *poff = ip->loongson3_lswc2_format.offset << 1; return 1; } if (ip->loongson3_lswc2_format.rq == 31) { *poff = (ip->loongson3_lswc2_format.offset << 1) + 1; return 1; } } #endif return 0; #endif } static inline int is_jump_ins(union mips_instruction *ip) { #ifdef CONFIG_CPU_MICROMIPS /* * jr16,jrc,jalr16,jalr16 * jal * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb * jraddiusp - NOT SUPPORTED * * microMIPS is kind of more fun... */ if (mm_insn_16bit(ip->word >> 16)) { if ((ip->mm16_r5_format.opcode == mm_pool16c_op && (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) return 1; return 0; } if (ip->j_format.opcode == mm_j32_op) return 1; if (ip->j_format.opcode == mm_jal32_op) return 1; if (ip->r_format.opcode != mm_pool32a_op || ip->r_format.func != mm_pool32axf_op) return 0; return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; #else if (ip->j_format.opcode == j_op) return 1; if (ip->j_format.opcode == jal_op) return 1; if (ip->r_format.opcode != spec_op) return 0; return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; #endif } static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size) { #ifdef CONFIG_CPU_MICROMIPS unsigned short tmp; /* * addiusp -imm * addius5 sp,-imm * addiu32 sp,sp,-imm * jradiussp - NOT SUPPORTED * * microMIPS is not more fun... */ if (mm_insn_16bit(ip->word >> 16)) { if (ip->mm16_r3_format.opcode == mm_pool16d_op && ip->mm16_r3_format.simmediate & mm_addiusp_func) { tmp = ip->mm_b0_format.simmediate >> 1; tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100; if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */ tmp ^= 0x100; *frame_size = -(signed short)(tmp << 2); return 1; } if (ip->mm16_r5_format.opcode == mm_pool16d_op && ip->mm16_r5_format.rt == 29) { tmp = ip->mm16_r5_format.imm >> 1; *frame_size = -(signed short)(tmp & 0xf); return 1; } return 0; } if (ip->mm_i_format.opcode == mm_addiu32_op && ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) { *frame_size = -ip->i_format.simmediate; return 1; } #else /* addiu/daddiu sp,sp,-imm */ if (ip->i_format.rs != 29 || ip->i_format.rt != 29) return 0; if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) { *frame_size = -ip->i_format.simmediate; return 1; } #endif return 0; } static int get_frame_info(struct mips_frame_info *info) { bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); union mips_instruction insn, *ip, *ip_end; unsigned int last_insn_size = 0; bool saw_jump = false; info->pc_offset = -1; info->frame_size = 0; ip = (void *)msk_isa16_mode((ulong)info->func); if (!ip) goto err; ip_end = (void *)ip + (info->func_size ? info->func_size : 512); while (ip < ip_end) { ip = (void *)ip + last_insn_size; if (is_mmips && mm_insn_16bit(ip->halfword[0])) { insn.word = ip->halfword[0] << 16; last_insn_size = 2; } else if (is_mmips) { insn.word = ip->halfword[0] << 16 | ip->halfword[1]; last_insn_size = 4; } else { insn.word = ip->word; last_insn_size = 4; } if (is_jr_ra_ins(ip)) { break; } else if (!info->frame_size) { is_sp_move_ins(&insn, &info->frame_size); continue; } else if (!saw_jump && is_jump_ins(ip)) { /* * If we see a jump instruction, we are finished * with the frame save. * * Some functions can have a shortcut return at * the beginning of the function, so don't start * looking for jump instruction until we see the * frame setup. * * The RA save instruction can get put into the * delay slot of the jump instruction, so look * at the next instruction, too. */ saw_jump = true; continue; } if (info->pc_offset == -1 && is_ra_save_ins(&insn, &info->pc_offset)) break; if (saw_jump) break; } if (info->frame_size && info->pc_offset >= 0) /* nested */ return 0; if (info->pc_offset < 0) /* leaf */ return 1; /* prologue seems bogus... */ err: return -1; } static struct mips_frame_info schedule_mfi __read_mostly; #ifdef CONFIG_KALLSYMS static unsigned long get___schedule_addr(void) { return kallsyms_lookup_name("__schedule"); } #else static unsigned long get___schedule_addr(void) { union mips_instruction *ip = (void *)schedule; int max_insns = 8; int i; for (i = 0; i < max_insns; i++, ip++) { if (ip->j_format.opcode == j_op) return J_TARGET(ip, ip->j_format.target); } return 0; } #endif static int __init frame_info_init(void) { unsigned long size = 0; #ifdef CONFIG_KALLSYMS unsigned long ofs; #endif unsigned long addr; addr = get___schedule_addr();