/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/kthread.h>#include <linux/pci.h>#include <linux/uaccess.h>#include <linux/pm_runtime.h> #include "amdgpu.h"#include "amdgpu_pm.h"#include "amdgpu_dm_debugfs.h"#include "amdgpu_ras.h"#include "amdgpu_rap.h"#include "amdgpu_securedisplay.h"#include "amdgpu_fw_attestation.h"#include "amdgpu_umr.h" #include "amdgpu_reset.h"#include "amdgpu_psp_ta.h" #if defined(CONFIG_DEBUG_FS) /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * * @read: True if reading * @f: open file handle * @buf: User buffer to write/read to * @size: Number of bytes to write/read * @pos:  Offset to seek to * * This debugfs entry has special meaning on the offset being sought. * Various bits have different meanings: * * Bit 62:  Indicates a GRBM bank switch is needed * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is * 	    zero) * Bits 24..33: The SE or ME selector if needed * Bits 34..43: The SH (or SA) or PIPE selector if needed * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed * * Bit 23:  Indicates that the PM power gating lock should be held * 	    This is necessary to read registers that might be * 	    unreliable during a power gating transistion. * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,		char __user *buf, size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r;	bool pm_pg_lock, use_bank, use_ring;	unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid; 	pm_pg_lock = use_bank = use_ring = false;	instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0; 	if (size & 0x3 || *pos & 0x3 ||			((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))		return -EINVAL; 	/* are we reading registers for which a PG lock is necessary? */	pm_pg_lock = (*pos >> 23) & 1; 	if (*pos & (1ULL << 62)) {		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; 		if (se_bank == 0x3FF)			se_bank = 0xFFFFFFFF;		if (sh_bank == 0x3FF)			sh_bank = 0xFFFFFFFF;		if (instance_bank == 0x3FF)			instance_bank = 0xFFFFFFFF;		use_bank = true;	} else if (*pos & (1ULL << 61)) { 		me = (*pos & GENMASK_ULL(33, 24)) >> 24;		pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;		queue = (*pos & GENMASK_ULL(53, 44)) >> 44;		vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; 		use_ring = true;	} else {		use_bank = use_ring = false;	} 	*pos &= (1UL << 22) - 1; 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	r = amdgpu_virt_enable_access_debugfs(adev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	if (use_bank) {		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {			pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);			pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);			amdgpu_virt_disable_access_debugfs(adev);			return -EINVAL;		}		mutex_lock(&adev->grbm_idx_mutex);		amdgpu_gfx_select_se_sh(adev, se_bank,					sh_bank, instance_bank);	} else if (use_ring) {		mutex_lock(&adev->srbm_mutex);		amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);	} 	if (pm_pg_lock)		mutex_lock(&adev->pm.mutex); 	while (size) {		uint32_t value; 		if (read) {			value = RREG32(*pos >> 2);			r = put_user(value, (uint32_t *)buf);		} else {			r = get_user(value, (uint32_t *)buf);			if (!r)				amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);		}		if (r) {			result = r;			goto end;		} 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} end:	if (use_bank) {		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);		mutex_unlock(&adev->grbm_idx_mutex);	} else if (use_ring) {		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);		mutex_unlock(&adev->srbm_mutex);	} 	if (pm_pg_lock)		mutex_unlock(&adev->pm.mutex); 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 	amdgpu_virt_disable_access_debugfs(adev);	return result;} /* * amdgpu_debugfs_regs_read - Callback for reading MMIO registers */static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);} /* * amdgpu_debugfs_regs_write - Callback for writing MMIO registers */static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,					 size_t size, loff_t *pos){	return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);} static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file){	struct amdgpu_debugfs_regs2_data *rd; 	rd = kzalloc(sizeof *rd, GFP_KERNEL);	if (!rd)		return -ENOMEM;	rd->adev = file_inode(file)->i_private;	file->private_data = rd;	mutex_init(&rd->lock); 	return 0;} static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file){	struct amdgpu_debugfs_regs2_data *rd = file->private_data;	mutex_destroy(&rd->lock);	kfree(file->private_data);	return 0;} static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en){	struct amdgpu_debugfs_regs2_data *rd = f->private_data;	struct amdgpu_device *adev = rd->adev;	ssize_t result = 0;	int r;	uint32_t value; 	if (size & 0x3 || offset & 0x3)		return -EINVAL; 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	r = amdgpu_virt_enable_access_debugfs(adev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	mutex_lock(&rd->lock); 	if (rd->id.use_grbm) {		if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||		    (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {			pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);			pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);			amdgpu_virt_disable_access_debugfs(adev);			mutex_unlock(&rd->lock);			return -EINVAL;		}		mutex_lock(&adev->grbm_idx_mutex);		amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,								rd->id.grbm.sh,								rd->id.grbm.instance);	} 	if (rd->id.use_srbm) {		mutex_lock(&adev->srbm_mutex);		amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,									rd->id.srbm.queue, rd->id.srbm.vmid);	} 	if (rd->id.pg_lock)		mutex_lock(&adev->pm.mutex); 	while (size) {		if (!write_en) {			value = RREG32(offset >> 2);			r = put_user(value, (uint32_t *)buf);		} else {			r = get_user(value, (uint32_t *)buf);			if (!r)				amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value);		}		if (r) {			result = r;			goto end;		}		offset += 4;		size -= 4;		result += 4;		buf += 4;	}end:	if (rd->id.use_grbm) {		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);		mutex_unlock(&adev->grbm_idx_mutex);	} 	if (rd->id.use_srbm) {		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);		mutex_unlock(&adev->srbm_mutex);	} 	if (rd->id.pg_lock)		mutex_unlock(&adev->pm.mutex); 	mutex_unlock(&rd->lock); 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 	amdgpu_virt_disable_access_debugfs(adev);	return result;} static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data){	struct amdgpu_debugfs_regs2_data *rd = f->private_data;	int r; 	switch (cmd) {	case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:		mutex_lock(&rd->lock);		r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata *)data, sizeof rd->id);		mutex_unlock(&rd->lock);		return r ? -EINVAL : 0;	default:		return -EINVAL;	}	return 0;} static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos){	return amdgpu_debugfs_regs2_op(f, buf, *pos, size, 0);} static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf, size_t size, loff_t *pos){	return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);}  /** * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register * * @f: open file handle * @buf: User buffer to store read data in * @size: Number of bytes to read * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	r = amdgpu_virt_enable_access_debugfs(adev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	while (size) {		uint32_t value; 		value = RREG32_PCIE(*pos);		r = put_user(value, (uint32_t *)buf);		if (r) {			pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);			pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);			amdgpu_virt_disable_access_debugfs(adev);			return r;		} 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 	amdgpu_virt_disable_access_debugfs(adev);	return result;} /** * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register * * @f: open file handle * @buf: User buffer to write data from * @size: Number of bytes to write * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to write.  This * allows writing multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,					 size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	r = amdgpu_virt_enable_access_debugfs(adev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	while (size) {		uint32_t value; 		r = get_user(value, (uint32_t *)buf);		if (r) {			pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);			pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);			amdgpu_virt_disable_access_debugfs(adev);			return r;		} 		WREG32_PCIE(*pos, value); 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 	amdgpu_virt_disable_access_debugfs(adev);	return result;} /** * amdgpu_debugfs_regs_didt_read - Read from a DIDT register * * @f: open file handle * @buf: User buffer to store read data in * @size: Number of bytes to read * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	r = amdgpu_virt_enable_access_debugfs(adev);	if (r < 0) {		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);		return r;	} 	while (size) {

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