/* * Handle unaligned accesses by emulation. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2014 Imagination Technologies Ltd. * * This file contains exception handler for address error exception with the * special capability to execute faulting instructions in software. The * handler does not try to handle the case when the program counter points * to an address not aligned to a word boundary. * * Putting data to unaligned addresses is a bad practice even on Intel where * only the performance is affected. Much worse is that such code is non- * portable. Due to several programs that die on MIPS due to alignment * problems I decided to implement this handler anyway though I originally * didn't intend to do this at all for user code. * * For now I enable fixing of address errors by default to make life easier. * I however intend to disable this somewhen in the future when the alignment * problems with user programs have been fixed. For programmers this is the * right way to go. * * Fixing address errors is a per process option. The option is inherited * across fork(2) and execve(2) calls. If you really want to use the * option in your user programs - I discourage the use of the software * emulation strongly - use the following code in your userland stuff: * * #include <sys/sysmips.h> * * ... * sysmips(MIPS_FIXADE, x); * ... * * The argument x is 0 for disabling software emulation, enabled otherwise. * * Below a little program to play around with this feature. * * #include <stdio.h> * #include <sys/sysmips.h> * * struct foo { * unsigned char bar[8]; * }; * * main(int argc, char *argv[]) * { * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7}; * unsigned int *p = (unsigned int *) (x.bar + 3); * int i; * * if (argc > 1) * sysmips(MIPS_FIXADE, atoi(argv[1])); * * printf("*p = %08lx\n", *p); * * *p = 0xdeadface; * * for(i = 0; i <= 7; i++) * printf("%02x ", x.bar[i]); * printf("\n"); * } * * Coprocessor loads are not supported; I think this case is unimportant * in the practice. * * TODO: Handle ndc (attempted store to doubleword in uncached memory) * exception for the R6000. * A store crossing a page boundary might be executed only partially. * Undo the partial store in this case. */#include <linux/context_tracking.h>#include <linux/mm.h>#include <linux/signal.h>#include <linux/smp.h>#include <linux/sched.h>#include <linux/debugfs.h>#include <linux/perf_event.h> #include <asm/asm.h>#include <asm/branch.h>#include <asm/byteorder.h>#include <asm/cop2.h>#include <asm/debug.h>#include <asm/fpu.h>#include <asm/fpu_emulator.h>#include <asm/inst.h>#include <asm/mmu_context.h>#include <linux/uaccess.h> #define STR(x) __STR(x)#define __STR(x) #x enum { UNALIGNED_ACTION_QUIET, UNALIGNED_ACTION_SIGNAL, UNALIGNED_ACTION_SHOW,};#ifdef CONFIG_DEBUG_FSstatic u32 unaligned_instructions;static u32 unaligned_action;#else#define unaligned_action UNALIGNED_ACTION_QUIET#endifextern void show_registers(struct pt_regs *regs); #ifdef __BIG_ENDIAN#define _LoadHW(addr, value, res, type) \do { \ __asm__ __volatile__ (".set\tnoat\n" \ "1:\t"type##_lb("%0", "0(%2)")"\n" \ "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ "3:\t.set\tat\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR#define _LoadW(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ "1:\t"type##_lwl("%0", "(%2)")"\n" \ "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR *//* For CPUs without lwl instruction */#define _LoadW(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ ".set\tpush\n" \ ".set\tnoat\n\t" \ "1:"type##_lb("%0", "0(%2)")"\n\t" \ "2:"type##_lbu("$1", "1(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "3:"type##_lbu("$1", "2(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "4:"type##_lbu("$1", "3(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ ".set\tpop\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%1, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #define _LoadHWU(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ "1:\t"type##_lbu("%0", "0(%2)")"\n" \ "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".set\tat\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR#define _LoadWU(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ "1:\t"type##_lwl("%0", "(%2)")"\n" \ "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ "dsll\t%0, %0, 32\n\t" \ "dsrl\t%0, %0, 32\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ "\t.section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #define _LoadDW(addr, value, res) \do { \ __asm__ __volatile__ ( \ "1:\tldl\t%0, (%2)\n" \ "2:\tldr\t%0, 7(%2)\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ "\t.section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR *//* For CPUs without lwl and ldl instructions */#define _LoadWU(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:"type##_lbu("%0", "0(%2)")"\n\t" \ "2:"type##_lbu("$1", "1(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "3:"type##_lbu("$1", "2(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "4:"type##_lbu("$1", "3(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ ".set\tpop\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%1, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #define _LoadDW(addr, value, res) \do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:lb\t%0, 0(%2)\n\t" \ "2:lbu\t $1, 1(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "3:lbu\t$1, 2(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "4:lbu\t$1, 3(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "5:lbu\t$1, 4(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "6:lbu\t$1, 5(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "7:lbu\t$1, 6(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "8:lbu\t$1, 7(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ ".set\tpop\n\t" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%1, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ STR(PTR)"\t5b, 11b\n\t" \ STR(PTR)"\t6b, 11b\n\t" \ STR(PTR)"\t7b, 11b\n\t" \ STR(PTR)"\t8b, 11b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \} while(0) #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #define _StoreHW(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ "1:\t"type##_sb("%1", "1(%2)")"\n" \ "srl\t$1, %1, 0x8\n" \ "2:\t"type##_sb("$1", "0(%2)")"\n" \ ".set\tat\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%0, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT));\} while(0) #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR#define _StoreW(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ "1:\t"type##_swl("%1", "(%2)")"\n" \ "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%0, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT)); \} while(0) #define _StoreDW(addr, value, res) \do { \ __asm__ __volatile__ ( \ "1:\tsdl\t%1,(%2)\n" \ "2:\tsdr\t%1, 7(%2)\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%0, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT)); \} while(0) #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */#define _StoreW(addr, value, res, type) \do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:"type##_sb("%1", "3(%2)")"\n\t" \ "srl\t$1, %1, 0x8\n\t" \ "2:"type##_sb("$1", "2(%2)")"\n\t" \ "srl\t$1, $1, 0x8\n\t" \ "3:"type##_sb("$1", "1(%2)")"\n\t" \ "srl\t$1, $1, 0x8\n\t" \ "4:"type##_sb("$1", "0(%2)")"\n\t" \ ".set\tpop\n\t" \ "li\t%0, 0\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%0, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ ".previous" \ : "=&r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT) \ : "memory"); \} while(0) #define _StoreDW(addr, value, res) \do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:sb\t%1, 7(%2)\n\t" \ "dsrl\t$1, %1, 0x8\n\t" \ "2:sb\t$1, 6(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "3:sb\t$1, 5(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "4:sb\t$1, 4(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "5:sb\t$1, 3(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "6:sb\t$1, 2(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "7:sb\t$1, 1(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "8:sb\t$1, 0(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ ".set\tpop\n\t" \ "li\t%0, 0\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%0, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ STR(PTR)"\t5b, 11b\n\t" \ STR(PTR)"\t6b, 11b\n\t" \ STR(PTR)"\t7b, 11b\n\t" \ STR(PTR)"\t8b, 11b\n\t" \ ".previous" \ : "=&r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT) \ : "memory"); \} while(0) #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #else /* __BIG_ENDIAN */ #define _LoadHW(addr, value, res, type) \do { \ __asm__ __volatile__ (".set\tnoat\n" \ "1:\t"type##_lb("%0", "1(%2)")"\n" \ "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ "3:\t.set\tat\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \Lines 1–500 of 2385. Load more
/* * Handle unaligned accesses by emulation. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. * Copyright (C) 2014 Imagination Technologies Ltd. * * This file contains exception handler for address error exception with the * special capability to execute faulting instructions in software. The * handler does not try to handle the case when the program counter points * to an address not aligned to a word boundary. * * Putting data to unaligned addresses is a bad practice even on Intel where * only the performance is affected. Much worse is that such code is non- * portable. Due to several programs that die on MIPS due to alignment * problems I decided to implement this handler anyway though I originally * didn't intend to do this at all for user code. * * For now I enable fixing of address errors by default to make life easier. * I however intend to disable this somewhen in the future when the alignment * problems with user programs have been fixed. For programmers this is the * right way to go. * * Fixing address errors is a per process option. The option is inherited * across fork(2) and execve(2) calls. If you really want to use the * option in your user programs - I discourage the use of the software * emulation strongly - use the following code in your userland stuff: * * #include <sys/sysmips.h> * * ... * sysmips(MIPS_FIXADE, x); * ... * * The argument x is 0 for disabling software emulation, enabled otherwise. * * Below a little program to play around with this feature. * * #include <stdio.h> * #include <sys/sysmips.h> * * struct foo { * unsigned char bar[8]; * }; * * main(int argc, char *argv[]) * { * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7}; * unsigned int *p = (unsigned int *) (x.bar + 3); * int i; * * if (argc > 1) * sysmips(MIPS_FIXADE, atoi(argv[1])); * * printf("*p = %08lx\n", *p); * * *p = 0xdeadface; * * for(i = 0; i <= 7; i++) * printf("%02x ", x.bar[i]); * printf("\n"); * } * * Coprocessor loads are not supported; I think this case is unimportant * in the practice. * * TODO: Handle ndc (attempted store to doubleword in uncached memory) * exception for the R6000. * A store crossing a page boundary might be executed only partially. * Undo the partial store in this case. */ #include <linux/context_tracking.h> #include <linux/mm.h> #include <linux/signal.h> #include <linux/smp.h> #include <linux/sched.h> #include <linux/debugfs.h> #include <linux/perf_event.h> #include <asm/asm.h> #include <asm/branch.h> #include <asm/byteorder.h> #include <asm/cop2.h> #include <asm/debug.h> #include <asm/fpu.h> #include <asm/fpu_emulator.h> #include <asm/inst.h> #include <asm/mmu_context.h> #include <linux/uaccess.h> #define STR(x) __STR(x) #define __STR(x) #x enum { UNALIGNED_ACTION_QUIET, UNALIGNED_ACTION_SIGNAL, UNALIGNED_ACTION_SHOW, }; #ifdef CONFIG_DEBUG_FS static u32 unaligned_instructions; static u32 unaligned_action; #else #define unaligned_action UNALIGNED_ACTION_QUIET #endif extern void show_registers(struct pt_regs *regs); #ifdef __BIG_ENDIAN #define _LoadHW(addr, value, res, type) \ do { \ __asm__ __volatile__ (".set\tnoat\n" \ "1:\t"type##_lb("%0", "0(%2)")"\n" \ "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ "3:\t.set\tat\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR #define _LoadW(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ "1:\t"type##_lwl("%0", "(%2)")"\n" \ "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ /* For CPUs without lwl instruction */ #define _LoadW(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ ".set\tpush\n" \ ".set\tnoat\n\t" \ "1:"type##_lb("%0", "0(%2)")"\n\t" \ "2:"type##_lbu("$1", "1(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "3:"type##_lbu("$1", "2(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "4:"type##_lbu("$1", "3(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ ".set\tpop\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%1, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #define _LoadHWU(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ "1:\t"type##_lbu("%0", "0(%2)")"\n" \ "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".set\tat\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR #define _LoadWU(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ "1:\t"type##_lwl("%0", "(%2)")"\n" \ "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ "dsll\t%0, %0, 32\n\t" \ "dsrl\t%0, %0, 32\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ "\t.section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #define _LoadDW(addr, value, res) \ do { \ __asm__ __volatile__ ( \ "1:\tldl\t%0, (%2)\n" \ "2:\tldr\t%0, 7(%2)\n\t" \ "li\t%1, 0\n" \ "3:\n\t" \ ".insn\n\t" \ "\t.section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%1, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ /* For CPUs without lwl and ldl instructions */ #define _LoadWU(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:"type##_lbu("%0", "0(%2)")"\n\t" \ "2:"type##_lbu("$1", "1(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "3:"type##_lbu("$1", "2(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "4:"type##_lbu("$1", "3(%2)")"\n\t" \ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ ".set\tpop\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%1, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #define _LoadDW(addr, value, res) \ do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:lb\t%0, 0(%2)\n\t" \ "2:lbu\t $1, 1(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "3:lbu\t$1, 2(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "4:lbu\t$1, 3(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "5:lbu\t$1, 4(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "6:lbu\t$1, 5(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "7:lbu\t$1, 6(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "8:lbu\t$1, 7(%2)\n\t" \ "dsll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ ".set\tpop\n\t" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%1, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ STR(PTR)"\t5b, 11b\n\t" \ STR(PTR)"\t6b, 11b\n\t" \ STR(PTR)"\t7b, 11b\n\t" \ STR(PTR)"\t8b, 11b\n\t" \ ".previous" \ : "=&r" (value), "=r" (res) \ : "r" (addr), "i" (-EFAULT)); \ } while(0) #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #define _StoreHW(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ ".set\tnoat\n" \ "1:\t"type##_sb("%1", "1(%2)")"\n" \ "srl\t$1, %1, 0x8\n" \ "2:\t"type##_sb("$1", "0(%2)")"\n" \ ".set\tat\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%0, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT));\ } while(0) #ifdef CONFIG_CPU_HAS_LOAD_STORE_LR #define _StoreW(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ "1:\t"type##_swl("%1", "(%2)")"\n" \ "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%0, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT)); \ } while(0) #define _StoreDW(addr, value, res) \ do { \ __asm__ __volatile__ ( \ "1:\tsdl\t%1,(%2)\n" \ "2:\tsdr\t%1, 7(%2)\n\t" \ "li\t%0, 0\n" \ "3:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "4:\tli\t%0, %3\n\t" \ "j\t3b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 4b\n\t" \ STR(PTR)"\t2b, 4b\n\t" \ ".previous" \ : "=r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT)); \ } while(0) #else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #define _StoreW(addr, value, res, type) \ do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:"type##_sb("%1", "3(%2)")"\n\t" \ "srl\t$1, %1, 0x8\n\t" \ "2:"type##_sb("$1", "2(%2)")"\n\t" \ "srl\t$1, $1, 0x8\n\t" \ "3:"type##_sb("$1", "1(%2)")"\n\t" \ "srl\t$1, $1, 0x8\n\t" \ "4:"type##_sb("$1", "0(%2)")"\n\t" \ ".set\tpop\n\t" \ "li\t%0, 0\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%0, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ ".previous" \ : "=&r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT) \ : "memory"); \ } while(0) #define _StoreDW(addr, value, res) \ do { \ __asm__ __volatile__ ( \ ".set\tpush\n\t" \ ".set\tnoat\n\t" \ "1:sb\t%1, 7(%2)\n\t" \ "dsrl\t$1, %1, 0x8\n\t" \ "2:sb\t$1, 6(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "3:sb\t$1, 5(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "4:sb\t$1, 4(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "5:sb\t$1, 3(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "6:sb\t$1, 2(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "7:sb\t$1, 1(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ "8:sb\t$1, 0(%2)\n\t" \ "dsrl\t$1, $1, 0x8\n\t" \ ".set\tpop\n\t" \ "li\t%0, 0\n" \ "10:\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \ "11:\tli\t%0, %3\n\t" \ "j\t10b\n\t" \ ".previous\n\t" \ ".section\t__ex_table,\"a\"\n\t" \ STR(PTR)"\t1b, 11b\n\t" \ STR(PTR)"\t2b, 11b\n\t" \ STR(PTR)"\t3b, 11b\n\t" \ STR(PTR)"\t4b, 11b\n\t" \ STR(PTR)"\t5b, 11b\n\t" \ STR(PTR)"\t6b, 11b\n\t" \ STR(PTR)"\t7b, 11b\n\t" \ STR(PTR)"\t8b, 11b\n\t" \ ".previous" \ : "=&r" (res) \ : "r" (value), "r" (addr), "i" (-EFAULT) \ : "memory"); \ } while(0) #endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */ #else /* __BIG_ENDIAN */ #define _LoadHW(addr, value, res, type) \ do { \ __asm__ __volatile__ (".set\tnoat\n" \ "1:\t"type##_lb("%0", "1(%2)")"\n" \ "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ "sll\t%0, 0x8\n\t" \ "or\t%0, $1\n\t" \ "li\t%1, 0\n" \ "3:\t.set\tat\n\t" \ ".insn\n\t" \ ".section\t.fixup,\"ax\"\n\t" \