// SPDX-License-Identifier: GPL-2.0-only/* * Resource Director Technology(RDT) * - Cache Allocation code. * * Copyright (C) 2016 Intel Corporation * * Authors: *    Fenghua Yu <fenghua.yu@intel.com> *    Tony Luck <tony.luck@intel.com> *    Vikas Shivappa <vikas.shivappa@intel.com> * * More information about RDT be found in the Intel (R) x86 Architecture * Software Developer Manual June 2016, volume 3, section 17.17. */ #define pr_fmt(fmt)	"resctrl: " fmt #include <linux/slab.h>#include <linux/err.h>#include <linux/cacheinfo.h>#include <linux/cpuhotplug.h> #include <asm/intel-family.h>#include <asm/resctrl_sched.h>#include "internal.h" /* Mutex to protect rdtgroup access. */DEFINE_MUTEX(rdtgroup_mutex); /* * The cached resctrl_pqr_state is strictly per CPU and can never be * updated from a remote CPU. Functions which modify the state * are called with interrupts disabled and no preemption, which * is sufficient for the protection. */DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); /* * Used to store the max resource name width and max resource data width * to display the schemata in a tabular format */int max_name_width, max_data_width; /* * Global boolean for rdt_alloc which is true if any * resource allocation is enabled. */bool rdt_alloc_capable; static voidmba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,		struct rdt_resource *r);static voidcat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r);static voidmba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m,	      struct rdt_resource *r); #define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains) struct rdt_resource rdt_resources_all[] = {	[RDT_RESOURCE_L3] =	{		.rid			= RDT_RESOURCE_L3,		.name			= "L3",		.domains		= domain_init(RDT_RESOURCE_L3),		.msr_base		= MSR_IA32_L3_CBM_BASE,		.msr_update		= cat_wrmsr,		.cache_level		= 3,		.cache = {			.min_cbm_bits	= 1,			.cbm_idx_mult	= 1,			.cbm_idx_offset	= 0,		},		.parse_ctrlval		= parse_cbm,		.format_str		= "%d=%0*x",		.fflags			= RFTYPE_RES_CACHE,	},	[RDT_RESOURCE_L3DATA] =	{		.rid			= RDT_RESOURCE_L3DATA,		.name			= "L3DATA",		.domains		= domain_init(RDT_RESOURCE_L3DATA),		.msr_base		= MSR_IA32_L3_CBM_BASE,		.msr_update		= cat_wrmsr,		.cache_level		= 3,		.cache = {			.min_cbm_bits	= 1,			.cbm_idx_mult	= 2,			.cbm_idx_offset	= 0,		},		.parse_ctrlval		= parse_cbm,		.format_str		= "%d=%0*x",		.fflags			= RFTYPE_RES_CACHE,	},	[RDT_RESOURCE_L3CODE] =	{		.rid			= RDT_RESOURCE_L3CODE,		.name			= "L3CODE",		.domains		= domain_init(RDT_RESOURCE_L3CODE),		.msr_base		= MSR_IA32_L3_CBM_BASE,		.msr_update		= cat_wrmsr,		.cache_level		= 3,		.cache = {			.min_cbm_bits	= 1,			.cbm_idx_mult	= 2,			.cbm_idx_offset	= 1,		},		.parse_ctrlval		= parse_cbm,		.format_str		= "%d=%0*x",		.fflags			= RFTYPE_RES_CACHE,	},	[RDT_RESOURCE_L2] =	{		.rid			= RDT_RESOURCE_L2,		.name			= "L2",		.domains		= domain_init(RDT_RESOURCE_L2),		.msr_base		= MSR_IA32_L2_CBM_BASE,		.msr_update		= cat_wrmsr,		.cache_level		= 2,		.cache = {			.min_cbm_bits	= 1,			.cbm_idx_mult	= 1,			.cbm_idx_offset	= 0,		},		.parse_ctrlval		= parse_cbm,		.format_str		= "%d=%0*x",		.fflags			= RFTYPE_RES_CACHE,	},	[RDT_RESOURCE_L2DATA] =	{		.rid			= RDT_RESOURCE_L2DATA,		.name			= "L2DATA",		.domains		= domain_init(RDT_RESOURCE_L2DATA),		.msr_base		= MSR_IA32_L2_CBM_BASE,		.msr_update		= cat_wrmsr,		.cache_level		= 2,		.cache = {			.min_cbm_bits	= 1,			.cbm_idx_mult	= 2,			.cbm_idx_offset	= 0,		},		.parse_ctrlval		= parse_cbm,		.format_str		= "%d=%0*x",		.fflags			= RFTYPE_RES_CACHE,	},	[RDT_RESOURCE_L2CODE] =	{		.rid			= RDT_RESOURCE_L2CODE,		.name			= "L2CODE",		.domains		= domain_init(RDT_RESOURCE_L2CODE),		.msr_base		= MSR_IA32_L2_CBM_BASE,		.msr_update		= cat_wrmsr,		.cache_level		= 2,		.cache = {			.min_cbm_bits	= 1,			.cbm_idx_mult	= 2,			.cbm_idx_offset	= 1,		},		.parse_ctrlval		= parse_cbm,		.format_str		= "%d=%0*x",		.fflags			= RFTYPE_RES_CACHE,	},	[RDT_RESOURCE_MBA] =	{		.rid			= RDT_RESOURCE_MBA,		.name			= "MB",		.domains		= domain_init(RDT_RESOURCE_MBA),		.cache_level		= 3,		.format_str		= "%d=%*u",		.fflags			= RFTYPE_RES_MB,	},}; static unsigned int cbm_idx(struct rdt_resource *r, unsigned int closid){	return closid * r->cache.cbm_idx_mult + r->cache.cbm_idx_offset;} /* * cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs * as they do not have CPUID enumeration support for Cache allocation. * The check for Vendor/Family/Model is not enough to guarantee that * the MSRs won't #GP fault because only the following SKUs support * CAT: *	Intel(R) Xeon(R)  CPU E5-2658  v3  @  2.20GHz *	Intel(R) Xeon(R)  CPU E5-2648L v3  @  1.80GHz *	Intel(R) Xeon(R)  CPU E5-2628L v3  @  2.00GHz *	Intel(R) Xeon(R)  CPU E5-2618L v3  @  2.30GHz *	Intel(R) Xeon(R)  CPU E5-2608L v3  @  2.00GHz *	Intel(R) Xeon(R)  CPU E5-2658A v3  @  2.20GHz * * Probe by trying to write the first of the L3 cach mask registers * and checking that the bits stick. Max CLOSids is always 4 and max cbm length * is always 20 on hsw server parts. The minimum cache bitmask length * allowed for HSW server is always 2 bits. Hardcode all of them. */static inline void cache_alloc_hsw_probe(void){	struct rdt_resource *r  = &rdt_resources_all[RDT_RESOURCE_L3];	u32 l, h, max_cbm = BIT_MASK(20) - 1; 	if (wrmsr_safe(MSR_IA32_L3_CBM_BASE, max_cbm, 0))		return; 	rdmsr(MSR_IA32_L3_CBM_BASE, l, h); 	/* If all the bits were set in MSR, return success */	if (l != max_cbm)		return; 	r->num_closid = 4;	r->default_ctrl = max_cbm;	r->cache.cbm_len = 20;	r->cache.shareable_bits = 0xc0000;	r->cache.min_cbm_bits = 2;	r->alloc_capable = true;	r->alloc_enabled = true; 	rdt_alloc_capable = true;} bool is_mba_sc(struct rdt_resource *r){	if (!r)		return rdt_resources_all[RDT_RESOURCE_MBA].membw.mba_sc; 	return r->membw.mba_sc;} /* * rdt_get_mb_table() - get a mapping of bandwidth(b/w) percentage values * exposed to user interface and the h/w understandable delay values. * * The non-linear delay values have the granularity of power of two * and also the h/w does not guarantee a curve for configured delay * values vs. actual b/w enforced. * Hence we need a mapping that is pre calibrated so the user can * express the memory b/w as a percentage value. */static inline bool rdt_get_mb_table(struct rdt_resource *r){	/*	 * There are no Intel SKUs as of now to support non-linear delay.	 */	pr_info("MBA b/w map not implemented for cpu:%d, model:%d",		boot_cpu_data.x86, boot_cpu_data.x86_model); 	return false;} static bool __get_mem_config_intel(struct rdt_resource *r){	union cpuid_0x10_3_eax eax;	union cpuid_0x10_x_edx edx;	u32 ebx, ecx; 	cpuid_count(0x00000010, 3, &eax.full, &ebx, &ecx, &edx.full);	r->num_closid = edx.split.cos_max + 1;	r->membw.max_delay = eax.split.max_delay + 1;	r->default_ctrl = MAX_MBA_BW;	if (ecx & MBA_IS_LINEAR) {		r->membw.delay_linear = true;		r->membw.min_bw = MAX_MBA_BW - r->membw.max_delay;		r->membw.bw_gran = MAX_MBA_BW - r->membw.max_delay;	} else {		if (!rdt_get_mb_table(r))			return false;	}	r->data_width = 3; 	r->alloc_capable = true;	r->alloc_enabled = true; 	return true;} static bool __rdt_get_mem_config_amd(struct rdt_resource *r){	union cpuid_0x10_3_eax eax;	union cpuid_0x10_x_edx edx;	u32 ebx, ecx; 	cpuid_count(0x80000020, 1, &eax.full, &ebx, &ecx, &edx.full);	r->num_closid = edx.split.cos_max + 1;	r->default_ctrl = MAX_MBA_BW_AMD; 	/* AMD does not use delay */	r->membw.delay_linear = false; 	r->membw.min_bw = 0;	r->membw.bw_gran = 1;	/* Max value is 2048, Data width should be 4 in decimal */	r->data_width = 4; 	r->alloc_capable = true;	r->alloc_enabled = true; 	return true;} static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r){	union cpuid_0x10_1_eax eax;	union cpuid_0x10_x_edx edx;	u32 ebx, ecx; 	cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);	r->num_closid = edx.split.cos_max + 1;	r->cache.cbm_len = eax.split.cbm_len + 1;	r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;	r->cache.shareable_bits = ebx & r->default_ctrl;	r->data_width = (r->cache.cbm_len + 3) / 4;	r->alloc_capable = true;	r->alloc_enabled = true;} static void rdt_get_cdp_config(int level, int type){	struct rdt_resource *r_l = &rdt_resources_all[level];	struct rdt_resource *r = &rdt_resources_all[type]; 	r->num_closid = r_l->num_closid / 2;	r->cache.cbm_len = r_l->cache.cbm_len;	r->default_ctrl = r_l->default_ctrl;	r->cache.shareable_bits = r_l->cache.shareable_bits;	r->data_width = (r->cache.cbm_len + 3) / 4;	r->alloc_capable = true;	/*	 * By default, CDP is disabled. CDP can be enabled by mount parameter	 * "cdp" during resctrl file system mount time.	 */	r->alloc_enabled = false;} static void rdt_get_cdp_l3_config(void){	rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA);	rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE);} static void rdt_get_cdp_l2_config(void){	rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA);	rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);} static int get_cache_id(int cpu, int level){	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);	int i; 	for (i = 0; i < ci->num_leaves; i++) {		if (ci->info_list[i].level == level)			return ci->info_list[i].id;	} 	return -1;} static voidmba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r){	unsigned int i; 	for (i = m->low; i < m->high; i++)		wrmsrl(r->msr_base + i, d->ctrl_val[i]);} /* * Map the memory b/w percentage value to delay values * that can be written to QOS_MSRs. * There are currently no SKUs which support non linear delay values. */u32 delay_bw_map(unsigned long bw, struct rdt_resource *r){	if (r->membw.delay_linear)		return MAX_MBA_BW - bw; 	pr_warn_once("Non Linear delay-bw map not supported but queried\n");	return r->default_ctrl;} static voidmba_wrmsr_intel(struct rdt_domain *d, struct msr_param *m,		struct rdt_resource *r){	unsigned int i; 	/*  Write the delay values for mba. */	for (i = m->low; i < m->high; i++)		wrmsrl(r->msr_base + i, delay_bw_map(d->ctrl_val[i], r));} static voidcat_wrmsr(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r){	unsigned int i; 	for (i = m->low; i < m->high; i++)		wrmsrl(r->msr_base + cbm_idx(r, i), d->ctrl_val[i]);} struct rdt_domain *get_domain_from_cpu(int cpu, struct rdt_resource *r){	struct rdt_domain *d; 	list_for_each_entry(d, &r->domains, list) {		/* Find the domain that contains this CPU */		if (cpumask_test_cpu(cpu, &d->cpu_mask))			return d;	} 	return NULL;} void rdt_ctrl_update(void *arg){	struct msr_param *m = arg;	struct rdt_resource *r = m->res;	int cpu = smp_processor_id();	struct rdt_domain *d; 	d = get_domain_from_cpu(cpu, r);	if (d) {		r->msr_update(d, m, r);		return;	}	pr_warn_once("cpu %d not found in any domain for resource %s\n",		     cpu, r->name);} /* * rdt_find_domain - Find a domain in a resource that matches input resource id * * Search resource r's domain list to find the resource id. If the resource * id is found in a domain, return the domain. Otherwise, if requested by * caller, return the first domain whose id is bigger than the input id. * The domain list is sorted by id in ascending order. */struct rdt_domain *rdt_find_domain(struct rdt_resource *r, int id,				   struct list_head **pos){	struct rdt_domain *d;	struct list_head *l; 	if (id < 0)		return ERR_PTR(-ENODEV); 	list_for_each(l, &r->domains) {		d = list_entry(l, struct rdt_domain, list);		/* When id is found, return its domain. */		if (id == d->id)			return d;		/* Stop searching when finding id's position in sorted list. */		if (id < d->id)			break;	} 	if (pos)		*pos = l; 	return NULL;} void setup_default_ctrlval(struct rdt_resource *r, u32 *dc, u32 *dm){	int i; 	/*	 * Initialize the Control MSRs to having no control.	 * For Cache Allocation: Set all bits in cbm	 * For Memory Allocation: Set b/w requested to 100%	 * and the bandwidth in MBps to U32_MAX	 */	for (i = 0; i < r->num_closid; i++, dc++, dm++) {		*dc = r->default_ctrl;		*dm = MBA_MAX_MBPS;	}} static int domain_setup_ctrlval(struct rdt_resource *r, struct rdt_domain *d){	struct msr_param m;	u32 *dc, *dm; 	dc = kmalloc_array(r->num_closid, sizeof(*d->ctrl_val), GFP_KERNEL);	if (!dc)		return -ENOMEM; 	dm = kmalloc_array(r->num_closid, sizeof(*d->mbps_val), GFP_KERNEL);	if (!dm) {		kfree(dc);		return -ENOMEM;	} 	d->ctrl_val = dc;	d->mbps_val = dm;	setup_default_ctrlval(r, dc, dm);

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