/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */#include <drm/drmP.h>#include "amdgpu.h"#include <drm/amdgpu_drm.h>#include "amdgpu_sched.h"#include "amdgpu_uvd.h"#include "amdgpu_vce.h"#include "atom.h" #include <linux/vga_switcheroo.h>#include <linux/slab.h>#include <linux/pm_runtime.h>#include "amdgpu_amdkfd.h"#include "amdgpu_gem.h"#include "amdgpu_display.h"#include "amdgpu_ras.h" static void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev){ struct amdgpu_gpu_instance *gpu_instance; int i; mutex_lock(&mgpu_info.mutex); for (i = 0; i < mgpu_info.num_gpu; i++) { gpu_instance = &(mgpu_info.gpu_ins[i]); if (gpu_instance->adev == adev) { mgpu_info.gpu_ins[i] = mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; mgpu_info.num_gpu--; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu--; else mgpu_info.num_dgpu--; break; } } mutex_unlock(&mgpu_info.mutex);} /** * amdgpu_driver_unload_kms - Main unload function for KMS. * * @dev: drm dev pointer * * This is the main unload function for KMS (all asics). * Returns 0 on success. */void amdgpu_driver_unload_kms(struct drm_device *dev){ struct amdgpu_device *adev = dev->dev_private; if (adev == NULL) return; amdgpu_unregister_gpu_instance(adev); if (adev->rmmio == NULL) goto done_free; if (amdgpu_sriov_vf(adev)) amdgpu_virt_request_full_gpu(adev, false); if (amdgpu_device_is_px(dev)) { pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); } amdgpu_acpi_fini(adev); amdgpu_device_fini(adev); done_free: kfree(adev); dev->dev_private = NULL;} static void amdgpu_register_gpu_instance(struct amdgpu_device *adev){ struct amdgpu_gpu_instance *gpu_instance; mutex_lock(&mgpu_info.mutex); if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { DRM_ERROR("Cannot register more gpu instance\n"); mutex_unlock(&mgpu_info.mutex); return; } gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); gpu_instance->adev = adev; gpu_instance->mgpu_fan_enabled = 0; mgpu_info.num_gpu++; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu++; else mgpu_info.num_dgpu++; mutex_unlock(&mgpu_info.mutex);} /** * amdgpu_driver_load_kms - Main load function for KMS. * * @dev: drm dev pointer * @flags: device flags * * This is the main load function for KMS (all asics). * Returns 0 on success, error on failure. */int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags){ struct amdgpu_device *adev; int r, acpi_status; #ifdef CONFIG_DRM_AMDGPU_SI if (!amdgpu_si_support) { switch (flags & AMD_ASIC_MASK) { case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: dev_info(dev->dev, "SI support provided by radeon.\n"); dev_info(dev->dev, "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" ); return -ENODEV; } }#endif#ifdef CONFIG_DRM_AMDGPU_CIK if (!amdgpu_cik_support) { switch (flags & AMD_ASIC_MASK) { case CHIP_KAVERI: case CHIP_BONAIRE: case CHIP_HAWAII: case CHIP_KABINI: case CHIP_MULLINS: dev_info(dev->dev, "CIK support provided by radeon.\n"); dev_info(dev->dev, "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" ); return -ENODEV; } }#endif adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); if (adev == NULL) { return -ENOMEM; } dev->dev_private = (void *)adev; if ((amdgpu_runtime_pm != 0) && amdgpu_has_atpx() && (amdgpu_is_atpx_hybrid() || amdgpu_has_atpx_dgpu_power_cntl()) && ((flags & AMD_IS_APU) == 0) && !pci_is_thunderbolt_attached(dev->pdev)) flags |= AMD_IS_PX; /* amdgpu_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = amdgpu_device_init(adev, dev, dev->pdev, flags); if (r) { dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); goto out; } /* Call ACPI methods: require modeset init * but failure is not fatal */ if (!r) { acpi_status = amdgpu_acpi_init(adev); if (acpi_status) dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); } if (amdgpu_device_is_px(dev)) { dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); pm_runtime_set_active(dev->dev); pm_runtime_allow(dev->dev); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); } amdgpu_register_gpu_instance(adev);out: if (r) { /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ if (adev->rmmio && amdgpu_device_is_px(dev)) pm_runtime_put_noidle(dev->dev); amdgpu_driver_unload_kms(dev); } return r;} static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, struct drm_amdgpu_query_fw *query_fw, struct amdgpu_device *adev){ switch (query_fw->fw_type) { case AMDGPU_INFO_FW_VCE: fw_info->ver = adev->vce.fw_version; fw_info->feature = adev->vce.fb_version; break; case AMDGPU_INFO_FW_UVD: fw_info->ver = adev->uvd.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_VCN: fw_info->ver = adev->vcn.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GMC: fw_info->ver = adev->gmc.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GFX_ME: fw_info->ver = adev->gfx.me_fw_version; fw_info->feature = adev->gfx.me_feature_version; break; case AMDGPU_INFO_FW_GFX_PFP: fw_info->ver = adev->gfx.pfp_fw_version; fw_info->feature = adev->gfx.pfp_feature_version; break; case AMDGPU_INFO_FW_GFX_CE: fw_info->ver = adev->gfx.ce_fw_version; fw_info->feature = adev->gfx.ce_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC: fw_info->ver = adev->gfx.rlc_fw_version; fw_info->feature = adev->gfx.rlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: fw_info->ver = adev->gfx.rlc_srlc_fw_version; fw_info->feature = adev->gfx.rlc_srlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: fw_info->ver = adev->gfx.rlc_srlg_fw_version; fw_info->feature = adev->gfx.rlc_srlg_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: fw_info->ver = adev->gfx.rlc_srls_fw_version; fw_info->feature = adev->gfx.rlc_srls_feature_version; break; case AMDGPU_INFO_FW_GFX_MEC: if (query_fw->index == 0) { fw_info->ver = adev->gfx.mec_fw_version; fw_info->feature = adev->gfx.mec_feature_version; } else if (query_fw->index == 1) { fw_info->ver = adev->gfx.mec2_fw_version; fw_info->feature = adev->gfx.mec2_feature_version; } else return -EINVAL; break; case AMDGPU_INFO_FW_SMC: fw_info->ver = adev->pm.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_TA: if (query_fw->index > 1) return -EINVAL; if (query_fw->index == 0) { fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_xgmi_ucode_version; } else { fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_ras_ucode_version; } break; case AMDGPU_INFO_FW_SDMA: if (query_fw->index >= adev->sdma.num_instances) return -EINVAL; fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; break; case AMDGPU_INFO_FW_SOS: fw_info->ver = adev->psp.sos_fw_version; fw_info->feature = adev->psp.sos_feature_version; break; case AMDGPU_INFO_FW_ASD: fw_info->ver = adev->psp.asd_fw_version; fw_info->feature = adev->psp.asd_feature_version; break; case AMDGPU_INFO_FW_DMCU: fw_info->ver = adev->dm.dmcu_fw_version; fw_info->feature = 0; break; default: return -EINVAL; } return 0;} static int amdgpu_hw_ip_info(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_hw_ip *result){ uint32_t ib_start_alignment = 0; uint32_t ib_size_alignment = 0; enum amd_ip_block_type type; unsigned int num_rings = 0; unsigned int i, j; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) return -EINVAL; switch (info->query_hw_ip.type) { case AMDGPU_HW_IP_GFX: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_gfx_rings; i++) if (adev->gfx.gfx_ring[i].sched.ready) ++num_rings; ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_compute_rings; i++) if (adev->gfx.compute_ring[i].sched.ready) ++num_rings; ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; for (i = 0; i < adev->sdma.num_instances; i++) if (adev->sdma.instance[i].ring.sched.ready) ++num_rings; ib_start_alignment = 256; ib_size_alignment = 4; break; case AMDGPU_HW_IP_UVD: type = AMD_IP_BLOCK_TYPE_UVD; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) continue; if (adev->uvd.inst[i].ring.sched.ready) ++num_rings; } ib_start_alignment = 64; ib_size_alignment = 64; break; case AMDGPU_HW_IP_VCE: type = AMD_IP_BLOCK_TYPE_VCE; for (i = 0; i < adev->vce.num_rings; i++) if (adev->vce.ring[i].sched.ready) ++num_rings; ib_start_alignment = 4; ib_size_alignment = 1; break; case AMDGPU_HW_IP_UVD_ENC: type = AMD_IP_BLOCK_TYPE_UVD; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) continue; for (j = 0; j < adev->uvd.num_enc_rings; j++) if (adev->uvd.inst[i].ring_enc[j].sched.ready) ++num_rings; } ib_start_alignment = 64; ib_size_alignment = 64; break; case AMDGPU_HW_IP_VCN_DEC: type = AMD_IP_BLOCK_TYPE_VCN; if (adev->vcn.ring_dec.sched.ready) ++num_rings; ib_start_alignment = 16; ib_size_alignment = 16; break; case AMDGPU_HW_IP_VCN_ENC: type = AMD_IP_BLOCK_TYPE_VCN; for (i = 0; i < adev->vcn.num_enc_rings; i++) if (adev->vcn.ring_enc[i].sched.ready) ++num_rings; ib_start_alignment = 64; ib_size_alignment = 1; break; case AMDGPU_HW_IP_VCN_JPEG: type = AMD_IP_BLOCK_TYPE_VCN; if (adev->vcn.ring_jpeg.sched.ready) ++num_rings; ib_start_alignment = 16; ib_size_alignment = 16; break; default: return -EINVAL; } for (i = 0; i < adev->num_ip_blocks; i++) if (adev->ip_blocks[i].version->type == type && adev->ip_blocks[i].status.valid) break; if (i == adev->num_ip_blocks) return 0; num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], num_rings); result->hw_ip_version_major = adev->ip_blocks[i].version->major; result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; result->capabilities_flags = 0; result->available_rings = (1 << num_rings) - 1; result->ib_start_alignment = ib_start_alignment; result->ib_size_alignment = ib_size_alignment; return 0;} /* * Userspace get information ioctl *//** * amdgpu_info_ioctl - answer a device specific request. * * @adev: amdgpu device pointer * @data: request object * @filp: drm filp * * This function is used to pass device specific parameters to the userspace * drivers. Examples include: pci device id, pipeline parms, tiling params, * etc. (all asics). * Returns 0 on success, -EINVAL on failure. */static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp){ struct amdgpu_device *adev = dev->dev_private; struct drm_amdgpu_info *info = data; struct amdgpu_mode_info *minfo = &adev->mode_info; void __user *out = (void __user *)(uintptr_t)info->return_pointer; uint32_t size = info->return_size; struct drm_crtc *crtc; uint32_t ui32 = 0; uint64_t ui64 = 0; int i, found; int ui32_size = sizeof(ui32); if (!info->return_size || !info->return_pointer) return -EINVAL; switch (info->query) { case AMDGPU_INFO_ACCEL_WORKING: ui32 = adev->accel_working; return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; case AMDGPU_INFO_CRTC_FROM_ID: for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { crtc = (struct drm_crtc *)minfo->crtcs[i]; if (crtc && crtc->base.id == info->mode_crtc.id) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); ui32 = amdgpu_crtc->crtc_id; found = 1; break; } } if (!found) { DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); return -EINVAL; }Lines 1–500 of 1423. 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/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie * Alex Deucher * Jerome Glisse */ #include <drm/drmP.h> #include "amdgpu.h" #include <drm/amdgpu_drm.h> #include "amdgpu_sched.h" #include "amdgpu_uvd.h" #include "amdgpu_vce.h" #include "atom.h" #include <linux/vga_switcheroo.h> #include <linux/slab.h> #include <linux/pm_runtime.h> #include "amdgpu_amdkfd.h" #include "amdgpu_gem.h" #include "amdgpu_display.h" #include "amdgpu_ras.h" static void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) { struct amdgpu_gpu_instance *gpu_instance; int i; mutex_lock(&mgpu_info.mutex); for (i = 0; i < mgpu_info.num_gpu; i++) { gpu_instance = &(mgpu_info.gpu_ins[i]); if (gpu_instance->adev == adev) { mgpu_info.gpu_ins[i] = mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; mgpu_info.num_gpu--; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu--; else mgpu_info.num_dgpu--; break; } } mutex_unlock(&mgpu_info.mutex); } /** * amdgpu_driver_unload_kms - Main unload function for KMS. * * @dev: drm dev pointer * * This is the main unload function for KMS (all asics). * Returns 0 on success. */ void amdgpu_driver_unload_kms(struct drm_device *dev) { struct amdgpu_device *adev = dev->dev_private; if (adev == NULL) return; amdgpu_unregister_gpu_instance(adev); if (adev->rmmio == NULL) goto done_free; if (amdgpu_sriov_vf(adev)) amdgpu_virt_request_full_gpu(adev, false); if (amdgpu_device_is_px(dev)) { pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); } amdgpu_acpi_fini(adev); amdgpu_device_fini(adev); done_free: kfree(adev); dev->dev_private = NULL; } static void amdgpu_register_gpu_instance(struct amdgpu_device *adev) { struct amdgpu_gpu_instance *gpu_instance; mutex_lock(&mgpu_info.mutex); if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { DRM_ERROR("Cannot register more gpu instance\n"); mutex_unlock(&mgpu_info.mutex); return; } gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); gpu_instance->adev = adev; gpu_instance->mgpu_fan_enabled = 0; mgpu_info.num_gpu++; if (adev->flags & AMD_IS_APU) mgpu_info.num_apu++; else mgpu_info.num_dgpu++; mutex_unlock(&mgpu_info.mutex); } /** * amdgpu_driver_load_kms - Main load function for KMS. * * @dev: drm dev pointer * @flags: device flags * * This is the main load function for KMS (all asics). * Returns 0 on success, error on failure. */ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) { struct amdgpu_device *adev; int r, acpi_status; #ifdef CONFIG_DRM_AMDGPU_SI if (!amdgpu_si_support) { switch (flags & AMD_ASIC_MASK) { case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: case CHIP_HAINAN: dev_info(dev->dev, "SI support provided by radeon.\n"); dev_info(dev->dev, "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" ); return -ENODEV; } } #endif #ifdef CONFIG_DRM_AMDGPU_CIK if (!amdgpu_cik_support) { switch (flags & AMD_ASIC_MASK) { case CHIP_KAVERI: case CHIP_BONAIRE: case CHIP_HAWAII: case CHIP_KABINI: case CHIP_MULLINS: dev_info(dev->dev, "CIK support provided by radeon.\n"); dev_info(dev->dev, "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" ); return -ENODEV; } } #endif adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); if (adev == NULL) { return -ENOMEM; } dev->dev_private = (void *)adev; if ((amdgpu_runtime_pm != 0) && amdgpu_has_atpx() && (amdgpu_is_atpx_hybrid() || amdgpu_has_atpx_dgpu_power_cntl()) && ((flags & AMD_IS_APU) == 0) && !pci_is_thunderbolt_attached(dev->pdev)) flags |= AMD_IS_PX; /* amdgpu_device_init should report only fatal error * like memory allocation failure or iomapping failure, * or memory manager initialization failure, it must * properly initialize the GPU MC controller and permit * VRAM allocation */ r = amdgpu_device_init(adev, dev, dev->pdev, flags); if (r) { dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); goto out; } /* Call ACPI methods: require modeset init * but failure is not fatal */ if (!r) { acpi_status = amdgpu_acpi_init(adev); if (acpi_status) dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); } if (amdgpu_device_is_px(dev)) { dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP); pm_runtime_use_autosuspend(dev->dev); pm_runtime_set_autosuspend_delay(dev->dev, 5000); pm_runtime_set_active(dev->dev); pm_runtime_allow(dev->dev); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); } amdgpu_register_gpu_instance(adev); out: if (r) { /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ if (adev->rmmio && amdgpu_device_is_px(dev)) pm_runtime_put_noidle(dev->dev); amdgpu_driver_unload_kms(dev); } return r; } static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, struct drm_amdgpu_query_fw *query_fw, struct amdgpu_device *adev) { switch (query_fw->fw_type) { case AMDGPU_INFO_FW_VCE: fw_info->ver = adev->vce.fw_version; fw_info->feature = adev->vce.fb_version; break; case AMDGPU_INFO_FW_UVD: fw_info->ver = adev->uvd.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_VCN: fw_info->ver = adev->vcn.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GMC: fw_info->ver = adev->gmc.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_GFX_ME: fw_info->ver = adev->gfx.me_fw_version; fw_info->feature = adev->gfx.me_feature_version; break; case AMDGPU_INFO_FW_GFX_PFP: fw_info->ver = adev->gfx.pfp_fw_version; fw_info->feature = adev->gfx.pfp_feature_version; break; case AMDGPU_INFO_FW_GFX_CE: fw_info->ver = adev->gfx.ce_fw_version; fw_info->feature = adev->gfx.ce_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC: fw_info->ver = adev->gfx.rlc_fw_version; fw_info->feature = adev->gfx.rlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: fw_info->ver = adev->gfx.rlc_srlc_fw_version; fw_info->feature = adev->gfx.rlc_srlc_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: fw_info->ver = adev->gfx.rlc_srlg_fw_version; fw_info->feature = adev->gfx.rlc_srlg_feature_version; break; case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: fw_info->ver = adev->gfx.rlc_srls_fw_version; fw_info->feature = adev->gfx.rlc_srls_feature_version; break; case AMDGPU_INFO_FW_GFX_MEC: if (query_fw->index == 0) { fw_info->ver = adev->gfx.mec_fw_version; fw_info->feature = adev->gfx.mec_feature_version; } else if (query_fw->index == 1) { fw_info->ver = adev->gfx.mec2_fw_version; fw_info->feature = adev->gfx.mec2_feature_version; } else return -EINVAL; break; case AMDGPU_INFO_FW_SMC: fw_info->ver = adev->pm.fw_version; fw_info->feature = 0; break; case AMDGPU_INFO_FW_TA: if (query_fw->index > 1) return -EINVAL; if (query_fw->index == 0) { fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_xgmi_ucode_version; } else { fw_info->ver = adev->psp.ta_fw_version; fw_info->feature = adev->psp.ta_ras_ucode_version; } break; case AMDGPU_INFO_FW_SDMA: if (query_fw->index >= adev->sdma.num_instances) return -EINVAL; fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; break; case AMDGPU_INFO_FW_SOS: fw_info->ver = adev->psp.sos_fw_version; fw_info->feature = adev->psp.sos_feature_version; break; case AMDGPU_INFO_FW_ASD: fw_info->ver = adev->psp.asd_fw_version; fw_info->feature = adev->psp.asd_feature_version; break; case AMDGPU_INFO_FW_DMCU: fw_info->ver = adev->dm.dmcu_fw_version; fw_info->feature = 0; break; default: return -EINVAL; } return 0; } static int amdgpu_hw_ip_info(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_hw_ip *result) { uint32_t ib_start_alignment = 0; uint32_t ib_size_alignment = 0; enum amd_ip_block_type type; unsigned int num_rings = 0; unsigned int i, j; if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) return -EINVAL; switch (info->query_hw_ip.type) { case AMDGPU_HW_IP_GFX: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_gfx_rings; i++) if (adev->gfx.gfx_ring[i].sched.ready) ++num_rings; ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_COMPUTE: type = AMD_IP_BLOCK_TYPE_GFX; for (i = 0; i < adev->gfx.num_compute_rings; i++) if (adev->gfx.compute_ring[i].sched.ready) ++num_rings; ib_start_alignment = 32; ib_size_alignment = 32; break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; for (i = 0; i < adev->sdma.num_instances; i++) if (adev->sdma.instance[i].ring.sched.ready) ++num_rings; ib_start_alignment = 256; ib_size_alignment = 4; break; case AMDGPU_HW_IP_UVD: type = AMD_IP_BLOCK_TYPE_UVD; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) continue; if (adev->uvd.inst[i].ring.sched.ready) ++num_rings; } ib_start_alignment = 64; ib_size_alignment = 64; break; case AMDGPU_HW_IP_VCE: type = AMD_IP_BLOCK_TYPE_VCE; for (i = 0; i < adev->vce.num_rings; i++) if (adev->vce.ring[i].sched.ready) ++num_rings; ib_start_alignment = 4; ib_size_alignment = 1; break; case AMDGPU_HW_IP_UVD_ENC: type = AMD_IP_BLOCK_TYPE_UVD; for (i = 0; i < adev->uvd.num_uvd_inst; i++) { if (adev->uvd.harvest_config & (1 << i)) continue; for (j = 0; j < adev->uvd.num_enc_rings; j++) if (adev->uvd.inst[i].ring_enc[j].sched.ready) ++num_rings; } ib_start_alignment = 64; ib_size_alignment = 64; break; case AMDGPU_HW_IP_VCN_DEC: type = AMD_IP_BLOCK_TYPE_VCN; if (adev->vcn.ring_dec.sched.ready) ++num_rings; ib_start_alignment = 16; ib_size_alignment = 16; break; case AMDGPU_HW_IP_VCN_ENC: type = AMD_IP_BLOCK_TYPE_VCN; for (i = 0; i < adev->vcn.num_enc_rings; i++) if (adev->vcn.ring_enc[i].sched.ready) ++num_rings; ib_start_alignment = 64; ib_size_alignment = 1; break; case AMDGPU_HW_IP_VCN_JPEG: type = AMD_IP_BLOCK_TYPE_VCN; if (adev->vcn.ring_jpeg.sched.ready) ++num_rings; ib_start_alignment = 16; ib_size_alignment = 16; break; default: return -EINVAL; } for (i = 0; i < adev->num_ip_blocks; i++) if (adev->ip_blocks[i].version->type == type && adev->ip_blocks[i].status.valid) break; if (i == adev->num_ip_blocks) return 0; num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], num_rings); result->hw_ip_version_major = adev->ip_blocks[i].version->major; result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; result->capabilities_flags = 0; result->available_rings = (1 << num_rings) - 1; result->ib_start_alignment = ib_start_alignment; result->ib_size_alignment = ib_size_alignment; return 0; } /* * Userspace get information ioctl */ /** * amdgpu_info_ioctl - answer a device specific request. * * @adev: amdgpu device pointer * @data: request object * @filp: drm filp * * This function is used to pass device specific parameters to the userspace * drivers. Examples include: pci device id, pipeline parms, tiling params, * etc. (all asics). * Returns 0 on success, -EINVAL on failure. */ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; struct drm_amdgpu_info *info = data; struct amdgpu_mode_info *minfo = &adev->mode_info; void __user *out = (void __user *)(uintptr_t)info->return_pointer; uint32_t size = info->return_size; struct drm_crtc *crtc; uint32_t ui32 = 0; uint64_t ui64 = 0; int i, found; int ui32_size = sizeof(ui32); if (!info->return_size || !info->return_pointer) return -EINVAL; switch (info->query) { case AMDGPU_INFO_ACCEL_WORKING: ui32 = adev->accel_working; return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; case AMDGPU_INFO_CRTC_FROM_ID: for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { crtc = (struct drm_crtc *)minfo->crtcs[i]; if (crtc && crtc->base.id == info->mode_crtc.id) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); ui32 = amdgpu_crtc->crtc_id; found = 1; break; } } if (!found) { DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); return -EINVAL; }