/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#include <linux/dma-fence-array.h>#include <linux/interval_tree_generic.h>#include <linux/idr.h>#include <drm/drmP.h>#include <drm/amdgpu_drm.h>#include "amdgpu.h"#include "amdgpu_trace.h"#include "amdgpu_amdkfd.h"#include "amdgpu_gmc.h"#include "amdgpu_xgmi.h" /** * DOC: GPUVM * * GPUVM is similar to the legacy gart on older asics, however * rather than there being a single global gart table * for the entire GPU, there are multiple VM page tables active * at any given time.  The VM page tables can contain a mix * vram pages and system memory pages and system memory pages * can be mapped as snooped (cached system pages) or unsnooped * (uncached system pages). * Each VM has an ID associated with it and there is a page table * associated with each VMID.  When execting a command buffer, * the kernel tells the the ring what VMID to use for that command * buffer.  VMIDs are allocated dynamically as commands are submitted. * The userspace drivers maintain their own address space and the kernel * sets up their pages tables accordingly when they submit their * command buffers and a VMID is assigned. * Cayman/Trinity support up to 8 active VMs at any given time; * SI supports 16. */ #define START(node) ((node)->start)#define LAST(node) ((node)->last) INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,		     START, LAST, static, amdgpu_vm_it) #undef START#undef LAST /** * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback */struct amdgpu_prt_cb { 	/**	 * @adev: amdgpu device	 */	struct amdgpu_device *adev; 	/**	 * @cb: callback	 */	struct dma_fence_cb cb;}; /** * amdgpu_vm_level_shift - return the addr shift for each level * * @adev: amdgpu_device pointer * @level: VMPT level * * Returns: * The number of bits the pfn needs to be right shifted for a level. */static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,				      unsigned level){	unsigned shift = 0xff; 	switch (level) {	case AMDGPU_VM_PDB2:	case AMDGPU_VM_PDB1:	case AMDGPU_VM_PDB0:		shift = 9 * (AMDGPU_VM_PDB0 - level) +			adev->vm_manager.block_size;		break;	case AMDGPU_VM_PTB:		shift = 0;		break;	default:		dev_err(adev->dev, "the level%d isn't supported.\n", level);	} 	return shift;} /** * amdgpu_vm_num_entries - return the number of entries in a PD/PT * * @adev: amdgpu_device pointer * @level: VMPT level * * Returns: * The number of entries in a page directory or page table. */static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,				      unsigned level){	unsigned shift = amdgpu_vm_level_shift(adev,					       adev->vm_manager.root_level); 	if (level == adev->vm_manager.root_level)		/* For the root directory */		return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;	else if (level != AMDGPU_VM_PTB)		/* Everything in between */		return 512;	else		/* For the page tables on the leaves */		return AMDGPU_VM_PTE_COUNT(adev);} /** * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD * * @adev: amdgpu_device pointer * * Returns: * The number of entries in the root page directory which needs the ATS setting. */static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev){	unsigned shift; 	shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);	return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);} /** * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT * * @adev: amdgpu_device pointer * @level: VMPT level * * Returns: * The mask to extract the entry number of a PD/PT from an address. */static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,				       unsigned int level){	if (level <= adev->vm_manager.root_level)		return 0xffffffff;	else if (level != AMDGPU_VM_PTB)		return 0x1ff;	else		return AMDGPU_VM_PTE_COUNT(adev) - 1;} /** * amdgpu_vm_bo_size - returns the size of the BOs in bytes * * @adev: amdgpu_device pointer * @level: VMPT level * * Returns: * The size of the BO for a page directory or page table in bytes. */static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level){	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);} /** * amdgpu_vm_bo_evicted - vm_bo is evicted * * @vm_bo: vm_bo which is evicted * * State for PDs/PTs and per VM BOs which are not at the location they should * be. */static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo){	struct amdgpu_vm *vm = vm_bo->vm;	struct amdgpu_bo *bo = vm_bo->bo; 	vm_bo->moved = true;	if (bo->tbo.type == ttm_bo_type_kernel)		list_move(&vm_bo->vm_status, &vm->evicted);	else		list_move_tail(&vm_bo->vm_status, &vm->evicted);} /** * amdgpu_vm_bo_relocated - vm_bo is reloacted * * @vm_bo: vm_bo which is relocated * * State for PDs/PTs which needs to update their parent PD. */static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo){	list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);} /** * amdgpu_vm_bo_moved - vm_bo is moved * * @vm_bo: vm_bo which is moved * * State for per VM BOs which are moved, but that change is not yet reflected * in the page tables. */static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo){	list_move(&vm_bo->vm_status, &vm_bo->vm->moved);} /** * amdgpu_vm_bo_idle - vm_bo is idle * * @vm_bo: vm_bo which is now idle * * State for PDs/PTs and per VM BOs which have gone through the state machine * and are now idle. */static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo){	list_move(&vm_bo->vm_status, &vm_bo->vm->idle);	vm_bo->moved = false;} /** * amdgpu_vm_bo_invalidated - vm_bo is invalidated * * @vm_bo: vm_bo which is now invalidated * * State for normal BOs which are invalidated and that change not yet reflected * in the PTs. */static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo){	spin_lock(&vm_bo->vm->invalidated_lock);	list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);	spin_unlock(&vm_bo->vm->invalidated_lock);} /** * amdgpu_vm_bo_done - vm_bo is done * * @vm_bo: vm_bo which is now done * * State for normal BOs which are invalidated and that change has been updated * in the PTs. */static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo){	spin_lock(&vm_bo->vm->invalidated_lock);	list_del_init(&vm_bo->vm_status);	spin_unlock(&vm_bo->vm->invalidated_lock);} /** * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm * * @base: base structure for tracking BO usage in a VM * @vm: vm to which bo is to be added * @bo: amdgpu buffer object * * Initialize a bo_va_base structure and add it to the appropriate lists * */static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,				   struct amdgpu_vm *vm,				   struct amdgpu_bo *bo){	base->vm = vm;	base->bo = bo;	base->next = NULL;	INIT_LIST_HEAD(&base->vm_status); 	if (!bo)		return;	base->next = bo->vm_bo;	bo->vm_bo = base; 	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)		return; 	vm->bulk_moveable = false;	if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)		amdgpu_vm_bo_relocated(base);	else		amdgpu_vm_bo_idle(base); 	if (bo->preferred_domains &	    amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))		return; 	/*	 * we checked all the prerequisites, but it looks like this per vm bo	 * is currently evicted. add the bo to the evicted list to make sure it	 * is validated on next vm use to avoid fault.	 * */	amdgpu_vm_bo_evicted(base);} /** * amdgpu_vm_pt_parent - get the parent page directory * * @pt: child page table * * Helper to get the parent entry for the child page table. NULL if we are at * the root page directory. */static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt){	struct amdgpu_bo *parent = pt->base.bo->parent; 	if (!parent)		return NULL; 	return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);} /** * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt */struct amdgpu_vm_pt_cursor {	uint64_t pfn;	struct amdgpu_vm_pt *parent;	struct amdgpu_vm_pt *entry;	unsigned level;}; /** * amdgpu_vm_pt_start - start PD/PT walk * * @adev: amdgpu_device pointer * @vm: amdgpu_vm structure * @start: start address of the walk * @cursor: state to initialize * * Initialize a amdgpu_vm_pt_cursor to start a walk. */static void amdgpu_vm_pt_start(struct amdgpu_device *adev,			       struct amdgpu_vm *vm, uint64_t start,			       struct amdgpu_vm_pt_cursor *cursor){	cursor->pfn = start;	cursor->parent = NULL;	cursor->entry = &vm->root;	cursor->level = adev->vm_manager.root_level;} /** * amdgpu_vm_pt_descendant - go to child node * * @adev: amdgpu_device pointer * @cursor: current state * * Walk to the child node of the current node. * Returns: * True if the walk was possible, false otherwise. */static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,				    struct amdgpu_vm_pt_cursor *cursor){	unsigned mask, shift, idx; 	if (!cursor->entry->entries)		return false; 	BUG_ON(!cursor->entry->base.bo);	mask = amdgpu_vm_entries_mask(adev, cursor->level);	shift = amdgpu_vm_level_shift(adev, cursor->level); 	++cursor->level;	idx = (cursor->pfn >> shift) & mask;	cursor->parent = cursor->entry;	cursor->entry = &cursor->entry->entries[idx];	return true;} /** * amdgpu_vm_pt_sibling - go to sibling node * * @adev: amdgpu_device pointer * @cursor: current state * * Walk to the sibling node of the current node. * Returns: * True if the walk was possible, false otherwise. */static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,				 struct amdgpu_vm_pt_cursor *cursor){	unsigned shift, num_entries; 	/* Root doesn't have a sibling */	if (!cursor->parent)		return false; 	/* Go to our parents and see if we got a sibling */	shift = amdgpu_vm_level_shift(adev, cursor->level - 1);	num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1); 	if (cursor->entry == &cursor->parent->entries[num_entries - 1])		return false; 	cursor->pfn += 1ULL << shift;	cursor->pfn &= ~((1ULL << shift) - 1);	++cursor->entry;	return true;} /** * amdgpu_vm_pt_ancestor - go to parent node * * @cursor: current state * * Walk to the parent node of the current node. * Returns: * True if the walk was possible, false otherwise. */static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor){	if (!cursor->parent)		return false; 	--cursor->level;	cursor->entry = cursor->parent;	cursor->parent = amdgpu_vm_pt_parent(cursor->parent);	return true;} /** * amdgpu_vm_pt_next - get next PD/PT in hieratchy * * @adev: amdgpu_device pointer * @cursor: current state * * Walk the PD/PT tree to the next node. */static void amdgpu_vm_pt_next(struct amdgpu_device *adev,			      struct amdgpu_vm_pt_cursor *cursor){	/* First try a newborn child */	if (amdgpu_vm_pt_descendant(adev, cursor))		return; 	/* If that didn't worked try to find a sibling */	while (!amdgpu_vm_pt_sibling(adev, cursor)) {		/* No sibling, go to our parents and grandparents */		if (!amdgpu_vm_pt_ancestor(cursor)) {			cursor->pfn = ~0ll;			return;		}	}} /** * amdgpu_vm_pt_first_dfs - start a deep first search * * @adev: amdgpu_device structure * @vm: amdgpu_vm structure * @cursor: state to initialize * * Starts a deep first traversal of the PD/PT tree. */static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,				   struct amdgpu_vm *vm,				   struct amdgpu_vm_pt_cursor *start,				   struct amdgpu_vm_pt_cursor *cursor){	if (start)		*cursor = *start;	else		amdgpu_vm_pt_start(adev, vm, 0, cursor);	while (amdgpu_vm_pt_descendant(adev, cursor));} 

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