// SPDX-License-Identifier: GPL-2.0-only/* * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ #include <linux/clk.h>#include <linux/delay.h>#include <linux/interrupt.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_device.h>#include <linux/platform_device.h>#include <linux/slab.h>#include <linux/sort.h> #include <soc/tegra/fuse.h> #include "mc.h" #define MC_INTSTATUS 0x000 #define MC_INTMASK 0x004 #define MC_ERR_STATUS 0x08#define MC_ERR_STATUS_TYPE_SHIFT 28#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)#define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)#define MC_ERR_STATUS_READABLE (1 << 27)#define MC_ERR_STATUS_WRITABLE (1 << 26)#define MC_ERR_STATUS_NONSECURE (1 << 25)#define MC_ERR_STATUS_ADR_HI_SHIFT 20#define MC_ERR_STATUS_ADR_HI_MASK 0x3#define MC_ERR_STATUS_SECURITY (1 << 17)#define MC_ERR_STATUS_RW (1 << 16) #define MC_ERR_ADR 0x0c #define MC_GART_ERROR_REQ 0x30#define MC_DECERR_EMEM_OTHERS_STATUS 0x58#define MC_SECURITY_VIOLATION_STATUS 0x74 #define MC_EMEM_ARB_CFG 0x90#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff#define MC_EMEM_ARB_MISC0 0xd8 #define MC_EMEM_ADR_CFG 0x54#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) #define MC_TIMING_CONTROL 0xfc#define MC_TIMING_UPDATE BIT(0) static const struct of_device_id tegra_mc_of_match[] = {#ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_3x_SOC { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_114_SOC { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_132_SOC { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },#endif#ifdef CONFIG_ARCH_TEGRA_210_SOC { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },#endif { }};MODULE_DEVICE_TABLE(of, tegra_mc_of_match); static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst){ unsigned long flags; u32 value; spin_lock_irqsave(&mc->lock, flags); value = mc_readl(mc, rst->control) | BIT(rst->bit); mc_writel(mc, value, rst->control); spin_unlock_irqrestore(&mc->lock, flags); return 0;} static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst){ return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;} static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst){ unsigned long flags; u32 value; spin_lock_irqsave(&mc->lock, flags); value = mc_readl(mc, rst->control) & ~BIT(rst->bit); mc_writel(mc, value, rst->control); spin_unlock_irqrestore(&mc->lock, flags); return 0;} static int tegra_mc_reset_status_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst){ return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;} const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { .block_dma = tegra_mc_block_dma_common, .dma_idling = tegra_mc_dma_idling_common, .unblock_dma = tegra_mc_unblock_dma_common, .reset_status = tegra_mc_reset_status_common,}; static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev){ return container_of(rcdev, struct tegra_mc, reset);} static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, unsigned long id){ unsigned int i; for (i = 0; i < mc->soc->num_resets; i++) if (mc->soc->resets[i].id == id) return &mc->soc->resets[i]; return NULL;} static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, unsigned long id){ struct tegra_mc *mc = reset_to_mc(rcdev); const struct tegra_mc_reset_ops *rst_ops; const struct tegra_mc_reset *rst; int retries = 500; int err; rst = tegra_mc_reset_find(mc, id); if (!rst) return -ENODEV; rst_ops = mc->soc->reset_ops; if (!rst_ops) return -ENODEV; if (rst_ops->block_dma) { /* block clients DMA requests */ err = rst_ops->block_dma(mc, rst); if (err) { dev_err(mc->dev, "failed to block %s DMA: %d\n", rst->name, err); return err; } } if (rst_ops->dma_idling) { /* wait for completion of the outstanding DMA requests */ while (!rst_ops->dma_idling(mc, rst)) { if (!retries--) { dev_err(mc->dev, "failed to flush %s DMA\n", rst->name); return -EBUSY; } usleep_range(10, 100); } } if (rst_ops->hotreset_assert) { /* clear clients DMA requests sitting before arbitration */ err = rst_ops->hotreset_assert(mc, rst); if (err) { dev_err(mc->dev, "failed to hot reset %s: %d\n", rst->name, err); return err; } } return 0;} static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, unsigned long id){ struct tegra_mc *mc = reset_to_mc(rcdev); const struct tegra_mc_reset_ops *rst_ops; const struct tegra_mc_reset *rst; int err; rst = tegra_mc_reset_find(mc, id); if (!rst) return -ENODEV; rst_ops = mc->soc->reset_ops; if (!rst_ops) return -ENODEV; if (rst_ops->hotreset_deassert) { /* take out client from hot reset */ err = rst_ops->hotreset_deassert(mc, rst); if (err) { dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", rst->name, err); return err; } } if (rst_ops->unblock_dma) { /* allow new DMA requests to proceed to arbitration */ err = rst_ops->unblock_dma(mc, rst); if (err) { dev_err(mc->dev, "failed to unblock %s DMA : %d\n", rst->name, err); return err; } } return 0;} static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, unsigned long id){ struct tegra_mc *mc = reset_to_mc(rcdev); const struct tegra_mc_reset_ops *rst_ops; const struct tegra_mc_reset *rst; rst = tegra_mc_reset_find(mc, id); if (!rst) return -ENODEV; rst_ops = mc->soc->reset_ops; if (!rst_ops) return -ENODEV; return rst_ops->reset_status(mc, rst);} static const struct reset_control_ops tegra_mc_reset_ops = { .assert = tegra_mc_hotreset_assert, .deassert = tegra_mc_hotreset_deassert, .status = tegra_mc_hotreset_status,}; static int tegra_mc_reset_setup(struct tegra_mc *mc){ int err; mc->reset.ops = &tegra_mc_reset_ops; mc->reset.owner = THIS_MODULE; mc->reset.of_node = mc->dev->of_node; mc->reset.of_reset_n_cells = 1; mc->reset.nr_resets = mc->soc->num_resets; err = reset_controller_register(&mc->reset); if (err < 0) return err; return 0;} static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc){ unsigned long long tick; unsigned int i; u32 value; /* compute the number of MC clock cycles per tick */ tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); do_div(tick, NSEC_PER_SEC); value = mc_readl(mc, MC_EMEM_ARB_CFG); value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); mc_writel(mc, value, MC_EMEM_ARB_CFG); /* write latency allowance defaults */ for (i = 0; i < mc->soc->num_clients; i++) { const struct tegra_mc_la *la = &mc->soc->clients[i].la; u32 value; value = mc_readl(mc, la->reg); value &= ~(la->mask << la->shift); value |= (la->def & la->mask) << la->shift; mc_writel(mc, value, la->reg); } /* latch new values */ mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); return 0;} void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate){ unsigned int i; struct tegra_mc_timing *timing = NULL; for (i = 0; i < mc->num_timings; i++) { if (mc->timings[i].rate == rate) { timing = &mc->timings[i]; break; } } if (!timing) { dev_err(mc->dev, "no memory timing registered for rate %lu\n", rate); return; } for (i = 0; i < mc->soc->num_emem_regs; ++i) mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);} unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc){ u8 dram_count; dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; dram_count++; return dram_count;} static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, struct device_node *node){ int err; u32 tmp; err = of_property_read_u32(node, "clock-frequency", &tmp); if (err) { dev_err(mc->dev, "timing %pOFn: failed to read rate\n", node); return err; } timing->rate = tmp; timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, sizeof(u32), GFP_KERNEL); if (!timing->emem_data) return -ENOMEM; err = of_property_read_u32_array(node, "nvidia,emem-configuration", timing->emem_data, mc->soc->num_emem_regs); if (err) { dev_err(mc->dev, "timing %pOFn: failed to read EMEM configuration\n", node); return err; } return 0;} static int load_timings(struct tegra_mc *mc, struct device_node *node){ struct device_node *child; struct tegra_mc_timing *timing; int child_count = of_get_child_count(node); int i = 0, err; mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), GFP_KERNEL); if (!mc->timings) return -ENOMEM; mc->num_timings = child_count; for_each_child_of_node(node, child) { timing = &mc->timings[i++]; err = load_one_timing(mc, timing, child); if (err) { of_node_put(child); return err; } } return 0;} static int tegra_mc_setup_timings(struct tegra_mc *mc){ struct device_node *node; u32 ram_code, node_ram_code; int err; ram_code = tegra_read_ram_code(); mc->num_timings = 0; for_each_child_of_node(mc->dev->of_node, node) { err = of_property_read_u32(node, "nvidia,ram-code", &node_ram_code); if (err || (node_ram_code != ram_code)) continue; err = load_timings(mc, node); of_node_put(node); if (err) return err; break; } if (mc->num_timings == 0) dev_warn(mc->dev, "no memory timings for RAM code %u registered\n", ram_code); return 0;} static const char *const status_names[32] = { [ 1] = "External interrupt", [ 6] = "EMEM address decode error", [ 7] = "GART page fault", [ 8] = "Security violation", [ 9] = "EMEM arbitration error", [10] = "Page fault", [11] = "Invalid APB ASID update", [12] = "VPR violation", [13] = "Secure carveout violation", [16] = "MTS carveout violation",}; static const char *const error_names[8] = { [2] = "EMEM decode error", [3] = "TrustZone violation", [4] = "Carveout violation", [6] = "SMMU translation error",}; static irqreturn_t tegra_mc_irq(int irq, void *data){ struct tegra_mc *mc = data; unsigned long status; unsigned int bit; /* mask all interrupts to avoid flooding */ status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; if (!status) return IRQ_NONE; for_each_set_bit(bit, &status, 32) { const char *error = status_names[bit] ?: "unknown"; const char *client = "unknown", *desc; const char *direction, *secure; phys_addr_t addr = 0; unsigned int i; char perm[7]; u8 id, type; u32 value; value = mc_readl(mc, MC_ERR_STATUS); #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits > 32) { addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & MC_ERR_STATUS_ADR_HI_MASK); addr <<= 32; }#endif if (value & MC_ERR_STATUS_RW) direction = "write"; else direction = "read"; if (value & MC_ERR_STATUS_SECURITY) secure = "secure "; else secure = ""; id = value & mc->soc->client_id_mask; for (i = 0; i < mc->soc->num_clients; i++) { if (mc->soc->clients[i].id == id) { client = mc->soc->clients[i].name; break;Lines 1–500 of 775. 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// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/sort.h> #include <soc/tegra/fuse.h> #include "mc.h" #define MC_INTSTATUS 0x000 #define MC_INTMASK 0x004 #define MC_ERR_STATUS 0x08 #define MC_ERR_STATUS_TYPE_SHIFT 28 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) #define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) #define MC_ERR_STATUS_READABLE (1 << 27) #define MC_ERR_STATUS_WRITABLE (1 << 26) #define MC_ERR_STATUS_NONSECURE (1 << 25) #define MC_ERR_STATUS_ADR_HI_SHIFT 20 #define MC_ERR_STATUS_ADR_HI_MASK 0x3 #define MC_ERR_STATUS_SECURITY (1 << 17) #define MC_ERR_STATUS_RW (1 << 16) #define MC_ERR_ADR 0x0c #define MC_GART_ERROR_REQ 0x30 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 #define MC_SECURITY_VIOLATION_STATUS 0x74 #define MC_EMEM_ARB_CFG 0x90 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0) #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff #define MC_EMEM_ARB_MISC0 0xd8 #define MC_EMEM_ADR_CFG 0x54 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) #define MC_TIMING_CONTROL 0xfc #define MC_TIMING_UPDATE BIT(0) static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, #endif #ifdef CONFIG_ARCH_TEGRA_3x_SOC { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, #endif #ifdef CONFIG_ARCH_TEGRA_114_SOC { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, #endif #ifdef CONFIG_ARCH_TEGRA_124_SOC { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, #endif #ifdef CONFIG_ARCH_TEGRA_132_SOC { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, #endif #ifdef CONFIG_ARCH_TEGRA_210_SOC { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, #endif { } }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; u32 value; spin_lock_irqsave(&mc->lock, flags); value = mc_readl(mc, rst->control) | BIT(rst->bit); mc_writel(mc, value, rst->control); spin_unlock_irqrestore(&mc->lock, flags); return 0; } static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; } static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { unsigned long flags; u32 value; spin_lock_irqsave(&mc->lock, flags); value = mc_readl(mc, rst->control) & ~BIT(rst->bit); mc_writel(mc, value, rst->control); spin_unlock_irqrestore(&mc->lock, flags); return 0; } static int tegra_mc_reset_status_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; } const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { .block_dma = tegra_mc_block_dma_common, .dma_idling = tegra_mc_dma_idling_common, .unblock_dma = tegra_mc_unblock_dma_common, .reset_status = tegra_mc_reset_status_common, }; static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) { return container_of(rcdev, struct tegra_mc, reset); } static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, unsigned long id) { unsigned int i; for (i = 0; i < mc->soc->num_resets; i++) if (mc->soc->resets[i].id == id) return &mc->soc->resets[i]; return NULL; } static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct tegra_mc *mc = reset_to_mc(rcdev); const struct tegra_mc_reset_ops *rst_ops; const struct tegra_mc_reset *rst; int retries = 500; int err; rst = tegra_mc_reset_find(mc, id); if (!rst) return -ENODEV; rst_ops = mc->soc->reset_ops; if (!rst_ops) return -ENODEV; if (rst_ops->block_dma) { /* block clients DMA requests */ err = rst_ops->block_dma(mc, rst); if (err) { dev_err(mc->dev, "failed to block %s DMA: %d\n", rst->name, err); return err; } } if (rst_ops->dma_idling) { /* wait for completion of the outstanding DMA requests */ while (!rst_ops->dma_idling(mc, rst)) { if (!retries--) { dev_err(mc->dev, "failed to flush %s DMA\n", rst->name); return -EBUSY; } usleep_range(10, 100); } } if (rst_ops->hotreset_assert) { /* clear clients DMA requests sitting before arbitration */ err = rst_ops->hotreset_assert(mc, rst); if (err) { dev_err(mc->dev, "failed to hot reset %s: %d\n", rst->name, err); return err; } } return 0; } static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct tegra_mc *mc = reset_to_mc(rcdev); const struct tegra_mc_reset_ops *rst_ops; const struct tegra_mc_reset *rst; int err; rst = tegra_mc_reset_find(mc, id); if (!rst) return -ENODEV; rst_ops = mc->soc->reset_ops; if (!rst_ops) return -ENODEV; if (rst_ops->hotreset_deassert) { /* take out client from hot reset */ err = rst_ops->hotreset_deassert(mc, rst); if (err) { dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", rst->name, err); return err; } } if (rst_ops->unblock_dma) { /* allow new DMA requests to proceed to arbitration */ err = rst_ops->unblock_dma(mc, rst); if (err) { dev_err(mc->dev, "failed to unblock %s DMA : %d\n", rst->name, err); return err; } } return 0; } static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, unsigned long id) { struct tegra_mc *mc = reset_to_mc(rcdev); const struct tegra_mc_reset_ops *rst_ops; const struct tegra_mc_reset *rst; rst = tegra_mc_reset_find(mc, id); if (!rst) return -ENODEV; rst_ops = mc->soc->reset_ops; if (!rst_ops) return -ENODEV; return rst_ops->reset_status(mc, rst); } static const struct reset_control_ops tegra_mc_reset_ops = { .assert = tegra_mc_hotreset_assert, .deassert = tegra_mc_hotreset_deassert, .status = tegra_mc_hotreset_status, }; static int tegra_mc_reset_setup(struct tegra_mc *mc) { int err; mc->reset.ops = &tegra_mc_reset_ops; mc->reset.owner = THIS_MODULE; mc->reset.of_node = mc->dev->of_node; mc->reset.of_reset_n_cells = 1; mc->reset.nr_resets = mc->soc->num_resets; err = reset_controller_register(&mc->reset); if (err < 0) return err; return 0; } static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) { unsigned long long tick; unsigned int i; u32 value; /* compute the number of MC clock cycles per tick */ tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); do_div(tick, NSEC_PER_SEC); value = mc_readl(mc, MC_EMEM_ARB_CFG); value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); mc_writel(mc, value, MC_EMEM_ARB_CFG); /* write latency allowance defaults */ for (i = 0; i < mc->soc->num_clients; i++) { const struct tegra_mc_la *la = &mc->soc->clients[i].la; u32 value; value = mc_readl(mc, la->reg); value &= ~(la->mask << la->shift); value |= (la->def & la->mask) << la->shift; mc_writel(mc, value, la->reg); } /* latch new values */ mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); return 0; } void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) { unsigned int i; struct tegra_mc_timing *timing = NULL; for (i = 0; i < mc->num_timings; i++) { if (mc->timings[i].rate == rate) { timing = &mc->timings[i]; break; } } if (!timing) { dev_err(mc->dev, "no memory timing registered for rate %lu\n", rate); return; } for (i = 0; i < mc->soc->num_emem_regs; ++i) mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); } unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) { u8 dram_count; dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; dram_count++; return dram_count; } static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, struct device_node *node) { int err; u32 tmp; err = of_property_read_u32(node, "clock-frequency", &tmp); if (err) { dev_err(mc->dev, "timing %pOFn: failed to read rate\n", node); return err; } timing->rate = tmp; timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, sizeof(u32), GFP_KERNEL); if (!timing->emem_data) return -ENOMEM; err = of_property_read_u32_array(node, "nvidia,emem-configuration", timing->emem_data, mc->soc->num_emem_regs); if (err) { dev_err(mc->dev, "timing %pOFn: failed to read EMEM configuration\n", node); return err; } return 0; } static int load_timings(struct tegra_mc *mc, struct device_node *node) { struct device_node *child; struct tegra_mc_timing *timing; int child_count = of_get_child_count(node); int i = 0, err; mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), GFP_KERNEL); if (!mc->timings) return -ENOMEM; mc->num_timings = child_count; for_each_child_of_node(node, child) { timing = &mc->timings[i++]; err = load_one_timing(mc, timing, child); if (err) { of_node_put(child); return err; } } return 0; } static int tegra_mc_setup_timings(struct tegra_mc *mc) { struct device_node *node; u32 ram_code, node_ram_code; int err; ram_code = tegra_read_ram_code(); mc->num_timings = 0; for_each_child_of_node(mc->dev->of_node, node) { err = of_property_read_u32(node, "nvidia,ram-code", &node_ram_code); if (err || (node_ram_code != ram_code)) continue; err = load_timings(mc, node); of_node_put(node); if (err) return err; break; } if (mc->num_timings == 0) dev_warn(mc->dev, "no memory timings for RAM code %u registered\n", ram_code); return 0; } static const char *const status_names[32] = { [ 1] = "External interrupt", [ 6] = "EMEM address decode error", [ 7] = "GART page fault", [ 8] = "Security violation", [ 9] = "EMEM arbitration error", [10] = "Page fault", [11] = "Invalid APB ASID update", [12] = "VPR violation", [13] = "Secure carveout violation", [16] = "MTS carveout violation", }; static const char *const error_names[8] = { [2] = "EMEM decode error", [3] = "TrustZone violation", [4] = "Carveout violation", [6] = "SMMU translation error", }; static irqreturn_t tegra_mc_irq(int irq, void *data) { struct tegra_mc *mc = data; unsigned long status; unsigned int bit; /* mask all interrupts to avoid flooding */ status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; if (!status) return IRQ_NONE; for_each_set_bit(bit, &status, 32) { const char *error = status_names[bit] ?: "unknown"; const char *client = "unknown", *desc; const char *direction, *secure; phys_addr_t addr = 0; unsigned int i; char perm[7]; u8 id, type; u32 value; value = mc_readl(mc, MC_ERR_STATUS); #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits > 32) { addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & MC_ERR_STATUS_ADR_HI_MASK); addr <<= 32; } #endif if (value & MC_ERR_STATUS_RW) direction = "write"; else direction = "read"; if (value & MC_ERR_STATUS_SECURITY) secure = "secure "; else secure = ""; id = value & mc->soc->client_id_mask; for (i = 0; i < mc->soc->num_clients; i++) { if (mc->soc->clients[i].id == id) { client = mc->soc->clients[i].name; break;