/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/kthread.h>#include <linux/pci.h>#include <linux/uaccess.h> #include <drm/drm_debugfs.h> #include "amdgpu.h" /** * amdgpu_debugfs_add_files - Add simple debugfs entries * * @adev:  Device to attach debugfs entries to * @files:  Array of function callbacks that respond to reads * @nfiles: Number of callbacks to register * */int amdgpu_debugfs_add_files(struct amdgpu_device *adev,			     const struct drm_info_list *files,			     unsigned nfiles){	unsigned i; 	for (i = 0; i < adev->debugfs_count; i++) {		if (adev->debugfs[i].files == files) {			/* Already registered */			return 0;		}	} 	i = adev->debugfs_count + 1;	if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {		DRM_ERROR("Reached maximum number of debugfs components.\n");		DRM_ERROR("Report so we increase "			  "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");		return -EINVAL;	}	adev->debugfs[adev->debugfs_count].files = files;	adev->debugfs[adev->debugfs_count].num_files = nfiles;	adev->debugfs_count = i;#if defined(CONFIG_DEBUG_FS)	drm_debugfs_create_files(files, nfiles,				 adev->ddev->primary->debugfs_root,				 adev->ddev->primary);#endif	return 0;} #if defined(CONFIG_DEBUG_FS) /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * * @read: True if reading * @f: open file handle * @buf: User buffer to write/read to * @size: Number of bytes to write/read * @pos:  Offset to seek to * * This debugfs entry has special meaning on the offset being sought. * Various bits have different meanings: * * Bit 62:  Indicates a GRBM bank switch is needed * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is * 			zero) * Bits 24..33: The SE or ME selector if needed * Bits 34..43: The SH (or SA) or PIPE selector if needed * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed * * Bit 23:  Indicates that the PM power gating lock should be held * 			This is necessary to read registers that might be * 			unreliable during a power gating transistion. * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,		char __user *buf, size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r;	bool pm_pg_lock, use_bank, use_ring;	unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid; 	pm_pg_lock = use_bank = use_ring = false;	instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0; 	if (size & 0x3 || *pos & 0x3 ||			((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))		return -EINVAL; 	/* are we reading registers for which a PG lock is necessary? */	pm_pg_lock = (*pos >> 23) & 1; 	if (*pos & (1ULL << 62)) {		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; 		if (se_bank == 0x3FF)			se_bank = 0xFFFFFFFF;		if (sh_bank == 0x3FF)			sh_bank = 0xFFFFFFFF;		if (instance_bank == 0x3FF)			instance_bank = 0xFFFFFFFF;		use_bank = 1;	} else if (*pos & (1ULL << 61)) { 		me = (*pos & GENMASK_ULL(33, 24)) >> 24;		pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;		queue = (*pos & GENMASK_ULL(53, 44)) >> 44;		vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; 		use_ring = 1;	} else {		use_bank = use_ring = 0;	} 	*pos &= (1UL << 22) - 1; 	if (use_bank) {		if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||		    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))			return -EINVAL;		mutex_lock(&adev->grbm_idx_mutex);		amdgpu_gfx_select_se_sh(adev, se_bank,					sh_bank, instance_bank);	} else if (use_ring) {		mutex_lock(&adev->srbm_mutex);		amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);	} 	if (pm_pg_lock)		mutex_lock(&adev->pm.mutex); 	while (size) {		uint32_t value; 		if (read) {			value = RREG32(*pos >> 2);			r = put_user(value, (uint32_t *)buf);		} else {			r = get_user(value, (uint32_t *)buf);			if (!r)				WREG32(*pos >> 2, value);		}		if (r) {			result = r;			goto end;		} 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} end:	if (use_bank) {		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);		mutex_unlock(&adev->grbm_idx_mutex);	} else if (use_ring) {		amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);		mutex_unlock(&adev->srbm_mutex);	} 	if (pm_pg_lock)		mutex_unlock(&adev->pm.mutex); 	return result;} /** * amdgpu_debugfs_regs_read - Callback for reading MMIO registers */static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);} /** * amdgpu_debugfs_regs_write - Callback for writing MMIO registers */static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,					 size_t size, loff_t *pos){	return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);}  /** * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register * * @f: open file handle * @buf: User buffer to store read data in * @size: Number of bytes to read * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	while (size) {		uint32_t value; 		value = RREG32_PCIE(*pos >> 2);		r = put_user(value, (uint32_t *)buf);		if (r)			return r; 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	return result;} /** * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register * * @f: open file handle * @buf: User buffer to write data from * @size: Number of bytes to write * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to write.  This * allows writing multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,					 size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	while (size) {		uint32_t value; 		r = get_user(value, (uint32_t *)buf);		if (r)			return r; 		WREG32_PCIE(*pos >> 2, value); 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	return result;} /** * amdgpu_debugfs_regs_didt_read - Read from a DIDT register * * @f: open file handle * @buf: User buffer to store read data in * @size: Number of bytes to read * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	while (size) {		uint32_t value; 		value = RREG32_DIDT(*pos >> 2);		r = put_user(value, (uint32_t *)buf);		if (r)			return r; 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	return result;} /** * amdgpu_debugfs_regs_didt_write - Write to a DIDT register * * @f: open file handle * @buf: User buffer to write data from * @size: Number of bytes to write * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to write.  This * allows writing multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,					 size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	while (size) {		uint32_t value; 		r = get_user(value, (uint32_t *)buf);		if (r)			return r; 		WREG32_DIDT(*pos >> 2, value); 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	return result;} /** * amdgpu_debugfs_regs_smc_read - Read from a SMC register * * @f: open file handle * @buf: User buffer to store read data in * @size: Number of bytes to read * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to read.  This * allows reading multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	while (size) {		uint32_t value; 		value = RREG32_SMC(*pos);		r = put_user(value, (uint32_t *)buf);		if (r)			return r; 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	return result;} /** * amdgpu_debugfs_regs_smc_write - Write to a SMC register * * @f: open file handle * @buf: User buffer to write data from * @size: Number of bytes to write * @pos:  Offset to seek to * * The lower bits are the BYTE offset of the register to write.  This * allows writing multiple registers in a single call and having * the returned size reflect that. */static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,					 size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	while (size) {		uint32_t value; 		r = get_user(value, (uint32_t *)buf);		if (r)			return r; 		WREG32_SMC(*pos, value); 		result += 4;		buf += 4;		*pos += 4;		size -= 4;	} 	return result;} /** * amdgpu_debugfs_gca_config_read - Read from gfx config data * * @f: open file handle * @buf: User buffer to store read data in * @size: Number of bytes to read * @pos:  Offset to seek to * * This file is used to access configuration data in a somewhat * stable fashion.  The format is a series of DWORDs with the first * indicating which revision it is.  New content is appended to the * end so that older software can still read the data. */ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,					size_t size, loff_t *pos){	struct amdgpu_device *adev = file_inode(f)->i_private;	ssize_t result = 0;	int r;	uint32_t *config, no_regs = 0; 	if (size & 0x3 || *pos & 0x3)		return -EINVAL; 	config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);	if (!config)		return -ENOMEM; 	/* version, increment each time something is added */	config[no_regs++] = 3;	config[no_regs++] = adev->gfx.config.max_shader_engines;	config[no_regs++] = adev->gfx.config.max_tile_pipes;	config[no_regs++] = adev->gfx.config.max_cu_per_sh;	config[no_regs++] = adev->gfx.config.max_sh_per_se;	config[no_regs++] = adev->gfx.config.max_backends_per_se;	config[no_regs++] = adev->gfx.config.max_texture_channel_caches;	config[no_regs++] = adev->gfx.config.max_gprs;	config[no_regs++] = adev->gfx.config.max_gs_threads;	config[no_regs++] = adev->gfx.config.max_hw_contexts;	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;	config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;	config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;	config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;	config[no_regs++] = adev->gfx.config.num_tile_pipes;	config[no_regs++] = adev->gfx.config.backend_enable_mask;

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