/* SPDX-License-Identifier: GPL-2.0-only *//* * Exception handling for Microblaze * * Rewriten interrupt handling * * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> * Copyright (C) 2008-2009 PetaLogix * * uClinux customisation (C) 2005 John Williams * * MMU code derived from arch/ppc/kernel/head_4xx.S: *	Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org> *		Initial PowerPC version. *	Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> *		Rewritten for PReP *	Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au> *		Low-level exception handers, MMU support, and rewrite. *	Copyright (C) 1997 Dan Malek <dmalek@jlc.net> *		PowerPC 8xx modifications. *	Copyright (C) 1998-1999 TiVo, Inc. *		PowerPC 403GCX modifications. *	Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu> *		PowerPC 403GCX/405GP modifications. *	Copyright 2000 MontaVista Software Inc. *		PPC405 modifications *	PowerPC 403GCX/405GP modifications. *		Author: MontaVista Software, Inc. *		frank_rowand@mvista.com or source@mvista.com *		debbie_chu@mvista.com * * Original code * Copyright (C) 2004 Xilinx, Inc. */ /* * Here are the handlers which don't require enabling translation * and calling other kernel code thus we can keep their design very simple * and do all processing in real mode. All what they need is a valid current * (that is an issue for the CONFIG_REGISTER_TASK_PTR case) * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore * these registers are saved/restored * The handlers which require translation are in entry.S --KAA * * Microblaze HW Exception Handler * - Non self-modifying exception handler for the following exception conditions *   - Unalignment *   - Instruction bus error *   - Data bus error *   - Illegal instruction opcode *   - Divide-by-zero * *   - Privileged instruction exception (MMU) *   - Data storage exception (MMU) *   - Instruction storage exception (MMU) *   - Data TLB miss exception (MMU) *   - Instruction TLB miss exception (MMU) * * Note we disable interrupts during exception handling, otherwise we will * possibly get multiple re-entrancy if interrupt handles themselves cause * exceptions. JW */ #include <asm/exceptions.h>#include <asm/unistd.h>#include <asm/page.h> #include <asm/entry.h>#include <asm/current.h>#include <linux/linkage.h>#include <linux/pgtable.h> #include <asm/mmu.h>#include <asm/signal.h>#include <asm/registers.h>#include <asm/asm-offsets.h> #undef DEBUG /* Helpful Macros */#define NUM_TO_REG(num)		r ## num 	#define RESTORE_STATE			\		lwi	r5, r1, 0;		\		mts	rmsr, r5;		\		nop;				\		lwi	r3, r1, PT_R3;		\		lwi	r4, r1, PT_R4;		\		lwi	r5, r1, PT_R5;		\		lwi	r6, r1, PT_R6;		\		lwi	r11, r1, PT_R11;	\		lwi	r31, r1, PT_R31;	\		lwi	r1, r1, PT_R1; #define LWREG_NOP			\	bri	ex_handler_unhandled;	\	nop; #define SWREG_NOP			\	bri	ex_handler_unhandled;	\	nop; /* r3 is the source */#define R3_TO_LWREG_V(regnum)				\	swi	r3, r1, 4 * regnum;				\	bri	ex_handler_done; /* r3 is the source */#define R3_TO_LWREG(regnum)				\	or	NUM_TO_REG (regnum), r0, r3;		\	bri	ex_handler_done; /* r3 is the target */#define SWREG_TO_R3_V(regnum)				\	lwi	r3, r1, 4 * regnum;				\	bri	ex_sw_tail; /* r3 is the target */#define SWREG_TO_R3(regnum)				\	or	r3, r0, NUM_TO_REG (regnum);		\	bri	ex_sw_tail; 	#define R3_TO_LWREG_VM_V(regnum)		\		brid	ex_lw_end_vm;			\		swi	r3, r7, 4 * regnum; 	#define R3_TO_LWREG_VM(regnum)			\		brid	ex_lw_end_vm;			\		or	NUM_TO_REG (regnum), r0, r3; 	#define SWREG_TO_R3_VM_V(regnum)		\		brid	ex_sw_tail_vm;			\		lwi	r3, r7, 4 * regnum; 	#define SWREG_TO_R3_VM(regnum)			\		brid	ex_sw_tail_vm;			\		or	r3, r0, NUM_TO_REG (regnum); 	/* Shift right instruction depending on available configuration */	#if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0	/* Only the used shift constants defined here - add more if needed */	#define BSRLI2(rD, rA)				\		srl rD, rA;		/* << 1 */	\		srl rD, rD;		/* << 2 */	#define BSRLI4(rD, rA)		\		BSRLI2(rD, rA);		\		BSRLI2(rD, rD)	#define BSRLI10(rD, rA)				\		srl rD, rA;		/* << 1 */	\		srl rD, rD;		/* << 2 */	\		srl rD, rD;		/* << 3 */	\		srl rD, rD;		/* << 4 */	\		srl rD, rD;		/* << 5 */	\		srl rD, rD;		/* << 6 */	\		srl rD, rD;		/* << 7 */	\		srl rD, rD;		/* << 8 */	\		srl rD, rD;		/* << 9 */	\		srl rD, rD		/* << 10 */	#define BSRLI20(rD, rA)		\		BSRLI10(rD, rA);	\		BSRLI10(rD, rD) 	.macro	bsrli, rD, rA, IMM	.if (\IMM) == 2		BSRLI2(\rD, \rA)	.elseif (\IMM) == 10		BSRLI10(\rD, \rA)	.elseif (\IMM) == 12		BSRLI2(\rD, \rA)		BSRLI10(\rD, \rD)	.elseif (\IMM) == 14		BSRLI4(\rD, \rA)		BSRLI10(\rD, \rD)	.elseif (\IMM) == 20		BSRLI20(\rD, \rA)	.elseif (\IMM) == 24		BSRLI4(\rD, \rA)		BSRLI20(\rD, \rD)	.elseif (\IMM) == 28		BSRLI4(\rD, \rA)		BSRLI4(\rD, \rD)		BSRLI20(\rD, \rD)	.else	.error "BSRLI shift macros \IMM"	.endif	.endm	#endif  .extern other_exception_handler /* Defined in exception.c */ /* * hw_exception_handler - Handler for exceptions * * Exception handler notes: * - Handles all exceptions * - Does not handle unaligned exceptions during load into r17, r1, r0. * - Does not handle unaligned exceptions during store from r17 (cannot be *   done) and r1 (slows down common case) * *  Relevant register structures * *  EAR - |----|----|----|----|----|----|----|----| *      - <  ##   32 bit faulting address     ##  > * *  ESR - |----|----|----|----|----| - | - |-----|-----| *      -                            W   S   REG   EXC * * * STACK FRAME STRUCTURE (for CONFIG_MMU=n) * ---------------------------------------- * *      +-------------+         + 0 *      |     MSR     | *      +-------------+         + 4 *      |     r1      | *      |      .      | *      |      .      | *      |      .      | *      |      .      | *      |     r18     | *      +-------------+         + 76 *      |      .      | *      |      .      | * * MMU kernel uses the same 'pt_pool_space' pointed space * which is used for storing register values - noMMu style was, that values were * stored in stack but in case of failure you lost information about register. * Currently you can see register value in memory in specific place. * In compare to with previous solution the speed should be the same. * * MMU exception handler has different handling compare to no MMU kernel. * Exception handler use jump table for directing of what happen. For MMU kernel * is this approach better because MMU relate exception are handled by asm code * in this file. In compare to with MMU expect of unaligned exception * is everything handled by C code. */ /* * every of these handlers is entered having R3/4/5/6/11/current saved on stack * and clobbered so care should be taken to restore them if someone is going to * return from exception */ /* wrappers to restore state before coming to entry.S */.section .data.align 4pt_pool_space:	.space	PT_SIZE #ifdef DEBUG/* Create space for exception counting. */.section .data.global exception_debug_table.align 4exception_debug_table:	/* Look at exception vector table. There is 32 exceptions * word size */	.space	(32 * 4)#endif /* DEBUG */ .section .rodata.align 4_MB_HW_ExceptionVectorTable:/*  0 - Undefined */	.long	TOPHYS(ex_handler_unhandled)/*  1 - Unaligned data access exception */	.long	TOPHYS(handle_unaligned_ex)/*  2 - Illegal op-code exception */	.long	TOPHYS(full_exception_trapw)/*  3 - Instruction bus error exception */	.long	TOPHYS(full_exception_trapw)/*  4 - Data bus error exception */	.long	TOPHYS(full_exception_trapw)/*  5 - Divide by zero exception */	.long	TOPHYS(full_exception_trapw)/*  6 - Floating point unit exception */	.long	TOPHYS(full_exception_trapw)/*  7 - Privileged instruction exception */	.long	TOPHYS(full_exception_trapw)/*  8 - 15 - Undefined */	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)/* 16 - Data storage exception */	.long	TOPHYS(handle_data_storage_exception)/* 17 - Instruction storage exception */	.long	TOPHYS(handle_instruction_storage_exception)/* 18 - Data TLB miss exception */	.long	TOPHYS(handle_data_tlb_miss_exception)/* 19 - Instruction TLB miss exception */	.long	TOPHYS(handle_instruction_tlb_miss_exception)/* 20 - 31 - Undefined */	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled)	.long	TOPHYS(ex_handler_unhandled) .global _hw_exception_handler.section .text.align 4.ent _hw_exception_handler_hw_exception_handler:	swi	r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */	/* Save date to kernel memory. Here is the problem	 * when you came from user space */	ori	r1, r0, TOPHYS(pt_pool_space);	swi	r3, r1, PT_R3	swi	r4, r1, PT_R4	swi	r5, r1, PT_R5	swi	r6, r1, PT_R6 	swi	r11, r1, PT_R11	swi	r31, r1, PT_R31	lwi	r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */ 	mfs	r5, rmsr;	nop	swi	r5, r1, 0;	mfs	r4, resr	nop	mfs	r3, rear;	nop 	andi	r5, r4, 0x1F;		/* Extract ESR[EXC] */ 	/* Calculate exception vector offset = r5 << 2 */	addk	r6, r5, r5; /* << 1 */	addk	r6, r6, r6; /* << 2 */ #ifdef DEBUG/* counting which exception happen */	lwi	r5, r0, TOPHYS(exception_debug_table)	addi	r5, r5, 1	swi	r5, r0, TOPHYS(exception_debug_table)	lwi	r5, r6, TOPHYS(exception_debug_table)	addi	r5, r5, 1	swi	r5, r6, TOPHYS(exception_debug_table)#endif/* end */	/* Load the HW Exception vector */	lwi	r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)	bra	r6 full_exception_trapw:	RESTORE_STATE	bri	full_exception_trap /* 0x01 - Unaligned data access exception * This occurs when a word access is not aligned on a word boundary, * or when a 16-bit access is not aligned on a 16-bit boundary. * This handler perform the access, and returns, except for MMU when * the unaligned address is last on a 4k page or the physical address is * not found in the page table, in which case unaligned_data_trap is called. */handle_unaligned_ex:	/* Working registers already saved: R3, R4, R5, R6	 *  R4 = ESR	 *  R3 = EAR	 */	andi	r6, r4, 0x1000			/* Check ESR[DS] */	beqi	r6, _no_delayslot		/* Branch if ESR[DS] not set */	mfs	r17, rbtr;	/* ESR[DS] set - return address in BTR */	nop_no_delayslot:	/* jump to high level unaligned handler */	RESTORE_STATE;	bri	unaligned_data_trap 	andi	r6, r4, 0x3E0; /* Mask and extract the register operand */	srl	r6, r6; /* r6 >> 5 */	srl	r6, r6;	srl	r6, r6;	srl	r6, r6;	srl	r6, r6;	/* Store the register operand in a temporary location */	sbi	r6, r0, TOPHYS(ex_reg_op); 	andi	r6, r4, 0x400; /* Extract ESR[S] */	bnei	r6, ex_sw;ex_lw:	andi	r6, r4, 0x800; /* Extract ESR[W] */	beqi	r6, ex_lhw;	lbui	r5, r3, 0; /* Exception address in r3 */	/* Load a word, byte-by-byte from destination address		and save it in tmp space */	sbi	r5, r0, TOPHYS(ex_tmp_data_loc_0);	lbui	r5, r3, 1;	sbi	r5, r0, TOPHYS(ex_tmp_data_loc_1);	lbui	r5, r3, 2;	sbi	r5, r0, TOPHYS(ex_tmp_data_loc_2);	lbui	r5, r3, 3;	sbi	r5, r0, TOPHYS(ex_tmp_data_loc_3);	/* Get the destination register value into r4 */	lwi	r4, r0, TOPHYS(ex_tmp_data_loc_0);	bri	ex_lw_tail;ex_lhw:	lbui	r5, r3, 0; /* Exception address in r3 */	/* Load a half-word, byte-by-byte from destination		address and save it in tmp space */	sbi	r5, r0, TOPHYS(ex_tmp_data_loc_0);	lbui	r5, r3, 1;	sbi	r5, r0, TOPHYS(ex_tmp_data_loc_1);	/* Get the destination register value into r4 */	lhui	r4, r0, TOPHYS(ex_tmp_data_loc_0);ex_lw_tail:	/* Get the destination register number into r5 */	lbui	r5, r0, TOPHYS(ex_reg_op);	/* Form load_word jump table offset (lw_table + (8 * regnum)) */	addik	r6, r0, TOPHYS(lw_table);	addk	r5, r5, r5;	addk	r5, r5, r5;	addk	r5, r5, r5;	addk	r5, r5, r6;	bra	r5;ex_lw_end: /* Exception handling of load word, ends */ex_sw:	/* Get the destination register number into r5 */	lbui	r5, r0, TOPHYS(ex_reg_op);	/* Form store_word jump table offset (sw_table + (8 * regnum)) */	addik	r6, r0, TOPHYS(sw_table);	add	r5, r5, r5;	add	r5, r5, r5;	add	r5, r5, r5;	add	r5, r5, r6;	bra	r5;ex_sw_tail:	mfs	r6, resr;	nop	andi	r6, r6, 0x800; /* Extract ESR[W] */	beqi	r6, ex_shw;	/* Get the word - delay slot */	swi	r4, r0, TOPHYS(ex_tmp_data_loc_0);	/* Store the word, byte-by-byte into destination address */	lbui	r4, r0, TOPHYS(ex_tmp_data_loc_0);	sbi	r4, r3, 0;	lbui	r4, r0, TOPHYS(ex_tmp_data_loc_1);	sbi	r4, r3, 1;	lbui	r4, r0, TOPHYS(ex_tmp_data_loc_2);	sbi	r4, r3, 2;	lbui	r4, r0, TOPHYS(ex_tmp_data_loc_3);	sbi	r4, r3, 3;	bri	ex_handler_done; ex_shw:	/* Store the lower half-word, byte-by-byte into destination address */	swi	r4, r0, TOPHYS(ex_tmp_data_loc_0);	lbui	r4, r0, TOPHYS(ex_tmp_data_loc_2);	sbi	r4, r3, 0;	lbui	r4, r0, TOPHYS(ex_tmp_data_loc_3);	sbi	r4, r3, 1;ex_sw_end: /* Exception handling of store word, ends. */ ex_handler_done:	RESTORE_STATE;	rted	r17, 0	nop 	/* Exception vector entry code. This code runs with address translation	 * turned off (i.e. using physical addresses). */ 	/* Exception vectors. */ 	/* 0x10 - Data Storage Exception	 * This happens for just a few reasons. U0 set (but we don't do that),	 * or zone protection fault (user violation, write to protected page).	 * If this is just an update of modified status, we do that quickly	 * and exit. Otherwise, we call heavyweight functions to do the work.	 */	handle_data_storage_exception:		/* Working registers already saved: R3, R4, R5, R6		 * R3 = ESR		 */		mfs	r11, rpid		nop		/* If we are faulting a kernel address, we have to use the		 * kernel page tables.		 */		ori	r5, r0, CONFIG_KERNEL_START		cmpu	r5, r3, r5		bgti	r5, ex3		/* First, check if it was a zone fault (which means a user		 * tried to access a kernel or read-protected page - always		 * a SEGV). All other faults here must be stores, so no		 * need to check ESR_S as well. */		andi	r4, r4, ESR_DIZ		/* ESR_Z - zone protection */		bnei	r4, ex2 

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