/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/firmware.h> #include "amdgpu.h"#include "amdgpu_discovery.h"#include "soc15_hw_ip.h"#include "discovery.h"#include "amdgpu_ras.h" #include "soc15.h"#include "gfx_v9_0.h"#include "gfx_v9_4_3.h"#include "gmc_v9_0.h"#include "df_v1_7.h"#include "df_v3_6.h"#include "df_v4_3.h"#include "df_v4_6_2.h"#include "df_v4_15.h"#include "nbio_v6_1.h"#include "nbio_v7_0.h"#include "nbio_v7_4.h"#include "nbio_v7_9.h"#include "nbio_v7_11.h"#include "hdp_v4_0.h"#include "vega10_ih.h"#include "vega20_ih.h"#include "sdma_v4_0.h"#include "sdma_v4_4_2.h"#include "uvd_v7_0.h"#include "vce_v4_0.h"#include "vcn_v1_0.h"#include "vcn_v2_5.h"#include "jpeg_v2_5.h"#include "smuio_v9_0.h"#include "gmc_v10_0.h"#include "gmc_v11_0.h"#include "gmc_v12_0.h"#include "gfxhub_v2_0.h"#include "mmhub_v2_0.h"#include "nbio_v2_3.h"#include "nbio_v4_3.h"#include "nbio_v7_2.h"#include "nbio_v7_7.h"#include "nbif_v6_3_1.h"#include "hdp_v5_0.h"#include "hdp_v5_2.h"#include "hdp_v6_0.h"#include "hdp_v7_0.h"#include "nv.h"#include "soc21.h"#include "soc24.h"#include "navi10_ih.h"#include "ih_v6_0.h"#include "ih_v6_1.h"#include "ih_v7_0.h"#include "gfx_v10_0.h"#include "gfx_v11_0.h"#include "gfx_v12_0.h"#include "sdma_v5_0.h"#include "sdma_v5_2.h"#include "sdma_v6_0.h"#include "sdma_v7_0.h"#include "lsdma_v6_0.h"#include "lsdma_v7_0.h"#include "vcn_v2_0.h"#include "jpeg_v2_0.h"#include "vcn_v3_0.h"#include "jpeg_v3_0.h"#include "vcn_v4_0.h"#include "jpeg_v4_0.h"#include "vcn_v4_0_3.h"#include "jpeg_v4_0_3.h"#include "vcn_v4_0_5.h"#include "jpeg_v4_0_5.h"#include "amdgpu_vkms.h"#include "mes_v11_0.h"#include "mes_v12_0.h"#include "smuio_v11_0.h"#include "smuio_v11_0_6.h"#include "smuio_v13_0.h"#include "smuio_v13_0_3.h"#include "smuio_v13_0_6.h"#include "smuio_v14_0_2.h"#include "vcn_v5_0_0.h"#include "jpeg_v5_0_0.h" #include "amdgpu_vpe.h"#if defined(CONFIG_DRM_AMD_ISP)#include "amdgpu_isp.h"#endif #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY); #define mmIP_DISCOVERY_VERSION  0x16A00#define mmRCC_CONFIG_MEMSIZE	0xde3#define mmMP0_SMN_C2PMSG_33	0x16061#define mmMM_INDEX		0x0#define mmMM_INDEX_HI		0x6#define mmMM_DATA		0x1 static const char *hw_id_names[HW_ID_MAX] = {	[MP1_HWID]		= "MP1",	[MP2_HWID]		= "MP2",	[THM_HWID]		= "THM",	[SMUIO_HWID]		= "SMUIO",	[FUSE_HWID]		= "FUSE",	[CLKA_HWID]		= "CLKA",	[PWR_HWID]		= "PWR",	[GC_HWID]		= "GC",	[UVD_HWID]		= "UVD",	[AUDIO_AZ_HWID]		= "AUDIO_AZ",	[ACP_HWID]		= "ACP",	[DCI_HWID]		= "DCI",	[DMU_HWID]		= "DMU",	[DCO_HWID]		= "DCO",	[DIO_HWID]		= "DIO",	[XDMA_HWID]		= "XDMA",	[DCEAZ_HWID]		= "DCEAZ",	[DAZ_HWID]		= "DAZ",	[SDPMUX_HWID]		= "SDPMUX",	[NTB_HWID]		= "NTB",	[IOHC_HWID]		= "IOHC",	[L2IMU_HWID]		= "L2IMU",	[VCE_HWID]		= "VCE",	[MMHUB_HWID]		= "MMHUB",	[ATHUB_HWID]		= "ATHUB",	[DBGU_NBIO_HWID]	= "DBGU_NBIO",	[DFX_HWID]		= "DFX",	[DBGU0_HWID]		= "DBGU0",	[DBGU1_HWID]		= "DBGU1",	[OSSSYS_HWID]		= "OSSSYS",	[HDP_HWID]		= "HDP",	[SDMA0_HWID]		= "SDMA0",	[SDMA1_HWID]		= "SDMA1",	[SDMA2_HWID]		= "SDMA2",	[SDMA3_HWID]		= "SDMA3",	[LSDMA_HWID]		= "LSDMA",	[ISP_HWID]		= "ISP",	[DBGU_IO_HWID]		= "DBGU_IO",	[DF_HWID]		= "DF",	[CLKB_HWID]		= "CLKB",	[FCH_HWID]		= "FCH",	[DFX_DAP_HWID]		= "DFX_DAP",	[L1IMU_PCIE_HWID]	= "L1IMU_PCIE",	[L1IMU_NBIF_HWID]	= "L1IMU_NBIF",	[L1IMU_IOAGR_HWID]	= "L1IMU_IOAGR",	[L1IMU3_HWID]		= "L1IMU3",	[L1IMU4_HWID]		= "L1IMU4",	[L1IMU5_HWID]		= "L1IMU5",	[L1IMU6_HWID]		= "L1IMU6",	[L1IMU7_HWID]		= "L1IMU7",	[L1IMU8_HWID]		= "L1IMU8",	[L1IMU9_HWID]		= "L1IMU9",	[L1IMU10_HWID]		= "L1IMU10",	[L1IMU11_HWID]		= "L1IMU11",	[L1IMU12_HWID]		= "L1IMU12",	[L1IMU13_HWID]		= "L1IMU13",	[L1IMU14_HWID]		= "L1IMU14",	[L1IMU15_HWID]		= "L1IMU15",	[WAFLC_HWID]		= "WAFLC",	[FCH_USB_PD_HWID]	= "FCH_USB_PD",	[PCIE_HWID]		= "PCIE",	[PCS_HWID]		= "PCS",	[DDCL_HWID]		= "DDCL",	[SST_HWID]		= "SST",	[IOAGR_HWID]		= "IOAGR",	[NBIF_HWID]		= "NBIF",	[IOAPIC_HWID]		= "IOAPIC",	[SYSTEMHUB_HWID]	= "SYSTEMHUB",	[NTBCCP_HWID]		= "NTBCCP",	[UMC_HWID]		= "UMC",	[SATA_HWID]		= "SATA",	[USB_HWID]		= "USB",	[CCXSEC_HWID]		= "CCXSEC",	[XGMI_HWID]		= "XGMI",	[XGBE_HWID]		= "XGBE",	[MP0_HWID]		= "MP0",	[VPE_HWID]		= "VPE",}; static int hw_id_map[MAX_HWIP] = {	[GC_HWIP]	= GC_HWID,	[HDP_HWIP]	= HDP_HWID,	[SDMA0_HWIP]	= SDMA0_HWID,	[SDMA1_HWIP]	= SDMA1_HWID,	[SDMA2_HWIP]    = SDMA2_HWID,	[SDMA3_HWIP]    = SDMA3_HWID,	[LSDMA_HWIP]    = LSDMA_HWID,	[MMHUB_HWIP]	= MMHUB_HWID,	[ATHUB_HWIP]	= ATHUB_HWID,	[NBIO_HWIP]	= NBIF_HWID,	[MP0_HWIP]	= MP0_HWID,	[MP1_HWIP]	= MP1_HWID,	[UVD_HWIP]	= UVD_HWID,	[VCE_HWIP]	= VCE_HWID,	[DF_HWIP]	= DF_HWID,	[DCE_HWIP]	= DMU_HWID,	[OSSSYS_HWIP]	= OSSSYS_HWID,	[SMUIO_HWIP]	= SMUIO_HWID,	[PWR_HWIP]	= PWR_HWID,	[NBIF_HWIP]	= NBIF_HWID,	[THM_HWIP]	= THM_HWID,	[CLK_HWIP]	= CLKA_HWID,	[UMC_HWIP]	= UMC_HWID,	[XGMI_HWIP]	= XGMI_HWID,	[DCI_HWIP]	= DCI_HWID,	[PCIE_HWIP]	= PCIE_HWID,	[VPE_HWIP]	= VPE_HWID,	[ISP_HWIP]	= ISP_HWID,}; static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary){	u64 tmr_offset, tmr_size, pos;	void *discv_regn;	int ret; 	ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);	if (ret)		return ret; 	pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 	/* This region is read-only and reserved from system use */	discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC);	if (discv_regn) {		memcpy(binary, discv_regn, adev->mman.discovery_tmr_size);		memunmap(discv_regn);		return 0;	} 	return -ENOENT;} #define IP_DISCOVERY_V2		2#define IP_DISCOVERY_V4		4 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,						 uint8_t *binary){	uint64_t vram_size;	u32 msg;	int i, ret = 0; 	if (!amdgpu_sriov_vf(adev)) {		/* It can take up to a second for IFWI init to complete on some dGPUs,		 * but generally it should be in the 60-100ms range.  Normally this starts		 * as soon as the device gets power so by the time the OS loads this has long		 * completed.  However, when a card is hotplugged via e.g., USB4, we need to		 * wait for this to complete.  Once the C2PMSG is updated, we can		 * continue.		 */ 		for (i = 0; i < 1000; i++) {			msg = RREG32(mmMP0_SMN_C2PMSG_33);			if (msg & 0x80000000)				break;			msleep(1);		}	} 	vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; 	if (vram_size) {		uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;		amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,					  adev->mman.discovery_tmr_size, false);	} else {		ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);	} 	return ret;} static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary){	const struct firmware *fw;	const char *fw_name;	int r; 	switch (amdgpu_discovery) {	case 2:		fw_name = FIRMWARE_IP_DISCOVERY;		break;	default:		dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");		return -EINVAL;	} 	r = request_firmware(&fw, fw_name, adev->dev);	if (r) {		dev_err(adev->dev, "can't load firmware \"%s\"\n",			fw_name);		return r;	} 	memcpy((u8 *)binary, (u8 *)fw->data, fw->size);	release_firmware(fw); 	return 0;} static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size){	uint16_t checksum = 0;	int i; 	for (i = 0; i < size; i++)		checksum += data[i]; 	return checksum;} static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,						    uint16_t expected){	return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);} static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary){	struct binary_header *bhdr;	bhdr = (struct binary_header *)binary; 	return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);} static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev){	/*	 * So far, apply this quirk only on those Navy Flounder boards which	 * have a bad harvest table of VCN config.	 */	if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&	    (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {		switch (adev->pdev->revision) {		case 0xC1:		case 0xC2:		case 0xC3:		case 0xC5:		case 0xC7:		case 0xCF:		case 0xDF:			adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;			adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;			break;		default:			break;		}	}} static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,					   struct binary_header *bhdr){	struct table_info *info;	uint16_t checksum;	uint16_t offset; 	info = &bhdr->table_list[NPS_INFO];	offset = le16_to_cpu(info->offset);	checksum = le16_to_cpu(info->checksum); 	struct nps_info_header *nhdr =		(struct nps_info_header *)(adev->mman.discovery_bin + offset); 	if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {		dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");		return -EINVAL;	} 	if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,					      le32_to_cpu(nhdr->size_bytes),					      checksum)) {		dev_dbg(adev->dev, "invalid nps info data table checksum\n");		return -EINVAL;	} 	return 0;} static int amdgpu_discovery_init(struct amdgpu_device *adev){	struct table_info *info;	struct binary_header *bhdr;	uint16_t offset;	uint16_t size;	uint16_t checksum;	int r; 	adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;	adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);	if (!adev->mman.discovery_bin)		return -ENOMEM; 	/* Read from file if it is the preferred option */	if (amdgpu_discovery == 2) {		dev_info(adev->dev, "use ip discovery information from file");		r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin); 		if (r) {			dev_err(adev->dev, "failed to read ip discovery binary from file\n");			r = -EINVAL;			goto out;		} 	} else {		r = amdgpu_discovery_read_binary_from_mem(			adev, adev->mman.discovery_bin);		if (r)			goto out;	} 	/* check the ip discovery binary signature */	if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {		dev_err(adev->dev,			"get invalid ip discovery binary signature\n");		r = -EINVAL;		goto out;	} 	bhdr = (struct binary_header *)adev->mman.discovery_bin; 	offset = offsetof(struct binary_header, binary_checksum) +		sizeof(bhdr->binary_checksum);	size = le16_to_cpu(bhdr->binary_size) - offset;	checksum = le16_to_cpu(bhdr->binary_checksum); 	if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,					      size, checksum)) {		dev_err(adev->dev, "invalid ip discovery binary checksum\n");		r = -EINVAL;		goto out;	} 	info = &bhdr->table_list[IP_DISCOVERY];	offset = le16_to_cpu(info->offset);	checksum = le16_to_cpu(info->checksum); 	if (offset) {		struct ip_discovery_header *ihdr =			(struct ip_discovery_header *)(adev->mman.discovery_bin + offset);		if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {			dev_err(adev->dev, "invalid ip discovery data table signature\n");			r = -EINVAL;			goto out;		} 		if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,						      le16_to_cpu(ihdr->size), checksum)) {			dev_err(adev->dev, "invalid ip discovery data table checksum\n");			r = -EINVAL;			goto out;		}	} 	info = &bhdr->table_list[GC];	offset = le16_to_cpu(info->offset);	checksum = le16_to_cpu(info->checksum); 	if (offset) {		struct gpu_info_header *ghdr =			(struct gpu_info_header *)(adev->mman.discovery_bin + offset); 		if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {			dev_err(adev->dev, "invalid ip discovery gc table id\n");			r = -EINVAL;			goto out;		} 		if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,						      le32_to_cpu(ghdr->size), checksum)) {			dev_err(adev->dev, "invalid gc data table checksum\n");			r = -EINVAL;			goto out;		}	}

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