/* * Copyright 2009 Jerome Glisse. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * *//* * Authors: *    Jerome Glisse <glisse@freedesktop.org> *    Dave Airlie */#include <linux/seq_file.h>#include <linux/atomic.h>#include <linux/wait.h>#include <linux/kref.h>#include <linux/slab.h>#include <linux/firmware.h>#include <linux/pm_runtime.h> #include <drm/drm_drv.h>#include "amdgpu.h"#include "amdgpu_trace.h"#include "amdgpu_reset.h" /* * Fences mark an event in the GPUs pipeline and are used * for GPU/CPU synchronization.  When the fence is written, * it is expected that all buffers associated with that fence * are no longer in use by the associated ring on the GPU and * that the relevant GPU caches have been flushed. */ struct amdgpu_fence {	struct dma_fence base; 	/* RB, DMA, etc. */	struct amdgpu_ring		*ring;	ktime_t				start_timestamp;}; static struct kmem_cache *amdgpu_fence_slab; int amdgpu_fence_slab_init(void){	amdgpu_fence_slab = KMEM_CACHE(amdgpu_fence, SLAB_HWCACHE_ALIGN);	if (!amdgpu_fence_slab)		return -ENOMEM;	return 0;} void amdgpu_fence_slab_fini(void){	rcu_barrier();	kmem_cache_destroy(amdgpu_fence_slab);}/* * Cast helper */static const struct dma_fence_ops amdgpu_fence_ops;static const struct dma_fence_ops amdgpu_job_fence_ops;static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f){	struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 	if (__f->base.ops == &amdgpu_fence_ops ||	    __f->base.ops == &amdgpu_job_fence_ops)		return __f; 	return NULL;} /** * amdgpu_fence_write - write a fence value * * @ring: ring the fence is associated with * @seq: sequence number to write * * Writes a fence value to memory (all asics). */static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq){	struct amdgpu_fence_driver *drv = &ring->fence_drv; 	if (drv->cpu_addr)		*drv->cpu_addr = cpu_to_le32(seq);} /** * amdgpu_fence_read - read a fence value * * @ring: ring the fence is associated with * * Reads a fence value from memory (all asics). * Returns the value of the fence read from memory. */static u32 amdgpu_fence_read(struct amdgpu_ring *ring){	struct amdgpu_fence_driver *drv = &ring->fence_drv;	u32 seq = 0; 	if (drv->cpu_addr)		seq = le32_to_cpu(*drv->cpu_addr);	else		seq = atomic_read(&drv->last_seq); 	return seq;} /** * amdgpu_fence_emit - emit a fence on the requested ring * * @ring: ring the fence is associated with * @f: resulting fence object * @job: job the fence is embedded in * @flags: flags to pass into the subordinate .emit_fence() call * * Emits a fence command on the requested ring (all asics). * Returns 0 on success, -ENOMEM on failure. */int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,		      unsigned int flags){	struct amdgpu_device *adev = ring->adev;	struct dma_fence *fence;	struct amdgpu_fence *am_fence;	struct dma_fence __rcu **ptr;	uint32_t seq;	int r; 	if (job == NULL) {		/* create a sperate hw fence */		am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);		if (am_fence == NULL)			return -ENOMEM;		fence = &am_fence->base;		am_fence->ring = ring;	} else {		/* take use of job-embedded fence */		fence = &job->hw_fence;	} 	seq = ++ring->fence_drv.sync_seq;	if (job && job->job_run_counter) {		/* reinit seq for resubmitted jobs */		fence->seqno = seq;		/* TO be inline with external fence creation and other drivers */		dma_fence_get(fence);	} else {		if (job) {			dma_fence_init(fence, &amdgpu_job_fence_ops,				       &ring->fence_drv.lock,				       adev->fence_context + ring->idx, seq);			/* Against remove in amdgpu_job_{free, free_cb} */			dma_fence_get(fence);		} else {			dma_fence_init(fence, &amdgpu_fence_ops,				       &ring->fence_drv.lock,				       adev->fence_context + ring->idx, seq);		}	} 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,			       seq, flags | AMDGPU_FENCE_FLAG_INT);	pm_runtime_get_noresume(adev_to_drm(adev)->dev);	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];	if (unlikely(rcu_dereference_protected(*ptr, 1))) {		struct dma_fence *old; 		rcu_read_lock();		old = dma_fence_get_rcu_safe(ptr);		rcu_read_unlock(); 		if (old) {			r = dma_fence_wait(old, false);			dma_fence_put(old);			if (r)				return r;		}	} 	to_amdgpu_fence(fence)->start_timestamp = ktime_get(); 	/* This function can't be called concurrently anyway, otherwise	 * emitting the fence would mess up the hardware ring buffer.	 */	rcu_assign_pointer(*ptr, dma_fence_get(fence)); 	*f = fence; 	return 0;} /** * amdgpu_fence_emit_polling - emit a fence on the requeste ring * * @ring: ring the fence is associated with * @s: resulting sequence number * @timeout: the timeout for waiting in usecs * * Emits a fence command on the requested ring (all asics). * Used For polling fence. * Returns 0 on success, -ENOMEM on failure. */int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,			      uint32_t timeout){	uint32_t seq;	signed long r; 	if (!s)		return -EINVAL; 	seq = ++ring->fence_drv.sync_seq;	r = amdgpu_fence_wait_polling(ring,				      seq - ring->fence_drv.num_fences_mask,				      timeout);	if (r < 1)		return -ETIMEDOUT; 	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,			       seq, 0); 	*s = seq; 	return 0;} /** * amdgpu_fence_schedule_fallback - schedule fallback check * * @ring: pointer to struct amdgpu_ring * * Start a timer as fallback to our interrupts. */static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring){	mod_timer(&ring->fence_drv.fallback_timer,		  jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);} /** * amdgpu_fence_process - check for fence activity * * @ring: pointer to struct amdgpu_ring * * Checks the current fence value and calculates the last * signalled fence value. Wakes the fence queue if the * sequence number has increased. * * Returns true if fence was processed */bool amdgpu_fence_process(struct amdgpu_ring *ring){	struct amdgpu_fence_driver *drv = &ring->fence_drv;	struct amdgpu_device *adev = ring->adev;	uint32_t seq, last_seq; 	do {		last_seq = atomic_read(&ring->fence_drv.last_seq);		seq = amdgpu_fence_read(ring); 	} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq); 	if (del_timer(&ring->fence_drv.fallback_timer) &&	    seq != ring->fence_drv.sync_seq)		amdgpu_fence_schedule_fallback(ring); 	if (unlikely(seq == last_seq))		return false; 	last_seq &= drv->num_fences_mask;	seq &= drv->num_fences_mask; 	do {		struct dma_fence *fence, **ptr; 		++last_seq;		last_seq &= drv->num_fences_mask;		ptr = &drv->fences[last_seq]; 		/* There is always exactly one thread signaling this fence slot */		fence = rcu_dereference_protected(*ptr, 1);		RCU_INIT_POINTER(*ptr, NULL); 		if (!fence)			continue; 		dma_fence_signal(fence);		dma_fence_put(fence);		pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);	} while (last_seq != seq); 	return true;} /** * amdgpu_fence_fallback - fallback for hardware interrupts * * @t: timer context used to obtain the pointer to ring structure * * Checks for fence activity. */static void amdgpu_fence_fallback(struct timer_list *t){	struct amdgpu_ring *ring = from_timer(ring, t,					      fence_drv.fallback_timer); 	if (amdgpu_fence_process(ring))		DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);} /** * amdgpu_fence_wait_empty - wait for all fences to signal * * @ring: ring index the fence is associated with * * Wait for all fences on the requested ring to signal (all asics). * Returns 0 if the fences have passed, error for all other cases. */int amdgpu_fence_wait_empty(struct amdgpu_ring *ring){	uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);	struct dma_fence *fence, **ptr;	int r; 	if (!seq)		return 0; 	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];	rcu_read_lock();	fence = rcu_dereference(*ptr);	if (!fence || !dma_fence_get_rcu(fence)) {		rcu_read_unlock();		return 0;	}	rcu_read_unlock(); 	r = dma_fence_wait(fence, false);	dma_fence_put(fence);	return r;} /** * amdgpu_fence_wait_polling - busy wait for givn sequence number * * @ring: ring index the fence is associated with * @wait_seq: sequence number to wait * @timeout: the timeout for waiting in usecs * * Wait for all fences on the requested ring to signal (all asics). * Returns left time if no timeout, 0 or minus if timeout. */signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,				      uint32_t wait_seq,				      signed long timeout){ 	while ((int32_t)(wait_seq - amdgpu_fence_read(ring)) > 0 && timeout > 0) {		udelay(2);		timeout -= 2;	}	return timeout > 0 ? timeout : 0;}/** * amdgpu_fence_count_emitted - get the count of emitted fences * * @ring: ring the fence is associated with * * Get the number of fences emitted on the requested ring (all asics). * Returns the number of emitted fences on the ring.  Used by the * dynpm code to ring track activity. */unsigned int amdgpu_fence_count_emitted(struct amdgpu_ring *ring){	uint64_t emitted; 	/* We are not protected by ring lock when reading the last sequence	 * but it's ok to report slightly wrong fence count here.	 */	emitted = 0x100000000ull;	emitted -= atomic_read(&ring->fence_drv.last_seq);	emitted += READ_ONCE(ring->fence_drv.sync_seq);	return lower_32_bits(emitted);} /** * amdgpu_fence_last_unsignaled_time_us - the time fence emitted until now * @ring: ring the fence is associated with * * Find the earliest fence unsignaled until now, calculate the time delta * between the time fence emitted and now. */u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring){	struct amdgpu_fence_driver *drv = &ring->fence_drv;	struct dma_fence *fence;	uint32_t last_seq, sync_seq; 	last_seq = atomic_read(&ring->fence_drv.last_seq);	sync_seq = READ_ONCE(ring->fence_drv.sync_seq);	if (last_seq == sync_seq)		return 0; 	++last_seq;	last_seq &= drv->num_fences_mask;	fence = drv->fences[last_seq];	if (!fence)		return 0; 	return ktime_us_delta(ktime_get(),		to_amdgpu_fence(fence)->start_timestamp);} /** * amdgpu_fence_update_start_timestamp - update the timestamp of the fence * @ring: ring the fence is associated with * @seq: the fence seq number to update. * @timestamp: the start timestamp to update. * * The function called at the time the fence and related ib is about to * resubmit to gpu in MCBP scenario. Thus we do not consider race condition * with amdgpu_fence_process to modify the same fence. */void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, ktime_t timestamp){	struct amdgpu_fence_driver *drv = &ring->fence_drv;	struct dma_fence *fence; 	seq &= drv->num_fences_mask;	fence = drv->fences[seq];	if (!fence)		return; 	to_amdgpu_fence(fence)->start_timestamp = timestamp;} /** * amdgpu_fence_driver_start_ring - make the fence driver * ready for use on the requested ring. * * @ring: ring to start the fence driver on * @irq_src: interrupt source to use for this ring * @irq_type: interrupt type to use for this ring * * Make the fence driver ready for processing (all asics). * Not all asics have all rings, so each asic will only * start the fence driver on the rings it has. * Returns 0 for success, errors for failure. */int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,				   struct amdgpu_irq_src *irq_src,				   unsigned int irq_type){	struct amdgpu_device *adev = ring->adev;	uint64_t index; 	if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {		ring->fence_drv.cpu_addr = ring->fence_cpu_addr;		ring->fence_drv.gpu_addr = ring->fence_gpu_addr;	} else {		/* put fence directly behind firmware */		index = ALIGN(adev->uvd.fw->size, 8);		ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;		ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;	}	amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq)); 	ring->fence_drv.irq_src = irq_src;	ring->fence_drv.irq_type = irq_type;	ring->fence_drv.initialized = true; 	DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",		      ring->name, ring->fence_drv.gpu_addr);	return 0;} /** * amdgpu_fence_driver_init_ring - init the fence driver * for the requested ring. *

Lines 1–500 of 1007. Load more