/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#include <linux/power_supply.h>#include <linux/kthread.h>#include <linux/module.h>#include <linux/console.h>#include <linux/slab.h>#include <linux/iommu.h>#include <linux/pci.h>#include <linux/pci-p2pdma.h>#include <linux/apple-gmux.h> #include <drm/drm_aperture.h>#include <drm/drm_atomic_helper.h>#include <drm/drm_crtc_helper.h>#include <drm/drm_fb_helper.h>#include <drm/drm_probe_helper.h>#include <drm/amdgpu_drm.h>#include <linux/device.h>#include <linux/vgaarb.h>#include <linux/vga_switcheroo.h>#include <linux/efi.h>#include "amdgpu.h"#include "amdgpu_trace.h"#include "amdgpu_i2c.h"#include "atom.h"#include "amdgpu_atombios.h"#include "amdgpu_atomfirmware.h"#include "amd_pcie.h"#ifdef CONFIG_DRM_AMDGPU_SI#include "si.h"#endif#ifdef CONFIG_DRM_AMDGPU_CIK#include "cik.h"#endif#include "vi.h"#include "soc15.h"#include "nv.h"#include "bif/bif_4_1_d.h"#include <linux/firmware.h>#include "amdgpu_vf_error.h" #include "amdgpu_amdkfd.h"#include "amdgpu_pm.h" #include "amdgpu_xgmi.h"#include "amdgpu_ras.h"#include "amdgpu_pmu.h"#include "amdgpu_fru_eeprom.h"#include "amdgpu_reset.h"#include "amdgpu_virt.h" #include <linux/suspend.h>#include <drm/task_barrier.h>#include <linux/pm_runtime.h> #include <drm/drm_drv.h> #if IS_ENABLED(CONFIG_X86)#include <asm/intel-family.h>#endif MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin"); #define AMDGPU_RESUME_MS		2000#define AMDGPU_MAX_RETRY_LIMIT		2#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL) static const struct drm_driver amdgpu_kms_driver; const char *amdgpu_asic_name[] = {	"TAHITI",	"PITCAIRN",	"VERDE",	"OLAND",	"HAINAN",	"BONAIRE",	"KAVERI",	"KABINI",	"HAWAII",	"MULLINS",	"TOPAZ",	"TONGA",	"FIJI",	"CARRIZO",	"STONEY",	"POLARIS10",	"POLARIS11",	"POLARIS12",	"VEGAM",	"VEGA10",	"VEGA12",	"VEGA20",	"RAVEN",	"ARCTURUS",	"RENOIR",	"ALDEBARAN",	"NAVI10",	"CYAN_SKILLFISH",	"NAVI14",	"NAVI12",	"SIENNA_CICHLID",	"NAVY_FLOUNDER",	"VANGOGH",	"DIMGREY_CAVEFISH",	"BEIGE_GOBY",	"YELLOW_CARP",	"IP DISCOVERY",	"LAST",}; /** * DOC: pcie_replay_count * * The amdgpu driver provides a sysfs API for reporting the total number * of PCIe replays (NAKs) * The file pcie_replay_count is used for this and returns the total * number of replays as a sum of the NAKs generated and NAKs received */ static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,		struct device_attribute *attr, char *buf){	struct drm_device *ddev = dev_get_drvdata(dev);	struct amdgpu_device *adev = drm_to_adev(ddev);	uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); 	return sysfs_emit(buf, "%llu\n", cnt);} static DEVICE_ATTR(pcie_replay_count, 0444,		amdgpu_device_get_pcie_replay_count, NULL); static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,					  struct bin_attribute *attr, char *buf,					  loff_t ppos, size_t count){	struct device *dev = kobj_to_dev(kobj);	struct drm_device *ddev = dev_get_drvdata(dev);	struct amdgpu_device *adev = drm_to_adev(ddev);	ssize_t bytes_read; 	switch (ppos) {	case AMDGPU_SYS_REG_STATE_XGMI:		bytes_read = amdgpu_asic_get_reg_state(			adev, AMDGPU_REG_STATE_TYPE_XGMI, buf, count);		break;	case AMDGPU_SYS_REG_STATE_WAFL:		bytes_read = amdgpu_asic_get_reg_state(			adev, AMDGPU_REG_STATE_TYPE_WAFL, buf, count);		break;	case AMDGPU_SYS_REG_STATE_PCIE:		bytes_read = amdgpu_asic_get_reg_state(			adev, AMDGPU_REG_STATE_TYPE_PCIE, buf, count);		break;	case AMDGPU_SYS_REG_STATE_USR:		bytes_read = amdgpu_asic_get_reg_state(			adev, AMDGPU_REG_STATE_TYPE_USR, buf, count);		break;	case AMDGPU_SYS_REG_STATE_USR_1:		bytes_read = amdgpu_asic_get_reg_state(			adev, AMDGPU_REG_STATE_TYPE_USR_1, buf, count);		break;	default:		return -EINVAL;	} 	return bytes_read;} BIN_ATTR(reg_state, 0444, amdgpu_sysfs_reg_state_get, NULL,	 AMDGPU_SYS_REG_STATE_END); int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev){	int ret; 	if (!amdgpu_asic_get_reg_state_supported(adev))		return 0; 	ret = sysfs_create_bin_file(&adev->dev->kobj, &bin_attr_reg_state); 	return ret;} void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev){	if (!amdgpu_asic_get_reg_state_supported(adev))		return;	sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state);} /** * DOC: board_info * * The amdgpu driver provides a sysfs API for giving board related information. * It provides the form factor information in the format * *   type : form factor * * Possible form factor values * * - "cem"		- PCIE CEM card * - "oam"		- Open Compute Accelerator Module * - "unknown"	- Not known * */ static ssize_t amdgpu_device_get_board_info(struct device *dev,					    struct device_attribute *attr,					    char *buf){	struct drm_device *ddev = dev_get_drvdata(dev);	struct amdgpu_device *adev = drm_to_adev(ddev);	enum amdgpu_pkg_type pkg_type = AMDGPU_PKG_TYPE_CEM;	const char *pkg; 	if (adev->smuio.funcs && adev->smuio.funcs->get_pkg_type)		pkg_type = adev->smuio.funcs->get_pkg_type(adev); 	switch (pkg_type) {	case AMDGPU_PKG_TYPE_CEM:		pkg = "cem";		break;	case AMDGPU_PKG_TYPE_OAM:		pkg = "oam";		break;	default:		pkg = "unknown";		break;	} 	return sysfs_emit(buf, "%s : %s\n", "type", pkg);} static DEVICE_ATTR(board_info, 0444, amdgpu_device_get_board_info, NULL); static struct attribute *amdgpu_board_attrs[] = {	&dev_attr_board_info.attr,	NULL,}; static umode_t amdgpu_board_attrs_is_visible(struct kobject *kobj,					     struct attribute *attr, int n){	struct device *dev = kobj_to_dev(kobj);	struct drm_device *ddev = dev_get_drvdata(dev);	struct amdgpu_device *adev = drm_to_adev(ddev); 	if (adev->flags & AMD_IS_APU)		return 0; 	return attr->mode;} static const struct attribute_group amdgpu_board_attrs_group = {	.attrs = amdgpu_board_attrs,	.is_visible = amdgpu_board_attrs_is_visible}; static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);  /** * amdgpu_device_supports_px - Is the device a dGPU with ATPX power control * * @dev: drm_device pointer * * Returns true if the device is a dGPU with ATPX power control, * otherwise return false. */bool amdgpu_device_supports_px(struct drm_device *dev){	struct amdgpu_device *adev = drm_to_adev(dev); 	if ((adev->flags & AMD_IS_PX) && !amdgpu_is_atpx_hybrid())		return true;	return false;} /** * amdgpu_device_supports_boco - Is the device a dGPU with ACPI power resources * * @dev: drm_device pointer * * Returns true if the device is a dGPU with ACPI power control, * otherwise return false. */bool amdgpu_device_supports_boco(struct drm_device *dev){	struct amdgpu_device *adev = drm_to_adev(dev); 	if (adev->has_pr3 ||	    ((adev->flags & AMD_IS_PX) && amdgpu_is_atpx_hybrid()))		return true;	return false;} /** * amdgpu_device_supports_baco - Does the device support BACO * * @dev: drm_device pointer * * Returns true if the device supporte BACO, * otherwise return false. */bool amdgpu_device_supports_baco(struct drm_device *dev){	struct amdgpu_device *adev = drm_to_adev(dev); 	return amdgpu_asic_supports_baco(adev);} /** * amdgpu_device_supports_smart_shift - Is the device dGPU with * smart shift support * * @dev: drm_device pointer * * Returns true if the device is a dGPU with Smart Shift support, * otherwise returns false. */bool amdgpu_device_supports_smart_shift(struct drm_device *dev){	return (amdgpu_device_supports_boco(dev) &&		amdgpu_acpi_is_power_shift_control_supported());} /* * VRAM access helper functions */ /** * amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA * * @adev: amdgpu_device pointer * @pos: offset of the buffer in vram * @buf: virtual address of the buffer in system memory * @size: read/write size, sizeof(@buf) must > @size * @write: true - write to vram, otherwise - read from vram */void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,			     void *buf, size_t size, bool write){	unsigned long flags;	uint32_t hi = ~0, tmp = 0;	uint32_t *data = buf;	uint64_t last;	int idx; 	if (!drm_dev_enter(adev_to_drm(adev), &idx))		return; 	BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4)); 	spin_lock_irqsave(&adev->mmio_idx_lock, flags);	for (last = pos + size; pos < last; pos += 4) {		tmp = pos >> 31; 		WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);		if (tmp != hi) {			WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);			hi = tmp;		}		if (write)			WREG32_NO_KIQ(mmMM_DATA, *data++);		else			*data++ = RREG32_NO_KIQ(mmMM_DATA);	} 	spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);	drm_dev_exit(idx);} /** * amdgpu_device_aper_access - access vram by vram aperature * * @adev: amdgpu_device pointer * @pos: offset of the buffer in vram * @buf: virtual address of the buffer in system memory * @size: read/write size, sizeof(@buf) must > @size * @write: true - write to vram, otherwise - read from vram * * The return value means how many bytes have been transferred. */size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,				 void *buf, size_t size, bool write){#ifdef CONFIG_64BIT	void __iomem *addr;	size_t count = 0;	uint64_t last; 	if (!adev->mman.aper_base_kaddr)		return 0; 	last = min(pos + size, adev->gmc.visible_vram_size);	if (last > pos) {		addr = adev->mman.aper_base_kaddr + pos;		count = last - pos; 		if (write) {			memcpy_toio(addr, buf, count);			/* Make sure HDP write cache flush happens without any reordering			 * after the system memory contents are sent over PCIe device			 */			mb();			amdgpu_device_flush_hdp(adev, NULL);		} else {			amdgpu_device_invalidate_hdp(adev, NULL);			/* Make sure HDP read cache is invalidated before issuing a read			 * to the PCIe device			 */			mb();			memcpy_fromio(buf, addr, count);		} 	} 	return count;#else	return 0;#endif} /** * amdgpu_device_vram_access - read/write a buffer in vram * * @adev: amdgpu_device pointer * @pos: offset of the buffer in vram * @buf: virtual address of the buffer in system memory * @size: read/write size, sizeof(@buf) must > @size * @write: true - write to vram, otherwise - read from vram */void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,			       void *buf, size_t size, bool write){	size_t count; 	/* try to using vram apreature to access vram first */	count = amdgpu_device_aper_access(adev, pos, buf, size, write);	size -= count;	if (size) {		/* using MM to access rest vram */		pos += count;		buf += count;		amdgpu_device_mm_access(adev, pos, buf, size, write);	}} /* * register access helper functions. */ /* Check if hw access should be skipped because of hotplug or device error */bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev){	if (adev->no_hw_access)		return true; #ifdef CONFIG_LOCKDEP	/*	 * This is a bit complicated to understand, so worth a comment. What we assert	 * here is that the GPU reset is not running on another thread in parallel.	 *	 * For this we trylock the read side of the reset semaphore, if that succeeds	 * we know that the reset is not running in paralell.	 *	 * If the trylock fails we assert that we are either already holding the read

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