/* * Copyright 2008 Advanced Micro Devices, Inc. * Copyright 2008 Red Hat Inc. * Copyright 2009 Jerome Glisse. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Dave Airlie *          Alex Deucher *          Jerome Glisse */#ifndef __AMDGPU_H__#define __AMDGPU_H__ #ifdef pr_fmt#undef pr_fmt#endif #define pr_fmt(fmt) "amdgpu: " fmt #include "amdgpu_ctx.h" #include <linux/atomic.h>#include <linux/wait.h>#include <linux/list.h>#include <linux/kref.h>#include <linux/rbtree.h>#include <linux/hashtable.h>#include <linux/dma-fence.h>#include <linux/pci.h> #include <drm/ttm/ttm_bo.h>#include <drm/ttm/ttm_placement.h> #include <drm/amdgpu_drm.h>#include <drm/drm_gem.h>#include <drm/drm_ioctl.h> #include <kgd_kfd_interface.h>#include "dm_pp_interface.h"#include "kgd_pp_interface.h" #include "amd_shared.h"#include "amdgpu_utils.h"#include "amdgpu_mode.h"#include "amdgpu_ih.h"#include "amdgpu_irq.h"#include "amdgpu_ucode.h"#include "amdgpu_ttm.h"#include "amdgpu_psp.h"#include "amdgpu_gds.h"#include "amdgpu_sync.h"#include "amdgpu_ring.h"#include "amdgpu_vm.h"#include "amdgpu_dpm.h"#include "amdgpu_acp.h"#include "amdgpu_uvd.h"#include "amdgpu_vce.h"#include "amdgpu_vcn.h"#include "amdgpu_jpeg.h"#include "amdgpu_vpe.h"#include "amdgpu_umsch_mm.h"#include "amdgpu_gmc.h"#include "amdgpu_gfx.h"#include "amdgpu_sdma.h"#include "amdgpu_lsdma.h"#include "amdgpu_nbio.h"#include "amdgpu_hdp.h"#include "amdgpu_dm.h"#include "amdgpu_virt.h"#include "amdgpu_csa.h"#include "amdgpu_mes_ctx.h"#include "amdgpu_gart.h"#include "amdgpu_debugfs.h"#include "amdgpu_job.h"#include "amdgpu_bo_list.h"#include "amdgpu_gem.h"#include "amdgpu_doorbell.h"#include "amdgpu_amdkfd.h"#include "amdgpu_discovery.h"#include "amdgpu_mes.h"#include "amdgpu_umc.h"#include "amdgpu_mmhub.h"#include "amdgpu_gfxhub.h"#include "amdgpu_df.h"#include "amdgpu_smuio.h"#include "amdgpu_fdinfo.h"#include "amdgpu_mca.h"#include "amdgpu_aca.h"#include "amdgpu_ras.h"#include "amdgpu_cper.h"#include "amdgpu_xcp.h"#include "amdgpu_seq64.h"#include "amdgpu_reg_state.h"#include "amdgpu_userq.h"#include "amdgpu_eviction_fence.h"#include "amdgpu_ip.h"#if defined(CONFIG_DRM_AMD_ISP)#include "amdgpu_isp.h"#endif #define MAX_GPU_INSTANCE		64 #define GFX_SLICE_PERIOD_MS		250 struct amdgpu_gpu_instance {	struct amdgpu_device		*adev;	int				mgpu_fan_enabled;}; struct amdgpu_mgpu_info {	struct amdgpu_gpu_instance	gpu_ins[MAX_GPU_INSTANCE];	struct mutex			mutex;	uint32_t			num_gpu;	uint32_t			num_dgpu;	uint32_t			num_apu;}; enum amdgpu_ss {	AMDGPU_SS_DRV_LOAD,	AMDGPU_SS_DEV_D0,	AMDGPU_SS_DEV_D3,	AMDGPU_SS_DRV_UNLOAD}; struct amdgpu_hwip_reg_entry {	u32		hwip;	u32		inst;	u32		seg;	u32		reg_offset;	const char	*reg_name;}; struct amdgpu_watchdog_timer {	bool timeout_fatal_disable;	uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */}; #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH	256 /* * Modules parameters. */extern int amdgpu_modeset;extern unsigned int amdgpu_vram_limit;extern int amdgpu_vis_vram_limit;extern int amdgpu_gart_size;extern int amdgpu_gtt_size;extern int amdgpu_moverate;extern int amdgpu_audio;extern int amdgpu_disp_priority;extern int amdgpu_hw_i2c;extern int amdgpu_pcie_gen2;extern int amdgpu_msi;extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];extern int amdgpu_dpm;extern int amdgpu_fw_load_type;extern int amdgpu_aspm;extern int amdgpu_runtime_pm;extern uint amdgpu_ip_block_mask;extern int amdgpu_bapm;extern int amdgpu_deep_color;extern int amdgpu_vm_size;extern int amdgpu_vm_block_size;extern int amdgpu_vm_fragment_size;extern int amdgpu_vm_fault_stop;extern int amdgpu_vm_debug;extern int amdgpu_vm_update_mode;extern int amdgpu_exp_hw_support;extern int amdgpu_dc;extern int amdgpu_sched_jobs;extern int amdgpu_sched_hw_submission;extern uint amdgpu_pcie_gen_cap;extern uint amdgpu_pcie_lane_cap;extern u64 amdgpu_cg_mask;extern uint amdgpu_pg_mask;extern uint amdgpu_sdma_phase_quantum;extern char *amdgpu_disable_cu;extern char *amdgpu_virtual_display;extern uint amdgpu_pp_feature_mask;extern uint amdgpu_force_long_training;extern int amdgpu_lbpw;extern int amdgpu_compute_multipipe;extern int amdgpu_gpu_recovery;extern int amdgpu_emu_mode;extern uint amdgpu_smu_memory_pool_size;extern int amdgpu_smu_pptable_id;extern uint amdgpu_dc_feature_mask;extern uint amdgpu_freesync_vid_mode;extern uint amdgpu_dc_debug_mask;extern uint amdgpu_dc_visual_confirm;extern int amdgpu_dm_abm_level;extern int amdgpu_backlight;extern int amdgpu_damage_clips;extern struct amdgpu_mgpu_info mgpu_info;extern int amdgpu_ras_enable;extern uint amdgpu_ras_mask;extern int amdgpu_bad_page_threshold;extern bool amdgpu_ignore_bad_page_threshold;extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;extern int amdgpu_async_gfx_ring;extern int amdgpu_mcbp;extern int amdgpu_discovery;extern int amdgpu_mes;extern int amdgpu_mes_log_enable;extern int amdgpu_mes_kiq;extern int amdgpu_uni_mes;extern int amdgpu_noretry;extern int amdgpu_force_asic_type;extern int amdgpu_smartshift_bias;extern int amdgpu_use_xgmi_p2p;extern int amdgpu_mtype_local;extern int amdgpu_enforce_isolation;#ifdef CONFIG_HSA_AMDextern int sched_policy;extern bool debug_evictions;extern bool no_system_mem_limit;extern int halt_if_hws_hang;extern uint amdgpu_svm_default_granularity;#elsestatic const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;static const bool __maybe_unused debug_evictions; /* = false */static const bool __maybe_unused no_system_mem_limit;static const int __maybe_unused halt_if_hws_hang;#endif#ifdef CONFIG_HSA_AMD_P2Pextern bool pcie_p2p;#endif extern int amdgpu_tmz;extern int amdgpu_reset_method; #ifdef CONFIG_DRM_AMDGPU_SIextern int amdgpu_si_support;#endif#ifdef CONFIG_DRM_AMDGPU_CIKextern int amdgpu_cik_support;#endifextern int amdgpu_num_kcq; #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)extern int amdgpu_vcnfw_log;extern int amdgpu_sg_display;extern int amdgpu_umsch_mm;extern int amdgpu_seamless;extern int amdgpu_umsch_mm_fwlog; extern int amdgpu_user_partt_mode;extern int amdgpu_agp;extern int amdgpu_rebar; extern int amdgpu_wbrf;extern int amdgpu_user_queue; extern uint amdgpu_hdmi_hpd_debounce_delay_ms; #define AMDGPU_VM_MAX_NUM_CTX			4096#define AMDGPU_SG_THRESHOLD			(256*1024*1024)#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */#define AMDGPU_FENCE_JIFFIES_TIMEOUT		(HZ / 2)#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32#define AMDGPUFB_CONN_LIMIT			4#define AMDGPU_BIOS_NUM_SCRATCH			16 #define AMDGPU_VBIOS_VGA_ALLOCATION		(9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ /* hard reset data */#define AMDGPU_ASIC_RESET_DATA                  0x39d5e86b /* reset flags */#define AMDGPU_RESET_GFX			(1 << 0)#define AMDGPU_RESET_COMPUTE			(1 << 1)#define AMDGPU_RESET_DMA			(1 << 2)#define AMDGPU_RESET_CP				(1 << 3)#define AMDGPU_RESET_GRBM			(1 << 4)#define AMDGPU_RESET_DMA1			(1 << 5)#define AMDGPU_RESET_RLC			(1 << 6)#define AMDGPU_RESET_SEM			(1 << 7)#define AMDGPU_RESET_IH				(1 << 8)#define AMDGPU_RESET_VMC			(1 << 9)#define AMDGPU_RESET_MC				(1 << 10)#define AMDGPU_RESET_DISPLAY			(1 << 11)#define AMDGPU_RESET_UVD			(1 << 12)#define AMDGPU_RESET_VCE			(1 << 13)#define AMDGPU_RESET_VCE1			(1 << 14) /* reset mask */#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */#define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ /* max cursor sizes (in pixels) */#define CIK_CURSOR_WIDTH 128#define CIK_CURSOR_HEIGHT 128 /* smart shift bias level limits */#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */#define AMDGPU_SWCTF_EXTRA_DELAY		50 struct amdgpu_xcp_mgr;struct amdgpu_device;struct amdgpu_irq_src;struct amdgpu_fpriv;struct amdgpu_bo_va_mapping;struct kfd_vm_fault_info;struct amdgpu_hive_info;struct amdgpu_reset_context;struct amdgpu_reset_control; enum amdgpu_cp_irq {	AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,	AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,	AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 	AMDGPU_CP_IRQ_LAST}; enum amdgpu_thermal_irq {	AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,	AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 	AMDGPU_THERMAL_IRQ_LAST}; enum amdgpu_kiq_irq {	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,	AMDGPU_CP_KIQ_IRQ_LAST};#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */#define MAX_KIQ_REG_TRY 1000 /* * BIOS. */bool amdgpu_get_bios(struct amdgpu_device *adev);bool amdgpu_read_bios(struct amdgpu_device *adev);bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,				     u8 *bios, u32 length_bytes);void amdgpu_bios_release(struct amdgpu_device *adev);/* * Clocks */ #define AMDGPU_MAX_PPLL 3 struct amdgpu_clock {	struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];	struct amdgpu_pll spll;	struct amdgpu_pll mpll;	/* 10 Khz units */	uint32_t default_mclk;	uint32_t default_sclk;	uint32_t default_dispclk;	uint32_t dp_extclk;	uint32_t max_pixel_clock;}; /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their * locking. * * Principe is simple, we keep a list of sub allocation in offset * order (first entry has offset == 0, last entry has the highest * offset). * * When allocating new object we first check if there is room at * the end total_size - (last_object_offset + last_object_size) >= * alloc_size. If so we allocate new object there. * * When there is not enough room at the end, we start waiting for * each sub object until we reach object_offset+object_size >= * alloc_size, this object then become the sub object we return. * * Alignment can't be bigger than page size. * * Hole are not considered for allocation to keep things simple. * Assumption is that there won't be hole (all object on same * alignment). */ struct amdgpu_sa_manager {	struct drm_suballoc_manager	base;	struct amdgpu_bo		*bo;	uint64_t			gpu_addr;	void				*cpu_ptr;}; /* * IRQS. */ struct amdgpu_flip_work {	struct delayed_work		flip_work;	struct work_struct		unpin_work;	struct amdgpu_device		*adev;	int				crtc_id;	u32				target_vblank;	uint64_t			base;	struct drm_pending_vblank_event *event;	struct amdgpu_bo		*old_abo;	unsigned			shared_count;	struct dma_fence		**shared;	struct dma_fence_cb		cb;	bool				async;}; /* * file private structure */ struct amdgpu_fpriv {	struct amdgpu_vm	vm;	struct amdgpu_bo_va	*prt_va;	struct amdgpu_bo_va	*csa_va;	struct amdgpu_bo_va	*seq64_va;	struct mutex		bo_list_lock;	struct idr		bo_list_handles;	struct amdgpu_ctx_mgr	ctx_mgr;	struct amdgpu_userq_mgr	userq_mgr; 	/* Eviction fence infra */	struct amdgpu_eviction_fence_mgr evf_mgr; 	/** GPU partition selection */	uint32_t		xcp_id;}; int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); /* * Writeback */#define AMDGPU_MAX_WB 1024	/* Reserve at most 1024 WB slots for amdgpu-owned rings. */ /** * amdgpu_wb - This struct is used for small GPU memory allocation. * * This struct is used to allocate a small amount of GPU memory that can be * used to shadow certain states into the memory. This is especially useful for * providing easy CPU access to some states without requiring register access * (e.g., if some block is power gated, reading register may be problematic). * * Note: the term writeback was initially used because many of the amdgpu * components had some level of writeback memory, and this struct initially * described those components. */struct amdgpu_wb { 	/**	 * @wb_obj:	 *	 * Buffer Object used for the writeback memory.	 */	struct amdgpu_bo	*wb_obj; 	/**	 * @wb:	 *	 * Pointer to the first writeback slot. In terms of CPU address	 * this value can be accessed directly by using the offset as an index.	 * For the GPU address, it is necessary to use gpu_addr and the offset.	 */	uint32_t		*wb; 	/**	 * @gpu_addr:	 *	 * Writeback base address in the GPU.	 */

Lines 1–500 of 1742. Load more