/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note *//* * Performance events: * *    Copyright (C) 2008-2009, Linutronix GmbH, Thomas Gleixner <tglx@kernel.org> *    Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar *    Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra * * Data type definitions, declarations, prototypes. * *    Started by: Thomas Gleixner and Ingo Molnar * * For licencing details see kernel-base/COPYING */#ifndef _UAPI_LINUX_PERF_EVENT_H#define _UAPI_LINUX_PERF_EVENT_H #include <linux/types.h>#include <linux/ioctl.h>#include <asm/byteorder.h> /* * User-space ABI bits: */ /* * attr.type */enum perf_type_id {	PERF_TYPE_HARDWARE			= 0,	PERF_TYPE_SOFTWARE			= 1,	PERF_TYPE_TRACEPOINT			= 2,	PERF_TYPE_HW_CACHE			= 3,	PERF_TYPE_RAW				= 4,	PERF_TYPE_BREAKPOINT			= 5, 	PERF_TYPE_MAX,				/* non-ABI */}; /* * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE * * PERF_TYPE_HARDWARE:			0xEEEEEEEE000000AA *					AA: hardware event ID *					EEEEEEEE: PMU type ID * * PERF_TYPE_HW_CACHE:			0xEEEEEEEE00DDCCBB *					BB: hardware cache ID *					CC: hardware cache op ID *					DD: hardware cache op result ID *					EEEEEEEE: PMU type ID * * If the PMU type ID is 0, PERF_TYPE_RAW will be applied. */#define PERF_PMU_TYPE_SHIFT			32#define PERF_HW_EVENT_MASK			0xffffffff /* * Generalized performance event event_id types, used by the * attr.event_id parameter of the sys_perf_event_open() * syscall: */enum perf_hw_id {	/*	 * Common hardware events, generalized by the kernel:	 */	PERF_COUNT_HW_CPU_CYCLES		= 0,	PERF_COUNT_HW_INSTRUCTIONS		= 1,	PERF_COUNT_HW_CACHE_REFERENCES		= 2,	PERF_COUNT_HW_CACHE_MISSES		= 3,	PERF_COUNT_HW_BRANCH_INSTRUCTIONS	= 4,	PERF_COUNT_HW_BRANCH_MISSES		= 5,	PERF_COUNT_HW_BUS_CYCLES		= 6,	PERF_COUNT_HW_STALLED_CYCLES_FRONTEND	= 7,	PERF_COUNT_HW_STALLED_CYCLES_BACKEND	= 8,	PERF_COUNT_HW_REF_CPU_CYCLES		= 9, 	PERF_COUNT_HW_MAX,			/* non-ABI */}; /* * Generalized hardware cache events: * *       { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x *       { read, write, prefetch } x *       { accesses, misses } */enum perf_hw_cache_id {	PERF_COUNT_HW_CACHE_L1D			= 0,	PERF_COUNT_HW_CACHE_L1I			= 1,	PERF_COUNT_HW_CACHE_LL			= 2,	PERF_COUNT_HW_CACHE_DTLB		= 3,	PERF_COUNT_HW_CACHE_ITLB		= 4,	PERF_COUNT_HW_CACHE_BPU			= 5,	PERF_COUNT_HW_CACHE_NODE		= 6, 	PERF_COUNT_HW_CACHE_MAX,		/* non-ABI */}; enum perf_hw_cache_op_id {	PERF_COUNT_HW_CACHE_OP_READ		= 0,	PERF_COUNT_HW_CACHE_OP_WRITE		= 1,	PERF_COUNT_HW_CACHE_OP_PREFETCH		= 2, 	PERF_COUNT_HW_CACHE_OP_MAX,		/* non-ABI */}; enum perf_hw_cache_op_result_id {	PERF_COUNT_HW_CACHE_RESULT_ACCESS	= 0,	PERF_COUNT_HW_CACHE_RESULT_MISS		= 1, 	PERF_COUNT_HW_CACHE_RESULT_MAX,		/* non-ABI */}; /* * Special "software" events provided by the kernel, even if the hardware * does not support performance events. These events measure various * physical and SW events of the kernel (and allow the profiling of them as * well): */enum perf_sw_ids {	PERF_COUNT_SW_CPU_CLOCK			= 0,	PERF_COUNT_SW_TASK_CLOCK		= 1,	PERF_COUNT_SW_PAGE_FAULTS		= 2,	PERF_COUNT_SW_CONTEXT_SWITCHES		= 3,	PERF_COUNT_SW_CPU_MIGRATIONS		= 4,	PERF_COUNT_SW_PAGE_FAULTS_MIN		= 5,	PERF_COUNT_SW_PAGE_FAULTS_MAJ		= 6,	PERF_COUNT_SW_ALIGNMENT_FAULTS		= 7,	PERF_COUNT_SW_EMULATION_FAULTS		= 8,	PERF_COUNT_SW_DUMMY			= 9,	PERF_COUNT_SW_BPF_OUTPUT		= 10,	PERF_COUNT_SW_CGROUP_SWITCHES		= 11, 	PERF_COUNT_SW_MAX,			/* non-ABI */}; /* * Bits that can be set in attr.sample_type to request information * in the overflow packets. */enum perf_event_sample_format {	PERF_SAMPLE_IP				= 1U << 0,	PERF_SAMPLE_TID				= 1U << 1,	PERF_SAMPLE_TIME			= 1U << 2,	PERF_SAMPLE_ADDR			= 1U << 3,	PERF_SAMPLE_READ			= 1U << 4,	PERF_SAMPLE_CALLCHAIN			= 1U << 5,	PERF_SAMPLE_ID				= 1U << 6,	PERF_SAMPLE_CPU				= 1U << 7,	PERF_SAMPLE_PERIOD			= 1U << 8,	PERF_SAMPLE_STREAM_ID			= 1U << 9,	PERF_SAMPLE_RAW				= 1U << 10,	PERF_SAMPLE_BRANCH_STACK		= 1U << 11,	PERF_SAMPLE_REGS_USER			= 1U << 12,	PERF_SAMPLE_STACK_USER			= 1U << 13,	PERF_SAMPLE_WEIGHT			= 1U << 14,	PERF_SAMPLE_DATA_SRC			= 1U << 15,	PERF_SAMPLE_IDENTIFIER			= 1U << 16,	PERF_SAMPLE_TRANSACTION			= 1U << 17,	PERF_SAMPLE_REGS_INTR			= 1U << 18,	PERF_SAMPLE_PHYS_ADDR			= 1U << 19,	PERF_SAMPLE_AUX				= 1U << 20,	PERF_SAMPLE_CGROUP			= 1U << 21,	PERF_SAMPLE_DATA_PAGE_SIZE		= 1U << 22,	PERF_SAMPLE_CODE_PAGE_SIZE		= 1U << 23,	PERF_SAMPLE_WEIGHT_STRUCT		= 1U << 24, 	PERF_SAMPLE_MAX = 1U << 25,		/* non-ABI */}; #define PERF_SAMPLE_WEIGHT_TYPE	(PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) /* * Values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set. * * If the user does not pass priv level information via branch_sample_type, * the kernel uses the event's priv level. Branch and event priv levels do * not have to match. Branch priv level is checked for permissions. * * The branch types can be combined, however BRANCH_ANY covers all types * of branches and therefore it supersedes all the other types. */enum perf_branch_sample_type_shift {	PERF_SAMPLE_BRANCH_USER_SHIFT		=  0, /* user branches */	PERF_SAMPLE_BRANCH_KERNEL_SHIFT		=  1, /* kernel branches */	PERF_SAMPLE_BRANCH_HV_SHIFT		=  2, /* hypervisor branches */ 	PERF_SAMPLE_BRANCH_ANY_SHIFT		=  3, /* any branch types */	PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT	=  4, /* any call branch */	PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT	=  5, /* any return branch */	PERF_SAMPLE_BRANCH_IND_CALL_SHIFT	=  6, /* indirect calls */	PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT	=  7, /* transaction aborts */	PERF_SAMPLE_BRANCH_IN_TX_SHIFT		=  8, /* in transaction */	PERF_SAMPLE_BRANCH_NO_TX_SHIFT		=  9, /* not in transaction */	PERF_SAMPLE_BRANCH_COND_SHIFT		= 10, /* conditional branches */ 	PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT	= 11, /* CALL/RET stack */	PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT	= 12, /* indirect jumps */	PERF_SAMPLE_BRANCH_CALL_SHIFT		= 13, /* direct call */ 	PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT	= 14, /* no flags */	PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT	= 15, /* no cycles */ 	PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT	= 16, /* save branch type */ 	PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT	= 17, /* save low level index of raw branch records */ 	PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT	= 18, /* save privilege mode */ 	PERF_SAMPLE_BRANCH_COUNTERS_SHIFT	= 19, /* save occurrences of events on a branch */ 	PERF_SAMPLE_BRANCH_MAX_SHIFT		/* non-ABI */}; enum perf_branch_sample_type {	PERF_SAMPLE_BRANCH_USER			= 1U << PERF_SAMPLE_BRANCH_USER_SHIFT,	PERF_SAMPLE_BRANCH_KERNEL		= 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT,	PERF_SAMPLE_BRANCH_HV			= 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 	PERF_SAMPLE_BRANCH_ANY			= 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,	PERF_SAMPLE_BRANCH_ANY_CALL		= 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,	PERF_SAMPLE_BRANCH_ANY_RETURN		= 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,	PERF_SAMPLE_BRANCH_IND_CALL		= 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,	PERF_SAMPLE_BRANCH_ABORT_TX		= 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,	PERF_SAMPLE_BRANCH_IN_TX		= 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,	PERF_SAMPLE_BRANCH_NO_TX		= 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,	PERF_SAMPLE_BRANCH_COND			= 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 	PERF_SAMPLE_BRANCH_CALL_STACK		= 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,	PERF_SAMPLE_BRANCH_IND_JUMP		= 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT,	PERF_SAMPLE_BRANCH_CALL			= 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 	PERF_SAMPLE_BRANCH_NO_FLAGS		= 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,	PERF_SAMPLE_BRANCH_NO_CYCLES		= 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 	PERF_SAMPLE_BRANCH_TYPE_SAVE		= 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 	PERF_SAMPLE_BRANCH_HW_INDEX		= 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 	PERF_SAMPLE_BRANCH_PRIV_SAVE		= 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, 	PERF_SAMPLE_BRANCH_COUNTERS		= 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT, 	PERF_SAMPLE_BRANCH_MAX			= 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,}; /* * Common control flow change classifications: */enum {	PERF_BR_UNKNOWN				=  0,	/* Unknown */	PERF_BR_COND				=  1,	/* Conditional */	PERF_BR_UNCOND				=  2,	/* Unconditional  */	PERF_BR_IND				=  3,	/* Indirect */	PERF_BR_CALL				=  4,	/* Function call */	PERF_BR_IND_CALL			=  5,	/* Indirect function call */	PERF_BR_RET				=  6,	/* Function return */	PERF_BR_SYSCALL				=  7,	/* Syscall */	PERF_BR_SYSRET				=  8,	/* Syscall return */	PERF_BR_COND_CALL			=  9,	/* Conditional function call */	PERF_BR_COND_RET			= 10,	/* Conditional function return */	PERF_BR_ERET				= 11,	/* Exception return */	PERF_BR_IRQ				= 12,	/* IRQ */	PERF_BR_SERROR				= 13,	/* System error */	PERF_BR_NO_TX				= 14,	/* Not in transaction */	PERF_BR_EXTEND_ABI			= 15,	/* Extend ABI */	PERF_BR_MAX,}; /* * Common branch speculation outcome classifications: */enum {	PERF_BR_SPEC_NA				= 0,	/* Not available */	PERF_BR_SPEC_WRONG_PATH			= 1,	/* Speculative but on wrong path */	PERF_BR_NON_SPEC_CORRECT_PATH		= 2,	/* Non-speculative but on correct path */	PERF_BR_SPEC_CORRECT_PATH		= 3,	/* Speculative and on correct path */	PERF_BR_SPEC_MAX,}; enum {	PERF_BR_NEW_FAULT_ALGN			= 0,    /* Alignment fault */	PERF_BR_NEW_FAULT_DATA			= 1,    /* Data fault */	PERF_BR_NEW_FAULT_INST			= 2,    /* Inst fault */	PERF_BR_NEW_ARCH_1			= 3,    /* Architecture specific */	PERF_BR_NEW_ARCH_2			= 4,    /* Architecture specific */	PERF_BR_NEW_ARCH_3			= 5,    /* Architecture specific */	PERF_BR_NEW_ARCH_4			= 6,    /* Architecture specific */	PERF_BR_NEW_ARCH_5			= 7,    /* Architecture specific */	PERF_BR_NEW_MAX,}; enum {	PERF_BR_PRIV_UNKNOWN			= 0,	PERF_BR_PRIV_USER			= 1,	PERF_BR_PRIV_KERNEL			= 2,	PERF_BR_PRIV_HV				= 3,}; #define PERF_BR_ARM64_FIQ			PERF_BR_NEW_ARCH_1#define PERF_BR_ARM64_DEBUG_HALT		PERF_BR_NEW_ARCH_2#define PERF_BR_ARM64_DEBUG_EXIT		PERF_BR_NEW_ARCH_3#define PERF_BR_ARM64_DEBUG_INST		PERF_BR_NEW_ARCH_4#define PERF_BR_ARM64_DEBUG_DATA		PERF_BR_NEW_ARCH_5 #define PERF_SAMPLE_BRANCH_PLM_ALL \	(PERF_SAMPLE_BRANCH_USER|\	 PERF_SAMPLE_BRANCH_KERNEL|\	 PERF_SAMPLE_BRANCH_HV) /* * Values to determine ABI of the registers dump. */enum perf_sample_regs_abi {	PERF_SAMPLE_REGS_ABI_NONE		= 0,	PERF_SAMPLE_REGS_ABI_32			= 1,	PERF_SAMPLE_REGS_ABI_64			= 2,}; /* * Values for the memory transaction event qualifier, mostly for * abort events. Multiple bits can be set. */enum {	PERF_TXN_ELISION			= (1 << 0), /* From elision */	PERF_TXN_TRANSACTION			= (1 << 1), /* From transaction */	PERF_TXN_SYNC				= (1 << 2), /* Instruction is related */	PERF_TXN_ASYNC				= (1 << 3), /* Instruction is not related */	PERF_TXN_RETRY				= (1 << 4), /* Retry possible */	PERF_TXN_CONFLICT			= (1 << 5), /* Conflict abort */	PERF_TXN_CAPACITY_WRITE			= (1 << 6), /* Capacity write abort */	PERF_TXN_CAPACITY_READ			= (1 << 7), /* Capacity read abort */ 	PERF_TXN_MAX				= (1 << 8), /* non-ABI */ 	/* Bits 32..63 are reserved for the abort code */ 	PERF_TXN_ABORT_MASK			= (0xffffffffULL << 32),	PERF_TXN_ABORT_SHIFT			= 32,}; /* * The format of the data returned by read() on a perf event fd, * as specified by attr.read_format: * * struct read_format { *	{ u64		value; *	  { u64		time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED *	  { u64		time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING *	  { u64		id;           } && PERF_FORMAT_ID *	  { u64		lost;         } && PERF_FORMAT_LOST *	} && !PERF_FORMAT_GROUP * *	{ u64		nr; *	  { u64		time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED *	  { u64		time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING *	  { u64		value; *	    { u64	id;           } && PERF_FORMAT_ID *	    { u64	lost;         } && PERF_FORMAT_LOST *	  }		cntr[nr]; *	} && PERF_FORMAT_GROUP * }; */enum perf_event_read_format {	PERF_FORMAT_TOTAL_TIME_ENABLED		= 1U << 0,	PERF_FORMAT_TOTAL_TIME_RUNNING		= 1U << 1,	PERF_FORMAT_ID				= 1U << 2,	PERF_FORMAT_GROUP			= 1U << 3,	PERF_FORMAT_LOST			= 1U << 4, 	PERF_FORMAT_MAX = 1U << 5,		/* non-ABI */}; #define PERF_ATTR_SIZE_VER0			 64	/* Size of first published 'struct perf_event_attr' */#define PERF_ATTR_SIZE_VER1			 72	/* Add: config2 */#define PERF_ATTR_SIZE_VER2			 80	/* Add: branch_sample_type */#define PERF_ATTR_SIZE_VER3			 96	/* Add: sample_regs_user */							/* Add: sample_stack_user */#define PERF_ATTR_SIZE_VER4			104	/* Add: sample_regs_intr */#define PERF_ATTR_SIZE_VER5			112	/* Add: aux_watermark */#define PERF_ATTR_SIZE_VER6			120	/* Add: aux_sample_size */#define PERF_ATTR_SIZE_VER7			128	/* Add: sig_data */#define PERF_ATTR_SIZE_VER8			136	/* Add: config3 */#define PERF_ATTR_SIZE_VER9			144	/* add: config4 */ /* * 'struct perf_event_attr' contains various attributes that define * a performance event - most of them hardware related configuration * details, but also a lot of behavioral switches and values implemented * by the kernel. */struct perf_event_attr { 	/*	 * Major type: hardware/software/tracepoint/etc.	 */	__u32			type; 	/*	 * Size of the attr structure, for forward/backwards compatibility.	 */	__u32			size; 	/*	 * Type specific configuration information.	 */	__u64			config; 	union {		__u64		sample_period;		__u64		sample_freq;	}; 	__u64			sample_type;	__u64			read_format; 	__u64			disabled       :  1, /* off by default        */				inherit	       :  1, /* children inherit it   */				pinned	       :  1, /* must always be on PMU */				exclusive      :  1, /* only group on PMU     */				exclude_user   :  1, /* don't count user      */				exclude_kernel :  1, /* ditto kernel          */				exclude_hv     :  1, /* ditto hypervisor      */				exclude_idle   :  1, /* don't count when idle */				mmap           :  1, /* include mmap data     */				comm	       :  1, /* include comm data     */				freq           :  1, /* use freq, not period  */				inherit_stat   :  1, /* per task counts       */				enable_on_exec :  1, /* next exec enables     */				task           :  1, /* trace fork/exit       */				watermark      :  1, /* wakeup_watermark      */				/*				 * precise_ip:				 *				 *  0 - SAMPLE_IP can have arbitrary skid				 *  1 - SAMPLE_IP must have constant skid				 *  2 - SAMPLE_IP requested to have 0 skid				 *  3 - SAMPLE_IP must have 0 skid				 *				 *  See also PERF_RECORD_MISC_EXACT_IP				 */				precise_ip     :  2, /* skid constraint       */				mmap_data      :  1, /* non-exec mmap data    */				sample_id_all  :  1, /* sample_type all events */ 				exclude_host   :  1, /* don't count in host   */				exclude_guest  :  1, /* don't count in guest  */ 				exclude_callchain_kernel : 1, /* exclude kernel callchains */				exclude_callchain_user   : 1, /* exclude user callchains */				mmap2          :  1, /* include mmap with inode data     */				comm_exec      :  1, /* flag comm events that are due to an exec */				use_clockid    :  1, /* use @clockid for time fields */				context_switch :  1, /* context switch data */				write_backward :  1, /* write ring buffer from end to beginning */				namespaces     :  1, /* include namespaces data */				ksymbol        :  1, /* include ksymbol events */				bpf_event      :  1, /* include BPF events */				aux_output     :  1, /* generate AUX records instead of events */				cgroup         :  1, /* include cgroup events */				text_poke      :  1, /* include text poke events */				build_id       :  1, /* use build ID in mmap2 events */				inherit_thread :  1, /* children only inherit if cloned with CLONE_THREAD */				remove_on_exec :  1, /* event is removed from task on exec */				sigtrap        :  1, /* send synchronous SIGTRAP on event */				defer_callchain:  1, /* request PERF_RECORD_CALLCHAIN_DEFERRED records */				defer_output   :  1, /* output PERF_RECORD_CALLCHAIN_DEFERRED records */				__reserved_1   : 24; 	union {		__u32		wakeup_events;	  /* wake up every n events */		__u32		wakeup_watermark; /* bytes before wakeup   */	}; 	__u32			bp_type;	union {		__u64		bp_addr;		__u64		kprobe_func; /* for perf_kprobe */		__u64		uprobe_path; /* for perf_uprobe */		__u64		config1;     /* extension of config */	};	union {		__u64		bp_len;		__u64		kprobe_addr;  /* when kprobe_func == NULL */		__u64		probe_offset; /* for perf_[k,u]probe */		__u64		config2;      /* extension of config1 */	};	__u64	branch_sample_type; /* enum perf_branch_sample_type */ 	/*	 * Defines set of user regs to dump on samples.	 * See asm/perf_regs.h for details.	 */	__u64	sample_regs_user; 	/*	 * Defines size of the user stack to dump on samples.	 */	__u32	sample_stack_user;

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