// SPDX-License-Identifier: GPL-2.0-only/* * Tegra host1x driver * * Copyright (c) 2010-2013, NVIDIA Corporation. */ #include <linux/clk.h>#include <linux/delay.h>#include <linux/dma-mapping.h>#include <linux/io.h>#include <linux/list.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_platform.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/slab.h> #include <soc/tegra/common.h> #define CREATE_TRACE_POINTS#include <trace/events/host1x.h>#undef CREATE_TRACE_POINTS #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)#include <asm/dma-iommu.h>#endif #include "bus.h"#include "channel.h"#include "context.h"#include "debug.h"#include "dev.h"#include "intr.h" #include "hw/host1x01.h"#include "hw/host1x02.h"#include "hw/host1x04.h"#include "hw/host1x05.h"#include "hw/host1x06.h"#include "hw/host1x07.h"#include "hw/host1x08.h" void host1x_common_writel(struct host1x *host1x, u32 v, u32 r){ writel(v, host1x->common_regs + r);} void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r){ writel(v, host1x->hv_regs + r);} u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r){ return readl(host1x->hv_regs + r);} void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r){ void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; writel(v, sync_regs + r);} u32 host1x_sync_readl(struct host1x *host1x, u32 r){ void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; return readl(sync_regs + r);} #ifdef CONFIG_64BITu64 host1x_sync_readq(struct host1x *host1x, u32 r){ void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; return readq(sync_regs + r);}#endif void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r){ writel(v, ch->regs + r);} u32 host1x_ch_readl(struct host1x_channel *ch, u32 r){ return readl(ch->regs + r);} static const struct host1x_info host1x01_info = { .nb_channels = 8, .nb_pts = 32, .nb_mlocks = 16, .nb_bases = 8, .init = host1x01_init, .sync_offset = 0x3000, .dma_mask = DMA_BIT_MASK(32), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = true,}; static const struct host1x_info host1x02_info = { .nb_channels = 9, .nb_pts = 32, .nb_mlocks = 16, .nb_bases = 12, .init = host1x02_init, .sync_offset = 0x3000, .dma_mask = DMA_BIT_MASK(32), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = true,}; static const struct host1x_info host1x04_info = { .nb_channels = 12, .nb_pts = 192, .nb_mlocks = 16, .nb_bases = 64, .init = host1x04_init, .sync_offset = 0x2100, .dma_mask = DMA_BIT_MASK(34), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = false,}; static const struct host1x_info host1x05_info = { .nb_channels = 14, .nb_pts = 192, .nb_mlocks = 16, .nb_bases = 64, .init = host1x05_init, .sync_offset = 0x2100, .dma_mask = DMA_BIT_MASK(34), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = false,}; static const struct host1x_sid_entry tegra186_sid_table[] = { { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 }, { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 }, { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 }, { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 }, { /* ISP */ .base = 0x1ae8, .offset = 0x50, .limit = 0x50 }, { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 }, { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 }, { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 }, { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 }, { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 }, { /* VI 0 */ .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 }, { /* VI 1 */ .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 }, { /* VI 2 */ .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 }, { /* VI 3 */ .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 }, { /* VI 4 */ .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 }, { /* VI 5 */ .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 }, { /* VI 6 */ .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 }, { /* VI 7 */ .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 }, { /* VI 8 */ .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 }, { /* VI 9 */ .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 }, { /* VI 10 */ .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 }, { /* VI 11 */ .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 },}; static const struct host1x_info host1x06_info = { .nb_channels = 63, .nb_pts = 576, .nb_mlocks = 24, .nb_bases = 16, .init = host1x06_init, .sync_offset = 0x0, .dma_mask = DMA_BIT_MASK(40), .has_wide_gather = true, .has_hypervisor = true, .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), .sid_table = tegra186_sid_table, .reserve_vblank_syncpts = false, .skip_reset_assert = true,}; static const struct host1x_sid_entry tegra194_sid_table[] = { { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 }, { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 }, { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 }, { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 }, { /* ISP */ .base = 0x1ae8, .offset = 0x800, .limit = 0x800 }, { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 }, { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 }, { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 }, { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 }, { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 }, { /* VI */ .base = 0x1b80, .offset = 0x800, .limit = 0x800 }, { /* VI_THI */ .base = 0x1b88, .offset = 0x30, .limit = 0x34 }, { /* ISP_THI */ .base = 0x1b90, .offset = 0x30, .limit = 0x34 }, { /* PVA0_CLUSTER */ .base = 0x1b98, .offset = 0x0, .limit = 0x0 }, { /* PVA0_CLUSTER */ .base = 0x1ba0, .offset = 0x0, .limit = 0x0 }, { /* NVDLA0 */ .base = 0x1ba8, .offset = 0x30, .limit = 0x34 }, { /* NVDLA1 */ .base = 0x1bb0, .offset = 0x30, .limit = 0x34 }, { /* NVENC1 */ .base = 0x1bb8, .offset = 0x30, .limit = 0x34 }, { /* NVDEC1 */ .base = 0x1bc0, .offset = 0x30, .limit = 0x34 },}; static const struct host1x_info host1x07_info = { .nb_channels = 63, .nb_pts = 704, .nb_mlocks = 32, .nb_bases = 0, .init = host1x07_init, .sync_offset = 0x0, .dma_mask = DMA_BIT_MASK(40), .has_wide_gather = true, .has_hypervisor = true, .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), .sid_table = tegra194_sid_table, .reserve_vblank_syncpts = false,}; /* * Tegra234 has two stream ID protection tables, one for setting stream IDs * through the channel path via SETSTREAMID, and one for setting them via * MMIO. We program each engine's data stream ID in the channel path table * and firmware stream ID in the MMIO path table. */static const struct host1x_sid_entry tegra234_sid_table[] = { { /* SE1 MMIO */ .base = 0x1650, .offset = 0x90, .limit = 0x90 }, { /* SE1 ch */ .base = 0x1730, .offset = 0x90, .limit = 0x90 }, { /* SE2 MMIO */ .base = 0x1658, .offset = 0x90, .limit = 0x90 }, { /* SE2 ch */ .base = 0x1738, .offset = 0x90, .limit = 0x90 }, { /* SE4 MMIO */ .base = 0x1660, .offset = 0x90, .limit = 0x90 }, { /* SE4 ch */ .base = 0x1740, .offset = 0x90, .limit = 0x90 }, { /* ISP MMIO */ .base = 0x1680, .offset = 0x800, .limit = 0x800 }, { /* VIC MMIO */ .base = 0x1688, .offset = 0x34, .limit = 0x34 }, { /* VIC ch */ .base = 0x17b8, .offset = 0x30, .limit = 0x30 }, { /* NVENC MMIO */ .base = 0x1690, .offset = 0x34, .limit = 0x34 }, { /* NVENC ch */ .base = 0x17c0, .offset = 0x30, .limit = 0x30 }, { /* NVDEC MMIO */ .base = 0x1698, .offset = 0x34, .limit = 0x34 }, { /* NVDEC ch */ .base = 0x17c8, .offset = 0x30, .limit = 0x30 }, { /* NVJPG MMIO */ .base = 0x16a0, .offset = 0x34, .limit = 0x34 }, { /* NVJPG ch */ .base = 0x17d0, .offset = 0x30, .limit = 0x30 }, { /* TSEC MMIO */ .base = 0x16a8, .offset = 0x30, .limit = 0x34 }, { /* NVJPG1 MMIO */ .base = 0x16b0, .offset = 0x34, .limit = 0x34 }, { /* NVJPG1 ch */ .base = 0x17a8, .offset = 0x30, .limit = 0x30 }, { /* VI MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 }, { /* VI_THI MMIO */ .base = 0x16c0, .offset = 0x30, .limit = 0x34 }, { /* ISP_THI MMIO */ .base = 0x16c8, .offset = 0x30, .limit = 0x34 }, { /* NVDLA MMIO */ .base = 0x16d8, .offset = 0x30, .limit = 0x34 }, { /* NVDLA ch */ .base = 0x17e0, .offset = 0x30, .limit = 0x34 }, { /* NVDLA1 MMIO */ .base = 0x16e0, .offset = 0x30, .limit = 0x34 }, { /* NVDLA1 ch */ .base = 0x17e8, .offset = 0x30, .limit = 0x34 }, { /* OFA MMIO */ .base = 0x16e8, .offset = 0x34, .limit = 0x34 }, { /* OFA ch */ .base = 0x1768, .offset = 0x30, .limit = 0x30 }, { /* VI2 MMIO */ .base = 0x16f0, .offset = 0x800, .limit = 0x800 }, { /* VI2_THI MMIO */ .base = 0x16f8, .offset = 0x30, .limit = 0x34 },}; static const struct host1x_info host1x08_info = { .nb_channels = 63, .nb_pts = 1024, .nb_mlocks = 24, .nb_bases = 0, .init = host1x08_init, .sync_offset = 0x0, .dma_mask = DMA_BIT_MASK(40), .has_wide_gather = true, .has_hypervisor = true, .has_common = true, .num_sid_entries = ARRAY_SIZE(tegra234_sid_table), .sid_table = tegra234_sid_table, .streamid_vm_table = { 0x1004, 128 }, .classid_vm_table = { 0x1404, 25 }, .mmio_vm_table = { 0x1504, 25 }, .reserve_vblank_syncpts = false,}; static const struct of_device_id host1x_of_match[] = { { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, }, { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, { },};MODULE_DEVICE_TABLE(of, host1x_of_match); static void host1x_setup_virtualization_tables(struct host1x *host){ const struct host1x_info *info = host->info; unsigned int i; if (!info->has_hypervisor) return; for (i = 0; i < info->num_sid_entries; i++) { const struct host1x_sid_entry *entry = &info->sid_table[i]; host1x_hypervisor_writel(host, entry->offset, entry->base); host1x_hypervisor_writel(host, entry->limit, entry->base + 4); } for (i = 0; i < info->streamid_vm_table.count; i++) { /* Allow access to all stream IDs to all VMs. */ host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i); } for (i = 0; i < info->classid_vm_table.count; i++) { /* Allow access to all classes to all VMs. */ host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i); } for (i = 0; i < info->mmio_vm_table.count; i++) { /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */ host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i); }} static bool host1x_wants_iommu(struct host1x *host1x){ /* Our IOMMU usage policy doesn't currently play well with GART */ if (of_machine_is_compatible("nvidia,tegra20")) return false; /* * If we support addressing a maximum of 32 bits of physical memory * and if the host1x firewall is enabled, there's no need to enable * IOMMU support. This can happen for example on Tegra20, Tegra30 * and Tegra114. * * Tegra124 and later can address up to 34 bits of physical memory and * many platforms come equipped with more than 2 GiB of system memory, * which requires crossing the 4 GiB boundary. But there's a catch: on * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can * only address up to 32 bits of memory in GATHER opcodes, which means * that command buffers need to either be in the first 2 GiB of system * memory (which could quickly lead to memory exhaustion), or command * buffers need to be treated differently from other buffers (which is * not possible with the current ABI). * * A third option is to use the IOMMU in these cases to make sure all * buffers will be mapped into a 32-bit IOVA space that host1x can * address. This allows all of the system memory to be used and works * within the limitations of the host1x on these SoCs. * * In summary, default to enable IOMMU on Tegra124 and later. For any * of the earlier SoCs, only use the IOMMU for additional safety when * the host1x firewall is disabled. */ if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) { if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) return false; } return true;} /* * Returns ERR_PTR on failure, NULL if the translation is IDENTITY, otherwise a * valid paging domain. */static struct iommu_domain *host1x_iommu_attach(struct host1x *host){ struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev); int err; #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) if (host->dev->archdata.mapping) { struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(host->dev); arm_iommu_detach_device(host->dev); arm_iommu_release_mapping(mapping); domain = iommu_get_domain_for_dev(host->dev); }#endif /* * We may not always want to enable IOMMU support (for example if the * host1x firewall is already enabled and we don't support addressing * more than 32 bits of physical memory), so check for that first. * * Similarly, if host1x is already attached to an IOMMU (via the DMA * API), don't try to attach again. */ if (domain && domain->type == IOMMU_DOMAIN_IDENTITY) domain = NULL; if (!host1x_wants_iommu(host) || domain) return domain; host->group = iommu_group_get(host->dev); if (host->group) { struct iommu_domain_geometry *geometry; dma_addr_t start, end; unsigned long order; err = iova_cache_get(); if (err < 0) goto put_group; host->domain = iommu_paging_domain_alloc(host->dev); if (IS_ERR(host->domain)) { err = PTR_ERR(host->domain); host->domain = NULL; goto put_cache; } err = iommu_attach_group(host->domain, host->group); if (err) { if (err == -ENODEV) err = 0; goto free_domain; } geometry = &host->domain->geometry; start = geometry->aperture_start & host->info->dma_mask; end = geometry->aperture_end & host->info->dma_mask; order = __ffs(host->domain->pgsize_bitmap); init_iova_domain(&host->iova, 1UL << order, start >> order); host->iova_end = end; domain = host->domain; } return domain; free_domain: iommu_domain_free(host->domain); host->domain = NULL;put_cache: iova_cache_put();put_group: iommu_group_put(host->group); host->group = NULL; return ERR_PTR(err);} static int host1x_iommu_init(struct host1x *host){ u64 mask = host->info->dma_mask; struct iommu_domain *domain; int err; domain = host1x_iommu_attach(host); if (IS_ERR(domain)) { err = PTR_ERR(domain); dev_err(host->dev, "failed to attach to IOMMU: %d\n", err); return err; } /* * If we're not behind an IOMMU make sure we don't get push buffers * that are allocated outside of the range addressable by the GATHER * opcode. * * Newer generations of Tegra (Tegra186 and later) support a wide * variant of the GATHER opcode that allows addressing more bits. */ if (!domain && !host->info->has_wide_gather) mask = DMA_BIT_MASK(32); err = dma_coerce_mask_and_coherent(host->dev, mask); if (err < 0) { dev_err(host->dev, "failed to set DMA mask: %d\n", err); return err; } return 0;} static void host1x_iommu_exit(struct host1x *host){ if (host->domain) { put_iova_domain(&host->iova); iommu_detach_group(host->domain, host->group); iommu_domain_free(host->domain); host->domain = NULL; iova_cache_put(); iommu_group_put(host->group);Lines 1–500 of 831. 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// SPDX-License-Identifier: GPL-2.0-only /* * Tegra host1x driver * * Copyright (c) 2010-2013, NVIDIA Corporation. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> #include <soc/tegra/common.h> #define CREATE_TRACE_POINTS #include <trace/events/host1x.h> #undef CREATE_TRACE_POINTS #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) #include <asm/dma-iommu.h> #endif #include "bus.h" #include "channel.h" #include "context.h" #include "debug.h" #include "dev.h" #include "intr.h" #include "hw/host1x01.h" #include "hw/host1x02.h" #include "hw/host1x04.h" #include "hw/host1x05.h" #include "hw/host1x06.h" #include "hw/host1x07.h" #include "hw/host1x08.h" void host1x_common_writel(struct host1x *host1x, u32 v, u32 r) { writel(v, host1x->common_regs + r); } void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) { writel(v, host1x->hv_regs + r); } u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) { return readl(host1x->hv_regs + r); } void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) { void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; writel(v, sync_regs + r); } u32 host1x_sync_readl(struct host1x *host1x, u32 r) { void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; return readl(sync_regs + r); } #ifdef CONFIG_64BIT u64 host1x_sync_readq(struct host1x *host1x, u32 r) { void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; return readq(sync_regs + r); } #endif void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) { writel(v, ch->regs + r); } u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) { return readl(ch->regs + r); } static const struct host1x_info host1x01_info = { .nb_channels = 8, .nb_pts = 32, .nb_mlocks = 16, .nb_bases = 8, .init = host1x01_init, .sync_offset = 0x3000, .dma_mask = DMA_BIT_MASK(32), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = true, }; static const struct host1x_info host1x02_info = { .nb_channels = 9, .nb_pts = 32, .nb_mlocks = 16, .nb_bases = 12, .init = host1x02_init, .sync_offset = 0x3000, .dma_mask = DMA_BIT_MASK(32), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = true, }; static const struct host1x_info host1x04_info = { .nb_channels = 12, .nb_pts = 192, .nb_mlocks = 16, .nb_bases = 64, .init = host1x04_init, .sync_offset = 0x2100, .dma_mask = DMA_BIT_MASK(34), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = false, }; static const struct host1x_info host1x05_info = { .nb_channels = 14, .nb_pts = 192, .nb_mlocks = 16, .nb_bases = 64, .init = host1x05_init, .sync_offset = 0x2100, .dma_mask = DMA_BIT_MASK(34), .has_wide_gather = false, .has_hypervisor = false, .num_sid_entries = 0, .sid_table = NULL, .reserve_vblank_syncpts = false, }; static const struct host1x_sid_entry tegra186_sid_table[] = { { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 }, { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 }, { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 }, { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 }, { /* ISP */ .base = 0x1ae8, .offset = 0x50, .limit = 0x50 }, { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 }, { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 }, { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 }, { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 }, { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 }, { /* VI 0 */ .base = 0x1b80, .offset = 0x10000, .limit = 0x10000 }, { /* VI 1 */ .base = 0x1b88, .offset = 0x20000, .limit = 0x20000 }, { /* VI 2 */ .base = 0x1b90, .offset = 0x30000, .limit = 0x30000 }, { /* VI 3 */ .base = 0x1b98, .offset = 0x40000, .limit = 0x40000 }, { /* VI 4 */ .base = 0x1ba0, .offset = 0x50000, .limit = 0x50000 }, { /* VI 5 */ .base = 0x1ba8, .offset = 0x60000, .limit = 0x60000 }, { /* VI 6 */ .base = 0x1bb0, .offset = 0x70000, .limit = 0x70000 }, { /* VI 7 */ .base = 0x1bb8, .offset = 0x80000, .limit = 0x80000 }, { /* VI 8 */ .base = 0x1bc0, .offset = 0x90000, .limit = 0x90000 }, { /* VI 9 */ .base = 0x1bc8, .offset = 0xa0000, .limit = 0xa0000 }, { /* VI 10 */ .base = 0x1bd0, .offset = 0xb0000, .limit = 0xb0000 }, { /* VI 11 */ .base = 0x1bd8, .offset = 0xc0000, .limit = 0xc0000 }, }; static const struct host1x_info host1x06_info = { .nb_channels = 63, .nb_pts = 576, .nb_mlocks = 24, .nb_bases = 16, .init = host1x06_init, .sync_offset = 0x0, .dma_mask = DMA_BIT_MASK(40), .has_wide_gather = true, .has_hypervisor = true, .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), .sid_table = tegra186_sid_table, .reserve_vblank_syncpts = false, .skip_reset_assert = true, }; static const struct host1x_sid_entry tegra194_sid_table[] = { { /* SE1 */ .base = 0x1ac8, .offset = 0x90, .limit = 0x90 }, { /* SE2 */ .base = 0x1ad0, .offset = 0x90, .limit = 0x90 }, { /* SE3 */ .base = 0x1ad8, .offset = 0x90, .limit = 0x90 }, { /* SE4 */ .base = 0x1ae0, .offset = 0x90, .limit = 0x90 }, { /* ISP */ .base = 0x1ae8, .offset = 0x800, .limit = 0x800 }, { /* VIC */ .base = 0x1af0, .offset = 0x30, .limit = 0x34 }, { /* NVENC */ .base = 0x1af8, .offset = 0x30, .limit = 0x34 }, { /* NVDEC */ .base = 0x1b00, .offset = 0x30, .limit = 0x34 }, { /* NVJPG */ .base = 0x1b08, .offset = 0x30, .limit = 0x34 }, { /* TSEC */ .base = 0x1b10, .offset = 0x30, .limit = 0x34 }, { /* TSECB */ .base = 0x1b18, .offset = 0x30, .limit = 0x34 }, { /* VI */ .base = 0x1b80, .offset = 0x800, .limit = 0x800 }, { /* VI_THI */ .base = 0x1b88, .offset = 0x30, .limit = 0x34 }, { /* ISP_THI */ .base = 0x1b90, .offset = 0x30, .limit = 0x34 }, { /* PVA0_CLUSTER */ .base = 0x1b98, .offset = 0x0, .limit = 0x0 }, { /* PVA0_CLUSTER */ .base = 0x1ba0, .offset = 0x0, .limit = 0x0 }, { /* NVDLA0 */ .base = 0x1ba8, .offset = 0x30, .limit = 0x34 }, { /* NVDLA1 */ .base = 0x1bb0, .offset = 0x30, .limit = 0x34 }, { /* NVENC1 */ .base = 0x1bb8, .offset = 0x30, .limit = 0x34 }, { /* NVDEC1 */ .base = 0x1bc0, .offset = 0x30, .limit = 0x34 }, }; static const struct host1x_info host1x07_info = { .nb_channels = 63, .nb_pts = 704, .nb_mlocks = 32, .nb_bases = 0, .init = host1x07_init, .sync_offset = 0x0, .dma_mask = DMA_BIT_MASK(40), .has_wide_gather = true, .has_hypervisor = true, .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), .sid_table = tegra194_sid_table, .reserve_vblank_syncpts = false, }; /* * Tegra234 has two stream ID protection tables, one for setting stream IDs * through the channel path via SETSTREAMID, and one for setting them via * MMIO. We program each engine's data stream ID in the channel path table * and firmware stream ID in the MMIO path table. */ static const struct host1x_sid_entry tegra234_sid_table[] = { { /* SE1 MMIO */ .base = 0x1650, .offset = 0x90, .limit = 0x90 }, { /* SE1 ch */ .base = 0x1730, .offset = 0x90, .limit = 0x90 }, { /* SE2 MMIO */ .base = 0x1658, .offset = 0x90, .limit = 0x90 }, { /* SE2 ch */ .base = 0x1738, .offset = 0x90, .limit = 0x90 }, { /* SE4 MMIO */ .base = 0x1660, .offset = 0x90, .limit = 0x90 }, { /* SE4 ch */ .base = 0x1740, .offset = 0x90, .limit = 0x90 }, { /* ISP MMIO */ .base = 0x1680, .offset = 0x800, .limit = 0x800 }, { /* VIC MMIO */ .base = 0x1688, .offset = 0x34, .limit = 0x34 }, { /* VIC ch */ .base = 0x17b8, .offset = 0x30, .limit = 0x30 }, { /* NVENC MMIO */ .base = 0x1690, .offset = 0x34, .limit = 0x34 }, { /* NVENC ch */ .base = 0x17c0, .offset = 0x30, .limit = 0x30 }, { /* NVDEC MMIO */ .base = 0x1698, .offset = 0x34, .limit = 0x34 }, { /* NVDEC ch */ .base = 0x17c8, .offset = 0x30, .limit = 0x30 }, { /* NVJPG MMIO */ .base = 0x16a0, .offset = 0x34, .limit = 0x34 }, { /* NVJPG ch */ .base = 0x17d0, .offset = 0x30, .limit = 0x30 }, { /* TSEC MMIO */ .base = 0x16a8, .offset = 0x30, .limit = 0x34 }, { /* NVJPG1 MMIO */ .base = 0x16b0, .offset = 0x34, .limit = 0x34 }, { /* NVJPG1 ch */ .base = 0x17a8, .offset = 0x30, .limit = 0x30 }, { /* VI MMIO */ .base = 0x16b8, .offset = 0x800, .limit = 0x800 }, { /* VI_THI MMIO */ .base = 0x16c0, .offset = 0x30, .limit = 0x34 }, { /* ISP_THI MMIO */ .base = 0x16c8, .offset = 0x30, .limit = 0x34 }, { /* NVDLA MMIO */ .base = 0x16d8, .offset = 0x30, .limit = 0x34 }, { /* NVDLA ch */ .base = 0x17e0, .offset = 0x30, .limit = 0x34 }, { /* NVDLA1 MMIO */ .base = 0x16e0, .offset = 0x30, .limit = 0x34 }, { /* NVDLA1 ch */ .base = 0x17e8, .offset = 0x30, .limit = 0x34 }, { /* OFA MMIO */ .base = 0x16e8, .offset = 0x34, .limit = 0x34 }, { /* OFA ch */ .base = 0x1768, .offset = 0x30, .limit = 0x30 }, { /* VI2 MMIO */ .base = 0x16f0, .offset = 0x800, .limit = 0x800 }, { /* VI2_THI MMIO */ .base = 0x16f8, .offset = 0x30, .limit = 0x34 }, }; static const struct host1x_info host1x08_info = { .nb_channels = 63, .nb_pts = 1024, .nb_mlocks = 24, .nb_bases = 0, .init = host1x08_init, .sync_offset = 0x0, .dma_mask = DMA_BIT_MASK(40), .has_wide_gather = true, .has_hypervisor = true, .has_common = true, .num_sid_entries = ARRAY_SIZE(tegra234_sid_table), .sid_table = tegra234_sid_table, .streamid_vm_table = { 0x1004, 128 }, .classid_vm_table = { 0x1404, 25 }, .mmio_vm_table = { 0x1504, 25 }, .reserve_vblank_syncpts = false, }; static const struct of_device_id host1x_of_match[] = { { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, }, { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, { }, }; MODULE_DEVICE_TABLE(of, host1x_of_match); static void host1x_setup_virtualization_tables(struct host1x *host) { const struct host1x_info *info = host->info; unsigned int i; if (!info->has_hypervisor) return; for (i = 0; i < info->num_sid_entries; i++) { const struct host1x_sid_entry *entry = &info->sid_table[i]; host1x_hypervisor_writel(host, entry->offset, entry->base); host1x_hypervisor_writel(host, entry->limit, entry->base + 4); } for (i = 0; i < info->streamid_vm_table.count; i++) { /* Allow access to all stream IDs to all VMs. */ host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i); } for (i = 0; i < info->classid_vm_table.count; i++) { /* Allow access to all classes to all VMs. */ host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i); } for (i = 0; i < info->mmio_vm_table.count; i++) { /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */ host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i); } } static bool host1x_wants_iommu(struct host1x *host1x) { /* Our IOMMU usage policy doesn't currently play well with GART */ if (of_machine_is_compatible("nvidia,tegra20")) return false; /* * If we support addressing a maximum of 32 bits of physical memory * and if the host1x firewall is enabled, there's no need to enable * IOMMU support. This can happen for example on Tegra20, Tegra30 * and Tegra114. * * Tegra124 and later can address up to 34 bits of physical memory and * many platforms come equipped with more than 2 GiB of system memory, * which requires crossing the 4 GiB boundary. But there's a catch: on * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can * only address up to 32 bits of memory in GATHER opcodes, which means * that command buffers need to either be in the first 2 GiB of system * memory (which could quickly lead to memory exhaustion), or command * buffers need to be treated differently from other buffers (which is * not possible with the current ABI). * * A third option is to use the IOMMU in these cases to make sure all * buffers will be mapped into a 32-bit IOVA space that host1x can * address. This allows all of the system memory to be used and works * within the limitations of the host1x on these SoCs. * * In summary, default to enable IOMMU on Tegra124 and later. For any * of the earlier SoCs, only use the IOMMU for additional safety when * the host1x firewall is disabled. */ if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) { if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) return false; } return true; } /* * Returns ERR_PTR on failure, NULL if the translation is IDENTITY, otherwise a * valid paging domain. */ static struct iommu_domain *host1x_iommu_attach(struct host1x *host) { struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev); int err; #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) if (host->dev->archdata.mapping) { struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(host->dev); arm_iommu_detach_device(host->dev); arm_iommu_release_mapping(mapping); domain = iommu_get_domain_for_dev(host->dev); } #endif /* * We may not always want to enable IOMMU support (for example if the * host1x firewall is already enabled and we don't support addressing * more than 32 bits of physical memory), so check for that first. * * Similarly, if host1x is already attached to an IOMMU (via the DMA * API), don't try to attach again. */ if (domain && domain->type == IOMMU_DOMAIN_IDENTITY) domain = NULL; if (!host1x_wants_iommu(host) || domain) return domain; host->group = iommu_group_get(host->dev); if (host->group) { struct iommu_domain_geometry *geometry; dma_addr_t start, end; unsigned long order; err = iova_cache_get(); if (err < 0) goto put_group; host->domain = iommu_paging_domain_alloc(host->dev); if (IS_ERR(host->domain)) { err = PTR_ERR(host->domain); host->domain = NULL; goto put_cache; } err = iommu_attach_group(host->domain, host->group); if (err) { if (err == -ENODEV) err = 0; goto free_domain; } geometry = &host->domain->geometry; start = geometry->aperture_start & host->info->dma_mask; end = geometry->aperture_end & host->info->dma_mask; order = __ffs(host->domain->pgsize_bitmap); init_iova_domain(&host->iova, 1UL << order, start >> order); host->iova_end = end; domain = host->domain; } return domain; free_domain: iommu_domain_free(host->domain); host->domain = NULL; put_cache: iova_cache_put(); put_group: iommu_group_put(host->group); host->group = NULL; return ERR_PTR(err); } static int host1x_iommu_init(struct host1x *host) { u64 mask = host->info->dma_mask; struct iommu_domain *domain; int err; domain = host1x_iommu_attach(host); if (IS_ERR(domain)) { err = PTR_ERR(domain); dev_err(host->dev, "failed to attach to IOMMU: %d\n", err); return err; } /* * If we're not behind an IOMMU make sure we don't get push buffers * that are allocated outside of the range addressable by the GATHER * opcode. * * Newer generations of Tegra (Tegra186 and later) support a wide * variant of the GATHER opcode that allows addressing more bits. */ if (!domain && !host->info->has_wide_gather) mask = DMA_BIT_MASK(32); err = dma_coerce_mask_and_coherent(host->dev, mask); if (err < 0) { dev_err(host->dev, "failed to set DMA mask: %d\n", err); return err; } return 0; } static void host1x_iommu_exit(struct host1x *host) { if (host->domain) { put_iova_domain(&host->iova); iommu_detach_group(host->domain, host->group); iommu_domain_free(host->domain); host->domain = NULL; iova_cache_put(); iommu_group_put(host->group);