/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/list.h>#include "amdgpu.h"#include "amdgpu_aca.h"#include "amdgpu_ras.h" #define ACA_BANK_HWID(type, hwid, mcatype) [ACA_HWIP_TYPE_##type] = {hwid, mcatype} typedef int bank_handler_t(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type, void *data); static struct aca_hwip aca_hwid_mcatypes[ACA_HWIP_TYPE_COUNT] = {	ACA_BANK_HWID(SMU,	0x01,	0x01),	ACA_BANK_HWID(PCS_XGMI, 0x50,	0x00),	ACA_BANK_HWID(UMC,	0x96,	0x00),}; static void aca_banks_init(struct aca_banks *banks){	if (!banks)		return; 	memset(banks, 0, sizeof(*banks));	INIT_LIST_HEAD(&banks->list);} static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank){	struct aca_bank_node *node; 	if (!bank)		return -EINVAL; 	node = kvzalloc_obj(*node);	if (!node)		return -ENOMEM; 	memcpy(&node->bank, bank, sizeof(*bank)); 	INIT_LIST_HEAD(&node->node);	list_add_tail(&node->node, &banks->list); 	banks->nr_banks++; 	return 0;} static void aca_banks_release(struct aca_banks *banks){	struct aca_bank_node *node, *tmp; 	if (list_empty(&banks->list))		return; 	list_for_each_entry_safe(node, tmp, &banks->list, node) {		list_del(&node->node);		kvfree(node);		banks->nr_banks--;	}} static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev, enum aca_smu_type type, u32 *count){	struct amdgpu_aca *aca = &adev->aca;	const struct aca_smu_funcs *smu_funcs = aca->smu_funcs; 	if (!count)		return -EINVAL; 	if (!smu_funcs || !smu_funcs->get_valid_aca_count)		return -EOPNOTSUPP; 	return smu_funcs->get_valid_aca_count(adev, type, count);} static struct aca_regs_dump {	const char *name;	int reg_idx;} aca_regs[] = {	{"CONTROL",		ACA_REG_IDX_CTL},	{"STATUS",		ACA_REG_IDX_STATUS},	{"ADDR",		ACA_REG_IDX_ADDR},	{"MISC",		ACA_REG_IDX_MISC0},	{"CONFIG",		ACA_REG_IDX_CONFIG},	{"IPID",		ACA_REG_IDX_IPID},	{"SYND",		ACA_REG_IDX_SYND},	{"DESTAT",		ACA_REG_IDX_DESTAT},	{"DEADDR",		ACA_REG_IDX_DEADDR},	{"CONTROL_MASK",	ACA_REG_IDX_CTL_MASK},}; static void aca_smu_bank_dump(struct amdgpu_device *adev, int idx, int total, struct aca_bank *bank,			      struct ras_query_context *qctx){	u64 event_id = qctx ? qctx->evid.event_id : RAS_EVENT_INVALID_ID;	int i; 	if (adev->debug_disable_ce_logs &&	    bank->smu_err_type == ACA_SMU_TYPE_CE &&	    !ACA_BANK_ERR_IS_DEFFERED(bank))		return; 	RAS_EVENT_LOG(adev, event_id, HW_ERR "Accelerator Check Architecture events logged\n");	/* plus 1 for output format, e.g: ACA[08/08]: xxxx */	for (i = 0; i < ARRAY_SIZE(aca_regs); i++)		RAS_EVENT_LOG(adev, event_id, HW_ERR "ACA[%02d/%02d].%s=0x%016llx\n",			      idx + 1, total, aca_regs[i].name, bank->regs[aca_regs[i].reg_idx]); 	if (ACA_REG__STATUS__SCRUB(bank->regs[ACA_REG_IDX_STATUS]))		RAS_EVENT_LOG(adev, event_id, HW_ERR "hardware error logged by the scrubber\n");} static bool aca_bank_hwip_is_matched(struct aca_bank *bank, enum aca_hwip_type type){ 	struct aca_hwip *hwip;	int hwid, mcatype;	u64 ipid; 	if (!bank || type == ACA_HWIP_TYPE_UNKNOW)		return false; 	hwip = &aca_hwid_mcatypes[type];	if (!hwip->hwid)		return false; 	ipid = bank->regs[ACA_REG_IDX_IPID];	hwid = ACA_REG__IPID__HARDWAREID(ipid);	mcatype = ACA_REG__IPID__MCATYPE(ipid); 	return hwip->hwid == hwid && hwip->mcatype == mcatype;} static int aca_smu_get_valid_aca_banks(struct amdgpu_device *adev, enum aca_smu_type type,				       int start, int count,				       struct aca_banks *banks, struct ras_query_context *qctx){	struct amdgpu_aca *aca = &adev->aca;	const struct aca_smu_funcs *smu_funcs = aca->smu_funcs;	struct aca_bank bank;	int i, max_count, ret; 	if (!count)		return 0; 	if (!smu_funcs || !smu_funcs->get_valid_aca_bank)		return -EOPNOTSUPP; 	switch (type) {	case ACA_SMU_TYPE_UE:		max_count = smu_funcs->max_ue_bank_count;		break;	case ACA_SMU_TYPE_CE:		max_count = smu_funcs->max_ce_bank_count;		break;	default:		return -EINVAL;	} 	if (start + count > max_count)		return -EINVAL; 	count = min_t(int, count, max_count);	for (i = 0; i < count; i++) {		memset(&bank, 0, sizeof(bank));		ret = smu_funcs->get_valid_aca_bank(adev, type, start + i, &bank);		if (ret)			return ret; 		bank.smu_err_type = type; 		/*		 * Poison being consumed when injecting a UE while running background workloads,		 * which are unexpected.		 */		if (type == ACA_SMU_TYPE_UE &&		    ACA_REG__STATUS__POISON(bank.regs[ACA_REG_IDX_STATUS]) &&		    !aca_bank_hwip_is_matched(&bank, ACA_HWIP_TYPE_UMC))			continue; 		aca_smu_bank_dump(adev, i, count, &bank, qctx); 		ret = aca_banks_add_bank(banks, &bank);		if (ret)			return ret;	} 	return 0;} static bool aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type){	const struct aca_bank_ops *bank_ops = handle->bank_ops; 	/* Parse all deferred errors with UMC aca handle */	if (ACA_BANK_ERR_IS_DEFFERED(bank))		return handle->hwip == ACA_HWIP_TYPE_UMC; 	if (!aca_bank_hwip_is_matched(bank, handle->hwip))		return false; 	if (!bank_ops->aca_bank_is_valid)		return true; 	return bank_ops->aca_bank_is_valid(handle, bank, type, handle->data);} static struct aca_bank_error *new_bank_error(struct aca_error *aerr, struct aca_bank_info *info){	struct aca_bank_error *bank_error; 	bank_error = kvzalloc_obj(*bank_error);	if (!bank_error)		return NULL; 	INIT_LIST_HEAD(&bank_error->node);	memcpy(&bank_error->info, info, sizeof(*info)); 	mutex_lock(&aerr->lock);	list_add_tail(&bank_error->node, &aerr->list);	aerr->nr_errors++;	mutex_unlock(&aerr->lock); 	return bank_error;} static struct aca_bank_error *find_bank_error(struct aca_error *aerr, struct aca_bank_info *info){	struct aca_bank_error *bank_error = NULL;	struct aca_bank_info *tmp_info;	bool found = false; 	mutex_lock(&aerr->lock);	list_for_each_entry(bank_error, &aerr->list, node) {		tmp_info = &bank_error->info;		if (tmp_info->socket_id == info->socket_id &&		    tmp_info->die_id == info->die_id) {			found = true;			goto out_unlock;		}	} out_unlock:	mutex_unlock(&aerr->lock); 	return found ? bank_error : NULL;} static void aca_bank_error_remove(struct aca_error *aerr, struct aca_bank_error *bank_error){	if (!aerr || !bank_error)		return; 	list_del(&bank_error->node);	aerr->nr_errors--; 	kvfree(bank_error);} static struct aca_bank_error *get_bank_error(struct aca_error *aerr, struct aca_bank_info *info){	struct aca_bank_error *bank_error; 	if (!aerr || !info)		return NULL; 	bank_error = find_bank_error(aerr, info);	if (bank_error)		return bank_error; 	return new_bank_error(aerr, info);} int aca_error_cache_log_bank_error(struct aca_handle *handle, struct aca_bank_info *info,				   enum aca_error_type type, u64 count){	struct aca_error_cache *error_cache = &handle->error_cache;	struct aca_bank_error *bank_error;	struct aca_error *aerr; 	if (!handle || !info || type >= ACA_ERROR_TYPE_COUNT)		return -EINVAL; 	if (!count)		return 0; 	aerr = &error_cache->errors[type];	bank_error = get_bank_error(aerr, info);	if (!bank_error)		return -ENOMEM; 	bank_error->count += count; 	return 0;} static int aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, enum aca_smu_type type){	const struct aca_bank_ops *bank_ops = handle->bank_ops; 	if (!bank)		return -EINVAL; 	if (!bank_ops->aca_bank_parser)		return -EOPNOTSUPP; 	return bank_ops->aca_bank_parser(handle, bank, type,					 handle->data);} static int handler_aca_log_bank_error(struct aca_handle *handle, struct aca_bank *bank,				      enum aca_smu_type type, void *data){	int ret; 	ret = aca_bank_parser(handle, bank, type);	if (ret)		return ret; 	return 0;} static int aca_dispatch_bank(struct aca_handle_manager *mgr, struct aca_bank *bank,			     enum aca_smu_type type, bank_handler_t handler, void *data){	struct aca_handle *handle;	int ret; 	if (list_empty(&mgr->list))		return 0; 	list_for_each_entry(handle, &mgr->list, node) {		if (!aca_bank_is_valid(handle, bank, type))			continue; 		ret = handler(handle, bank, type, data);		if (ret)			return ret;	} 	return 0;} static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks,			      enum aca_smu_type type, bank_handler_t handler, void *data){	struct aca_bank_node *node;	struct aca_bank *bank;	int ret; 	if (!mgr || !banks)		return -EINVAL; 	/* pre check to avoid unnecessary operations */	if (list_empty(&mgr->list) || list_empty(&banks->list))		return 0; 	list_for_each_entry(node, &banks->list, node) {		bank = &node->bank; 		ret = aca_dispatch_bank(mgr, bank, type, handler, data);		if (ret)			return ret;	} 	return 0;} static bool aca_bank_should_update(struct amdgpu_device *adev, enum aca_smu_type type){	struct amdgpu_aca *aca = &adev->aca;	bool ret = true; 	/*	 * Because the UE Valid MCA count will only be cleared after reset,	 * in order to avoid repeated counting of the error count,	 * the aca bank is only updated once during the gpu recovery stage.	 */	if (type == ACA_SMU_TYPE_UE) {		if (amdgpu_ras_intr_triggered())			ret = atomic_cmpxchg(&aca->ue_update_flag, 0, 1) == 0;		else			atomic_set(&aca->ue_update_flag, 0);	} 	return ret;} static void aca_banks_generate_cper(struct amdgpu_device *adev,				    enum aca_smu_type type,				    struct aca_banks *banks,				    int count){	struct aca_bank_node *node;	struct aca_bank *bank;	int r; 	if (!adev->cper.enabled)		return; 	if (!banks || !count) {		dev_warn(adev->dev, "fail to generate cper records\n");		return;	} 	/* UEs must be encoded into separate CPER entries */	if (type == ACA_SMU_TYPE_UE) {		struct aca_banks de_banks; 		aca_banks_init(&de_banks);		list_for_each_entry(node, &banks->list, node) {			bank = &node->bank;			if (bank->aca_err_type == ACA_ERROR_TYPE_DEFERRED) {				r = aca_banks_add_bank(&de_banks, bank);				if (r)					dev_warn(adev->dev, "fail to add de banks, ret = %d\n", r);			} else {				if (amdgpu_cper_generate_ue_record(adev, bank))					dev_warn(adev->dev, "fail to generate ue cper records\n");			}		} 		if (!list_empty(&de_banks.list)) {			if (amdgpu_cper_generate_ce_records(adev, &de_banks, de_banks.nr_banks))				dev_warn(adev->dev, "fail to generate de cper records\n");		} 		aca_banks_release(&de_banks);	} else {		/*		 * SMU_TYPE_CE banks are combined into 1 CPER entries,		 * they could be CEs or DEs or both		 */		if (amdgpu_cper_generate_ce_records(adev, banks, count))			dev_warn(adev->dev, "fail to generate ce cper records\n");	}} static int aca_banks_update(struct amdgpu_device *adev, enum aca_smu_type type,			    bank_handler_t handler, struct ras_query_context *qctx, void *data){	struct amdgpu_aca *aca = &adev->aca;	struct aca_banks banks;	u32 count = 0;	int ret; 	if (list_empty(&aca->mgr.list))		return 0; 	if (!aca_bank_should_update(adev, type))		return 0; 	ret = aca_smu_get_valid_aca_count(adev, type, &count);	if (ret)		return ret; 	if (!count)		return 0; 	aca_banks_init(&banks); 	ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &banks, qctx);	if (ret)		goto err_release_banks; 	if (list_empty(&banks.list)) {		ret = 0;		goto err_release_banks;	} 	ret = aca_dispatch_banks(&aca->mgr, &banks, type,				 handler, data);	if (ret)		goto err_release_banks; 	aca_banks_generate_cper(adev, type, &banks, count); err_release_banks:	aca_banks_release(&banks);

Lines 1–500 of 985. Load more