/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <drm/amdgpu_drm.h>#include "amdgpu.h"#include "atomfirmware.h"#include "amdgpu_atomfirmware.h"#include "atom.h"#include "atombios.h"#include "soc15_hw_ip.h" union firmware_info { struct atom_firmware_info_v3_1 v31; struct atom_firmware_info_v3_2 v32; struct atom_firmware_info_v3_3 v33; struct atom_firmware_info_v3_4 v34; struct atom_firmware_info_v3_5 v35;}; /* * Helper function to query firmware capability * * @adev: amdgpu_device pointer * * Return firmware_capability in firmwareinfo table on success or 0 if not */uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev){ struct amdgpu_mode_info *mode_info = &adev->mode_info; int index; u16 data_offset, size; union firmware_info *firmware_info; u8 frev, crev; u32 fw_cap = 0; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, firmwareinfo); if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, &frev, &crev, &data_offset)) { /* support firmware_info 3.1 + */ if ((frev == 3 && crev >= 1) || (frev > 3)) { firmware_info = (union firmware_info *) (mode_info->atom_context->bios + data_offset); fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); } } return fw_cap;} /* * Helper function to query gpu virtualizaiton capability * * @adev: amdgpu_device pointer * * Return true if gpu virtualization is supported or false if not */bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev){ u32 fw_cap; fw_cap = adev->mode_info.firmware_flags; return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false;} void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev){ int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, firmwareinfo); uint16_t data_offset; if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, NULL, NULL, &data_offset)) { struct atom_firmware_info_v3_1 *firmware_info = (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + data_offset); adev->bios_scratch_reg_offset = le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); }} static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev, struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes){ u32 start_addr, fw_size, drv_size; start_addr = le32_to_cpu(fw_usage->start_address_in_kb); fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb); DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n", start_addr, fw_size, drv_size); if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { /* Firmware request VRAM reservation for SR-IOV */ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, (start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, fw_size << 10, true); /* Use the default scratch size */ *usage_bytes = 0; } else { *usage_bytes = drv_size << 10; } return 0;} static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev, struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes){ u32 fw_start_addr, fw_size, drv_start_addr, drv_size; fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb); fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb); drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb); DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n", fw_start_addr, fw_size, drv_start_addr, drv_size); if (amdgpu_sriov_vf(adev) && ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { /* Firmware request VRAM reservation for SR-IOV */ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, (fw_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, fw_size << 10, true); } if (amdgpu_sriov_vf(adev) && ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { /* driver request VRAM reservation for SR-IOV */ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_DRV_VRAM_USAGE, (drv_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, drv_size << 10, true); } *usage_bytes = 0; return 0;} int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev){ struct atom_context *ctx = adev->mode_info.atom_context; int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_usagebyfirmware); struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1; struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2; u16 data_offset; u8 frev, crev; int usage_bytes = 0; /* Skip atomfirmware allocation for SRIOV VFs when dynamic crit regn is enabled */ if (!(amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled)) { if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) { if (frev == 2 && crev == 1) { fw_usage_v2_1 = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); amdgpu_atomfirmware_allocate_fb_v2_1(adev, fw_usage_v2_1, &usage_bytes); } else if (frev >= 2 && crev >= 2) { fw_usage_v2_2 = (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset); amdgpu_atomfirmware_allocate_fb_v2_2(adev, fw_usage_v2_2, &usage_bytes); } } } ctx->scratch_size_bytes = 0; if (usage_bytes == 0) usage_bytes = 20 * 1024; /* allocate some scratch memory */ ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); if (!ctx->scratch) return -ENOMEM; ctx->scratch_size_bytes = usage_bytes; return 0;} union igp_info { struct atom_integrated_system_info_v1_11 v11; struct atom_integrated_system_info_v1_12 v12; struct atom_integrated_system_info_v2_1 v21; struct atom_integrated_system_info_v2_3 v23;}; union umc_info { struct atom_umc_info_v3_1 v31; struct atom_umc_info_v3_2 v32; struct atom_umc_info_v3_3 v33; struct atom_umc_info_v4_0 v40;}; union vram_info { struct atom_vram_info_header_v2_3 v23; struct atom_vram_info_header_v2_4 v24; struct atom_vram_info_header_v2_5 v25; struct atom_vram_info_header_v2_6 v26; struct atom_vram_info_header_v3_0 v30;}; union vram_module { struct atom_vram_module_v9 v9; struct atom_vram_module_v10 v10; struct atom_vram_module_v11 v11; struct atom_vram_module_v3_0 v30;}; static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, int atom_mem_type){ int vram_type; if (adev->flags & AMD_IS_APU) { switch (atom_mem_type) { case Ddr2MemType: case LpDdr2MemType: vram_type = AMDGPU_VRAM_TYPE_DDR2; break; case Ddr3MemType: case LpDdr3MemType: vram_type = AMDGPU_VRAM_TYPE_DDR3; break; case Ddr4MemType: vram_type = AMDGPU_VRAM_TYPE_DDR4; break; case LpDdr4MemType: vram_type = AMDGPU_VRAM_TYPE_LPDDR4; break; case Ddr5MemType: vram_type = AMDGPU_VRAM_TYPE_DDR5; break; case LpDdr5MemType: vram_type = AMDGPU_VRAM_TYPE_LPDDR5; break; default: vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; break; } } else { switch (atom_mem_type) { case ATOM_DGPU_VRAM_TYPE_GDDR5: vram_type = AMDGPU_VRAM_TYPE_GDDR5; break; case ATOM_DGPU_VRAM_TYPE_HBM2: case ATOM_DGPU_VRAM_TYPE_HBM2E: case ATOM_DGPU_VRAM_TYPE_HBM3: vram_type = AMDGPU_VRAM_TYPE_HBM; break; case ATOM_DGPU_VRAM_TYPE_GDDR6: vram_type = AMDGPU_VRAM_TYPE_GDDR6; break; case ATOM_DGPU_VRAM_TYPE_HBM3E: vram_type = AMDGPU_VRAM_TYPE_HBM3E; break; default: vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; break; } } return vram_type;} static int amdgpu_atomfirmware_get_uma_carveout_info_v2_3(struct amdgpu_device *adev, union igp_info *igp_info, struct amdgpu_uma_carveout_info *uma_info){ struct uma_carveout_option *opts; uint8_t nr_uma_options; int i; nr_uma_options = igp_info->v23.UMACarveoutIndexMax; if (!nr_uma_options) return -ENODEV; if (nr_uma_options > MAX_UMA_OPTION_ENTRIES) { drm_dbg(adev_to_drm(adev), "Number of UMA options exceeds max table size. Options will not be parsed"); return -EINVAL; } uma_info->num_entries = nr_uma_options; uma_info->uma_option_index = igp_info->v23.UMACarveoutIndex; opts = igp_info->v23.UMASizeControlOption; for (i = 0; i < nr_uma_options; i++) { if (!opts[i].memoryCarvedGb) uma_info->entries[i].memory_carved_mb = 512; else uma_info->entries[i].memory_carved_mb = (uint32_t)opts[i].memoryCarvedGb << 10; uma_info->entries[i].flags = opts[i].uma_carveout_option_flags.all8; strscpy(uma_info->entries[i].name, opts[i].optionName, MAX_UMA_OPTION_NAME); } return 0;} int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, struct amdgpu_uma_carveout_info *uma_info){ struct amdgpu_mode_info *mode_info = &adev->mode_info; union igp_info *igp_info; u16 data_offset, size; u8 frev, crev; int index; if (!(adev->flags & AMD_IS_APU)) return -ENODEV; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, integratedsysteminfo); if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { return -EINVAL; } igp_info = (union igp_info *) (mode_info->atom_context->bios + data_offset); switch (frev) { case 2: switch (crev) { case 3: return amdgpu_atomfirmware_get_uma_carveout_info_v2_3(adev, igp_info, uma_info); break; default: break; } break; default: break; } return -ENODEV;} int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor){ struct amdgpu_mode_info *mode_info = &adev->mode_info; int index; u16 data_offset, size; union igp_info *igp_info; u8 frev, crev; u8 mem_type; u32 mem_channel_number; u32 mem_channel_width; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, integratedsysteminfo); if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { igp_info = (union igp_info *) (mode_info->atom_context->bios + data_offset); switch (frev) { case 1: switch (crev) { case 11: case 12: mem_channel_number = igp_info->v11.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; mem_type = igp_info->v11.memorytype; if (mem_type == LpDdr5MemType) mem_channel_width = 32; else mem_channel_width = 64; if (vram_width) *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; default: return -EINVAL; } break; case 2: switch (crev) { case 1: case 2: mem_channel_number = igp_info->v21.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; mem_type = igp_info->v21.memorytype; if (mem_type == LpDdr5MemType) mem_channel_width = 32; else mem_channel_width = 64; if (vram_width) *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; case 3: mem_channel_number = igp_info->v23.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; mem_type = igp_info->v23.memorytype; if (mem_type == LpDdr5MemType) mem_channel_width = 32; else mem_channel_width = 64; if (vram_width) *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; default: return -EINVAL; } break; default: return -EINVAL; } } else { return -EINVAL; } return 0;} int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor){ struct amdgpu_mode_info *mode_info = &adev->mode_info; int index; u16 data_offset, size; union umc_info *umc_info; u8 frev, crev; u8 mem_type; u8 mem_vendor; u32 mem_channel_number; u32 mem_channel_width; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); if (frev == 4) { switch (crev) { case 0: mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); mem_type = le32_to_cpu(umc_info->v40.vram_type); mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; if (vram_vendor) *vram_vendor = mem_vendor; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); if (vram_width) *vram_width = mem_channel_number * (1 << mem_channel_width); break; default: return -EINVAL; } } else {Lines 1–500 of 1119. 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/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <drm/amdgpu_drm.h> #include "amdgpu.h" #include "atomfirmware.h" #include "amdgpu_atomfirmware.h" #include "atom.h" #include "atombios.h" #include "soc15_hw_ip.h" union firmware_info { struct atom_firmware_info_v3_1 v31; struct atom_firmware_info_v3_2 v32; struct atom_firmware_info_v3_3 v33; struct atom_firmware_info_v3_4 v34; struct atom_firmware_info_v3_5 v35; }; /* * Helper function to query firmware capability * * @adev: amdgpu_device pointer * * Return firmware_capability in firmwareinfo table on success or 0 if not */ uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *adev) { struct amdgpu_mode_info *mode_info = &adev->mode_info; int index; u16 data_offset, size; union firmware_info *firmware_info; u8 frev, crev; u32 fw_cap = 0; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, firmwareinfo); if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, &frev, &crev, &data_offset)) { /* support firmware_info 3.1 + */ if ((frev == 3 && crev >= 1) || (frev > 3)) { firmware_info = (union firmware_info *) (mode_info->atom_context->bios + data_offset); fw_cap = le32_to_cpu(firmware_info->v31.firmware_capability); } } return fw_cap; } /* * Helper function to query gpu virtualizaiton capability * * @adev: amdgpu_device pointer * * Return true if gpu virtualization is supported or false if not */ bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev) { u32 fw_cap; fw_cap = adev->mode_info.firmware_flags; return (fw_cap & ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION) ? true : false; } void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev) { int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, firmwareinfo); uint16_t data_offset; if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL, NULL, NULL, &data_offset)) { struct atom_firmware_info_v3_1 *firmware_info = (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios + data_offset); adev->bios_scratch_reg_offset = le32_to_cpu(firmware_info->bios_scratch_reg_startaddr); } } static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev, struct vram_usagebyfirmware_v2_1 *fw_usage, int *usage_bytes) { u32 start_addr, fw_size, drv_size; start_addr = le32_to_cpu(fw_usage->start_address_in_kb); fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); drv_size = le16_to_cpu(fw_usage->used_by_driver_in_kb); DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n", start_addr, fw_size, drv_size); if ((start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == (u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { /* Firmware request VRAM reservation for SR-IOV */ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, (start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, fw_size << 10, true); /* Use the default scratch size */ *usage_bytes = 0; } else { *usage_bytes = drv_size << 10; } return 0; } static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev, struct vram_usagebyfirmware_v2_2 *fw_usage, int *usage_bytes) { u32 fw_start_addr, fw_size, drv_start_addr, drv_size; fw_start_addr = le32_to_cpu(fw_usage->fw_region_start_address_in_kb); fw_size = le16_to_cpu(fw_usage->used_by_firmware_in_kb); drv_start_addr = le32_to_cpu(fw_usage->driver_region0_start_address_in_kb); drv_size = le32_to_cpu(fw_usage->used_by_driver_region0_in_kb); DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x %dkb\n", fw_start_addr, fw_size, drv_start_addr, drv_size); if (amdgpu_sriov_vf(adev) && ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { /* Firmware request VRAM reservation for SR-IOV */ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE, (fw_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, fw_size << 10, true); } if (amdgpu_sriov_vf(adev) && ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { /* driver request VRAM reservation for SR-IOV */ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_DRV_VRAM_USAGE, (drv_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, drv_size << 10, true); } *usage_bytes = 0; return 0; } int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) { struct atom_context *ctx = adev->mode_info.atom_context; int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_usagebyfirmware); struct vram_usagebyfirmware_v2_1 *fw_usage_v2_1; struct vram_usagebyfirmware_v2_2 *fw_usage_v2_2; u16 data_offset; u8 frev, crev; int usage_bytes = 0; /* Skip atomfirmware allocation for SRIOV VFs when dynamic crit regn is enabled */ if (!(amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled)) { if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) { if (frev == 2 && crev == 1) { fw_usage_v2_1 = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset); amdgpu_atomfirmware_allocate_fb_v2_1(adev, fw_usage_v2_1, &usage_bytes); } else if (frev >= 2 && crev >= 2) { fw_usage_v2_2 = (struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset); amdgpu_atomfirmware_allocate_fb_v2_2(adev, fw_usage_v2_2, &usage_bytes); } } } ctx->scratch_size_bytes = 0; if (usage_bytes == 0) usage_bytes = 20 * 1024; /* allocate some scratch memory */ ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); if (!ctx->scratch) return -ENOMEM; ctx->scratch_size_bytes = usage_bytes; return 0; } union igp_info { struct atom_integrated_system_info_v1_11 v11; struct atom_integrated_system_info_v1_12 v12; struct atom_integrated_system_info_v2_1 v21; struct atom_integrated_system_info_v2_3 v23; }; union umc_info { struct atom_umc_info_v3_1 v31; struct atom_umc_info_v3_2 v32; struct atom_umc_info_v3_3 v33; struct atom_umc_info_v4_0 v40; }; union vram_info { struct atom_vram_info_header_v2_3 v23; struct atom_vram_info_header_v2_4 v24; struct atom_vram_info_header_v2_5 v25; struct atom_vram_info_header_v2_6 v26; struct atom_vram_info_header_v3_0 v30; }; union vram_module { struct atom_vram_module_v9 v9; struct atom_vram_module_v10 v10; struct atom_vram_module_v11 v11; struct atom_vram_module_v3_0 v30; }; static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, int atom_mem_type) { int vram_type; if (adev->flags & AMD_IS_APU) { switch (atom_mem_type) { case Ddr2MemType: case LpDdr2MemType: vram_type = AMDGPU_VRAM_TYPE_DDR2; break; case Ddr3MemType: case LpDdr3MemType: vram_type = AMDGPU_VRAM_TYPE_DDR3; break; case Ddr4MemType: vram_type = AMDGPU_VRAM_TYPE_DDR4; break; case LpDdr4MemType: vram_type = AMDGPU_VRAM_TYPE_LPDDR4; break; case Ddr5MemType: vram_type = AMDGPU_VRAM_TYPE_DDR5; break; case LpDdr5MemType: vram_type = AMDGPU_VRAM_TYPE_LPDDR5; break; default: vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; break; } } else { switch (atom_mem_type) { case ATOM_DGPU_VRAM_TYPE_GDDR5: vram_type = AMDGPU_VRAM_TYPE_GDDR5; break; case ATOM_DGPU_VRAM_TYPE_HBM2: case ATOM_DGPU_VRAM_TYPE_HBM2E: case ATOM_DGPU_VRAM_TYPE_HBM3: vram_type = AMDGPU_VRAM_TYPE_HBM; break; case ATOM_DGPU_VRAM_TYPE_GDDR6: vram_type = AMDGPU_VRAM_TYPE_GDDR6; break; case ATOM_DGPU_VRAM_TYPE_HBM3E: vram_type = AMDGPU_VRAM_TYPE_HBM3E; break; default: vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; break; } } return vram_type; } static int amdgpu_atomfirmware_get_uma_carveout_info_v2_3(struct amdgpu_device *adev, union igp_info *igp_info, struct amdgpu_uma_carveout_info *uma_info) { struct uma_carveout_option *opts; uint8_t nr_uma_options; int i; nr_uma_options = igp_info->v23.UMACarveoutIndexMax; if (!nr_uma_options) return -ENODEV; if (nr_uma_options > MAX_UMA_OPTION_ENTRIES) { drm_dbg(adev_to_drm(adev), "Number of UMA options exceeds max table size. Options will not be parsed"); return -EINVAL; } uma_info->num_entries = nr_uma_options; uma_info->uma_option_index = igp_info->v23.UMACarveoutIndex; opts = igp_info->v23.UMASizeControlOption; for (i = 0; i < nr_uma_options; i++) { if (!opts[i].memoryCarvedGb) uma_info->entries[i].memory_carved_mb = 512; else uma_info->entries[i].memory_carved_mb = (uint32_t)opts[i].memoryCarvedGb << 10; uma_info->entries[i].flags = opts[i].uma_carveout_option_flags.all8; strscpy(uma_info->entries[i].name, opts[i].optionName, MAX_UMA_OPTION_NAME); } return 0; } int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, struct amdgpu_uma_carveout_info *uma_info) { struct amdgpu_mode_info *mode_info = &adev->mode_info; union igp_info *igp_info; u16 data_offset, size; u8 frev, crev; int index; if (!(adev->flags & AMD_IS_APU)) return -ENODEV; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, integratedsysteminfo); if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { return -EINVAL; } igp_info = (union igp_info *) (mode_info->atom_context->bios + data_offset); switch (frev) { case 2: switch (crev) { case 3: return amdgpu_atomfirmware_get_uma_carveout_info_v2_3(adev, igp_info, uma_info); break; default: break; } break; default: break; } return -ENODEV; } int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor) { struct amdgpu_mode_info *mode_info = &adev->mode_info; int index; u16 data_offset, size; union igp_info *igp_info; u8 frev, crev; u8 mem_type; u32 mem_channel_number; u32 mem_channel_width; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, integratedsysteminfo); if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { igp_info = (union igp_info *) (mode_info->atom_context->bios + data_offset); switch (frev) { case 1: switch (crev) { case 11: case 12: mem_channel_number = igp_info->v11.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; mem_type = igp_info->v11.memorytype; if (mem_type == LpDdr5MemType) mem_channel_width = 32; else mem_channel_width = 64; if (vram_width) *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; default: return -EINVAL; } break; case 2: switch (crev) { case 1: case 2: mem_channel_number = igp_info->v21.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; mem_type = igp_info->v21.memorytype; if (mem_type == LpDdr5MemType) mem_channel_width = 32; else mem_channel_width = 64; if (vram_width) *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; case 3: mem_channel_number = igp_info->v23.umachannelnumber; if (!mem_channel_number) mem_channel_number = 1; mem_type = igp_info->v23.memorytype; if (mem_type == LpDdr5MemType) mem_channel_width = 32; else mem_channel_width = 64; if (vram_width) *vram_width = mem_channel_number * mem_channel_width; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); break; default: return -EINVAL; } break; default: return -EINVAL; } } else { return -EINVAL; } return 0; } int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor) { struct amdgpu_mode_info *mode_info = &adev->mode_info; int index; u16 data_offset, size; union umc_info *umc_info; u8 frev, crev; u8 mem_type; u8 mem_vendor; u32 mem_channel_number; u32 mem_channel_width; index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); if (frev == 4) { switch (crev) { case 0: mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); mem_type = le32_to_cpu(umc_info->v40.vram_type); mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; if (vram_vendor) *vram_vendor = mem_vendor; if (vram_type) *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); if (vram_width) *vram_width = mem_channel_number * (1 << mem_channel_width); break; default: return -EINVAL; } } else {