| @@ -72,6 +72,7 @@ · 71 unmodified lines |
| 72 | #include <linux/pci.h> | 72 | #include <linux/pci.h> |
| 73 | #include <linux/firmware.h> | 73 | #include <linux/firmware.h> |
| 74 | #include <linux/component.h> | 74 | #include <linux/component.h> |
| | 75 | #include <linux/dmi.h> |
| 75 | | 76 | |
| 76 | #include <drm/display/drm_dp_mst_helper.h> | 77 | #include <drm/display/drm_dp_mst_helper.h> |
| 77 | #include <drm/display/drm_hdmi_helper.h> | 78 | #include <drm/display/drm_hdmi_helper.h> |
| @@ -462,6 +463,26 @@ static void dm_pflip_high_irq(void *interrupt_params) · 384 unmodified lines |
| 462 | vrr_active, (int) !e); | 463 | vrr_active, (int) !e); |
| 463 | } | 464 | } |
| 464 | | 465 | |
| | 466 | static void dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc) |
| | 467 | { |
| | 468 | struct drm_crtc *crtc = &acrtc->base; |
| | 469 | struct drm_device *dev = crtc->dev; |
| | 470 | unsigned long flags; |
| | 471 | |
| | 472 | drm_crtc_handle_vblank(crtc); |
| | 473 | |
| | 474 | spin_lock_irqsave(&dev->event_lock, flags); |
| | 475 | |
| | 476 | /* Send completion event for cursor-only commits */ |
| | 477 | if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { |
| | 478 | drm_crtc_send_vblank_event(crtc, acrtc->event); |
| | 479 | drm_crtc_vblank_put(crtc); |
| | 480 | acrtc->event = NULL; |
| | 481 | } |
| | 482 | |
| | 483 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| | 484 | } |
| | 485 | |
| 465 | static void dm_vupdate_high_irq(void *interrupt_params) | 486 | static void dm_vupdate_high_irq(void *interrupt_params) |
| 466 | { | 487 | { |
| 467 | struct common_irq_params *irq_params = interrupt_params; | 488 | struct common_irq_params *irq_params = interrupt_params; |
| @@ -500,7 +521,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) · 32 unmodified lines |
| 500 | * if a pageflip happened inside front-porch. | 521 | * if a pageflip happened inside front-porch. |
| 501 | */ | 522 | */ |
| 502 | if (vrr_active) { | 523 | if (vrr_active) { |
| 503 | drm_crtc_handle_vblank(&acrtc->base); | 524 | dm_crtc_handle_vblank(acrtc); |
| 504 | | 525 | |
| 505 | /* BTR processing for pre-DCE12 ASICs */ | 526 | /* BTR processing for pre-DCE12 ASICs */ |
| 506 | if (acrtc->dm_irq_params.stream && | 527 | if (acrtc->dm_irq_params.stream && |
| @@ -552,7 +573,7 @@ static void dm_crtc_high_irq(void *interrupt_params) · 45 unmodified lines |
| 552 | * to dm_vupdate_high_irq after end of front-porch. | 573 | * to dm_vupdate_high_irq after end of front-porch. |
| 553 | */ | 574 | */ |
| 554 | if (!vrr_active) | 575 | if (!vrr_active) |
| 555 | drm_crtc_handle_vblank(&acrtc->base); | 576 | dm_crtc_handle_vblank(acrtc); |
| 556 | | 577 | |
| 557 | /** | 578 | /** |
| 558 | * Following stuff must happen at start of vblank, for crc | 579 | * Following stuff must happen at start of vblank, for crc |
| @@ -1382,6 +1403,41 @@ static bool dm_should_disable_stutter(struct pci_dev *pdev) · 823 unmodified lines |
| 1382 | return false; | 1403 | return false; |
| 1383 | } | 1404 | } |
| 1384 | | 1405 | |
| | 1406 | static const struct dmi_system_id hpd_disconnect_quirk_table[] = { |
| | 1407 | { |
| | 1408 | .matches = { |
| | 1409 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| | 1410 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"), |
| | 1411 | }, |
| | 1412 | }, |
| | 1413 | { |
| | 1414 | .matches = { |
| | 1415 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| | 1416 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"), |
| | 1417 | }, |
| | 1418 | }, |
| | 1419 | { |
| | 1420 | .matches = { |
| | 1421 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| | 1422 | DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"), |
| | 1423 | }, |
| | 1424 | }, |
| | 1425 | {} |
| | 1426 | }; |
| | 1427 | |
| | 1428 | static void retrieve_dmi_info(struct amdgpu_display_manager *dm) |
| | 1429 | { |
| | 1430 | const struct dmi_system_id *dmi_id; |
| | 1431 | |
| | 1432 | dm->aux_hpd_discon_quirk = false; |
| | 1433 | |
| | 1434 | dmi_id = dmi_first_match(hpd_disconnect_quirk_table); |
| | 1435 | if (dmi_id) { |
| | 1436 | dm->aux_hpd_discon_quirk = true; |
| | 1437 | DRM_INFO("aux_hpd_discon_quirk attached\n"); |
| | 1438 | } |
| | 1439 | } |
| | 1440 | |
| 1385 | static int amdgpu_dm_init(struct amdgpu_device *adev) | 1441 | static int amdgpu_dm_init(struct amdgpu_device *adev) |
| 1386 | { | 1442 | { |
| 1387 | struct dc_init_data init_data; | 1443 | struct dc_init_data init_data; |
| @@ -1508,6 +1564,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 120 unmodified lines |
| 1508 | } | 1564 | } |
| 1509 | | 1565 | |
| 1510 | INIT_LIST_HEAD(&adev->dm.da_list); | 1566 | INIT_LIST_HEAD(&adev->dm.da_list); |
| | 1567 | |
| | 1568 | retrieve_dmi_info(&adev->dm); |
| | 1569 | |
| 1511 | /* Display Core create. */ | 1570 | /* Display Core create. */ |
| 1512 | adev->dm.dc = dc_create(&init_data); | 1571 | adev->dm.dc = dc_create(&init_data); |
| 1513 | | 1572 | |
| @@ -5407,7 +5466,7 @@ fill_blending_from_plane_state(const struct drm_plane_state *plane_state, · 3893 unmodified lines |
| 5407 | } | 5466 | } |
| 5408 | } | 5467 | } |
| 5409 | | 5468 | |
| 5410 | if (per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) | 5469 | if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) |
| 5411 | *pre_multiplied_alpha = false; | 5470 | *pre_multiplied_alpha = false; |
| 5412 | } | 5471 | } |
| 5413 | | 5472 | |
| @@ -9135,6 +9194,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 3721 unmodified lines |
| 9135 | struct amdgpu_bo *abo; | 9194 | struct amdgpu_bo *abo; |
| 9136 | uint32_t target_vblank, last_flip_vblank; | 9195 | uint32_t target_vblank, last_flip_vblank; |
| 9137 | bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); | 9196 | bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); |
| | 9197 | bool cursor_update = false; |
| 9138 | bool pflip_present = false; | 9198 | bool pflip_present = false; |
| 9139 | struct { | 9199 | struct { |
| 9140 | struct dc_surface_update surface_updates[MAX_SURFACES]; | 9200 | struct dc_surface_update surface_updates[MAX_SURFACES]; |
| @@ -9170,8 +9230,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 29 unmodified lines |
| 9170 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); | 9230 | struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); |
| 9171 | | 9231 | |
| 9172 | /* Cursor plane is handled after stream updates */ | 9232 | /* Cursor plane is handled after stream updates */ |
| 9173 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | 9233 | if (plane->type == DRM_PLANE_TYPE_CURSOR) { |
| | 9234 | if ((fb && crtc == pcrtc) || |
| | 9235 | (old_plane_state->fb && old_plane_state->crtc == pcrtc)) |
| | 9236 | cursor_update = true; |
| | 9237 | |
| 9174 | continue; | 9238 | continue; |
| | 9239 | } |
| 9175 | | 9240 | |
| 9176 | if (!fb || !crtc || pcrtc != crtc) | 9241 | if (!fb || !crtc || pcrtc != crtc) |
| 9177 | continue; | 9242 | continue; |
| @@ -9334,6 +9399,17 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, · 156 unmodified lines |
| 9334 | bundle->stream_update.vrr_infopacket = | 9399 | bundle->stream_update.vrr_infopacket = |
| 9335 | &acrtc_state->stream->vrr_infopacket; | 9400 | &acrtc_state->stream->vrr_infopacket; |
| 9336 | } | 9401 | } |
| | 9402 | } else if (cursor_update && acrtc_state->active_planes > 0 && |
| | 9403 | !acrtc_state->force_dpms_off && |
| | 9404 | acrtc_attach->base.state->event) { |
| | 9405 | drm_crtc_vblank_get(pcrtc); |
| | 9406 | |
| | 9407 | spin_lock_irqsave(&pcrtc->dev->event_lock, flags); |
| | 9408 | |
| | 9409 | acrtc_attach->event = acrtc_attach->base.state->event; |
| | 9410 | acrtc_attach->base.state->event = NULL; |
| | 9411 | |
| | 9412 | spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); |
| 9337 | } | 9413 | } |
| 9338 | | 9414 | |
| 9339 | /* Update the planes if changed or disable if we don't have any. */ | 9415 | /* Update the planes if changed or disable if we don't have any. */ |