Merge tag 'perf-core-2026-06-14' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip

Pull performance events updates from Ingo Molnar: "Core perf code updates: - Reveal PMU type in fdinfo (Chun-Tse Shao) Intel CPU PMU driver updates: - Fix various inaccurate hard-coded event configurations (Dapeng Mi) Intel uncore PMU driver updates (Zide Chen): - Fix discovery unit lookup bug for multi-die systems - Guard against invalid box control address - Fix PCI device refcount leak in UPI discovery - Defer ADL global PMON enable to enable_box() to save power - Fix uncore_die_to_cpu() for offline dies - Implement global init callback for GNR uncore AMD CPU PMU driver updates: - Always use the NMI latency mitigation (Sandipan Das) AMD uncore PMU driver updates: - Use Node ID to identify DF and UMC domains (Sandipan Das)" * tag 'perf-core-2026-06-14' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip: (22 commits) perf/x86/amd/uncore: Use Node ID to identify DF and UMC domains perf: Reveal PMU type in fdinfo perf/x86/intel/uncore: Implement global init callback for GNR uncore perf/x86/intel/uncore: Fix uncore_die_to_cpu() for offline dies perf/x86/intel/uncore: Move die_to_cpu() to uncore.c perf/x86/intel/uncore: Defer ADL global PMON enable to enable_box() perf/x86/intel/uncore: Fix PCI device refcount leak in UPI discovery perf/x86/intel/uncore: Guard against invalid box control address perf/x86/intel/uncore: Fix discovery unit lookup for multi-die systems perf/x86/amd/core: Always use the NMI latency mitigation perf/x86/intel: Update event constraints and cache_extra_regsfor CWF perf/x86/intel: Update event constraints and cache_extra_regsfor SRF perf/x86/intel: Update event constraints and cache_extra_regsfor NVL perf/x86/intel: Update event constraints for PTL perf/x86/intel: Update event constraints and cache_extra_regsfor ARL perf/x86/intel: Update event constraints and cache_extra_regsfor LNL perf/x86/intel: Update event constraints and cache_extra_regsfor MTL perf/x86/intel: Update event constraints and cache_extra_regsfor ADL perf/x86/intel: Update event constraints for DMR perf/x86/intel: Update event constraints and cache_extra_regsfor SPR ...

Linus Torvalds committed 5 months ago

Commit 0bcc2dc2 parents d8d706a 67d277211 files · +540 −145Browse files

Unified · Split

11 files

arch/x86/events/amd/core.c +3 −3
arch/x86/events/amd/uncore.c +3 −3
arch/x86/events/intel/core.c +408 −81
arch/x86/events/intel/ds.c +17 −6
arch/x86/events/intel/uncore.c +31 −1
arch/x86/events/intel/uncore.h +2 −1
arch/x86/events/intel/uncore_discovery.c +31 −15
arch/x86/events/intel/uncore_snb.c +0 −7
arch/x86/events/intel/uncore_snbep.c +12 −24
arch/x86/events/perf_event.h +4 −4
kernel/events/core.c +29 −0

arch/x86/events/amd/core.c+3−3

@@ -1412,12 +1412,12 @@ static int __init amd_core_pmu_init(void) · 1411 unmodified lines
1412	1412	u64 even_ctr_mask = 0ULL;
1413	1413	int i;
1414	1414
1415		− if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
1416		− return 0;
1417		−
1418	1415	/* Avoid calculating the value each time in the NMI handler */
1419	1416	perf_nmi_window = msecs_to_jiffies(100);
1420	1417
	1418	+ if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
	1419	+ return 0;
	1420	+
1421	1421	/*
1422	1422	* If core performance counter extensions exists, we must use
1423	1423	* MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also

arch/x86/events/amd/uncore.c+3−3

@@ -700,7 +700,7 @@ void amd_uncore_df_ctx_scan(struct amd_uncore *uncore, unsigned int cpu) · 699 unmodified lines
700	700	info.split.aux_data = 0;
701	701	info.split.num_pmcs = NUM_COUNTERS_NB;
702	702	info.split.gid = 0;
703		− info.split.cid = topology_logical_package_id(cpu);
	703	+ info.split.cid = topology_amd_node_id(cpu);
704	704
705	705	if (pmu_version >= 2) {
706	706	ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
@@ -999,8 +999,8 @@ void amd_uncore_umc_ctx_scan(struct amd_uncore *uncore, unsigned int cpu) · 292 unmodified lines
999	999	cpuid(EXT_PERFMON_DEBUG_FEATURES, &eax, &ebx.full, &ecx, &edx);
1000	1000	info.split.aux_data = ecx; /* stash active mask */
1001	1001	info.split.num_pmcs = ebx.split.num_umc_pmc;
1002		− info.split.gid = topology_logical_package_id(cpu);
1003		− info.split.cid = topology_logical_package_id(cpu);
	1002	+ info.split.gid = topology_amd_node_id(cpu);
	1003	+ info.split.cid = topology_amd_node_id(cpu);
1004	1004	*per_cpu_ptr(uncore->info, cpu) = info;
1005	1005	}
1006	1006

arch/x86/events/intel/core.c+408−81

@@ -215,39 +215,47 @@ static struct event_constraint intel_slm_event_constraints[] __read_mostly = · 214 unmodified lines
215	215
216	216	static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
217	217	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
	218	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
218	219	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
219		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
	220	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	221	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
220	222	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
221	223	EVENT_CONSTRAINT_END
222	224	};
223	225
224	226	static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
225	227	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
	228	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
226	229	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
227		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
	230	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	231	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
228	232	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
229	233	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
	234	+ FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
230	235	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
	236	+ FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
231	237	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
	238	+ FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
232	239	EVENT_CONSTRAINT_END
233	240	};
234	241
235	242	static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
236	243	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
	244	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
237	245	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
238		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
	246	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	247	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
239	248	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
240	249	FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
	250	+ FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
241	251	FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
	252	+ FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
242	253	FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
	254	+ FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
243	255	INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
244	256	INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
245	257	INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
246	258	INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
247		− INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1),
248		− INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2),
249		− INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4),
250		− INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8),
251	259	INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
252	260	INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
253	261	INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
@@ -310,10 +318,11 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = { · 56 unmodified lines
310	318	static struct event_constraint intel_icl_event_constraints[] = {
311	319	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
312	320	FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
313		− FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
	321	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
314	322	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
315		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
316		− FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
	323	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	324	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
	325	+ FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
317	326	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
318	327	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
319	328	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -355,11 +364,12 @@ static struct extra_reg intel_glc_extra_regs[] __read_mostly = { · 35 unmodified lines
355	364
356	365	static struct event_constraint intel_glc_event_constraints[] = {
357	366	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
358		− FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
	367	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
359	368	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
360		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
	369	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	370	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
361	371	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
362		− FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
	372	+ FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
363	373	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
364	374	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
365	375	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -379,9 +389,13 @@ static struct event_constraint intel_glc_event_constraints[] = { · 13 unmodified lines
379	389
380	390	INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
381	391	INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
	392	+ INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
	393	+ INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
382	394	INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
	395	+ INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
383	396	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
384	397	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
	398	+ INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
385	399	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
386	400	INTEL_EVENT_CONSTRAINT(0xce, 0x1),
387	401	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
@@ -407,11 +421,12 @@ static struct extra_reg intel_rwc_extra_regs[] __read_mostly = { · 19 unmodified lines
407	421
408	422	static struct event_constraint intel_lnc_event_constraints[] = {
409	423	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
410		− FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
	424	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
411	425	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
412		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
	426	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	427	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
413	428	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
414		− FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
	429	+ FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
415	430	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
416	431	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
417	432	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -423,8 +438,6 @@ static struct event_constraint intel_lnc_event_constraints[] = { · 5 unmodified lines
423	438
424	439	INTEL_EVENT_CONSTRAINT(0x20, 0xf),
425	440
426		− INTEL_UEVENT_CONSTRAINT(0x012a, 0xf),
427		− INTEL_UEVENT_CONSTRAINT(0x012b, 0xf),
428	441	INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
429	442	INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
430	443
@@ -435,15 +448,14 @@ static struct event_constraint intel_lnc_event_constraints[] = { · 4 unmodified lines
435	448	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
436	449	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
437	450	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
438		− INTEL_UEVENT_CONSTRAINT(0x10a4, 0x1),
	451	+ INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8),
439	452	INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
440	453	INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
441	454	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
442	455
	456	+ INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff),
443	457	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
444	458
445		− INTEL_UEVENT_CONSTRAINT(0x00e0, 0xf),
446		−
447	459	EVENT_CONSTRAINT_END
448	460	};
449	461
@@ -460,11 +472,12 @@ static struct extra_reg intel_lnc_extra_regs[] __read_mostly = { · 10 unmodified lines
460	472
461	473	static struct event_constraint intel_pnc_event_constraints[] = {
462	474	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
463		− FIXED_EVENT_CONSTRAINT(0x0100, 0), /* INST_RETIRED.PREC_DIST */
	475	+ FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
464	476	FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
465		− FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
	477	+ FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
	478	+ FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
466	479	FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
467		− FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
	480	+ FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
468	481	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
469	482	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
470	483	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
@@ -706,6 +719,80 @@ static __initconst const u64 glc_hw_cache_event_ids · 235 unmodified lines
706	719	},
707	720	};
708	721
	722	+/* ADL P-core (Golden cove) specific event code. */
	723	+static __initconst const u64 adl_glc_hw_cache_event_ids
	724	+ [PERF_COUNT_HW_CACHE_MAX]
	725	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	726	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
	727	+{
	728	+ [ C(L1D ) ] = {
	729	+ [ C(OP_READ) ] = {
	730	+ [ C(RESULT_ACCESS) ] = 0x81d0,
	731	+ [ C(RESULT_MISS) ] = 0xe124,
	732	+ },
	733	+ [ C(OP_WRITE) ] = {
	734	+ [ C(RESULT_ACCESS) ] = 0x82d0,
	735	+ },
	736	+ },
	737	+ [ C(L1I ) ] = {
	738	+ [ C(OP_READ) ] = {
	739	+ [ C(RESULT_MISS) ] = 0xe424,
	740	+ },
	741	+ [ C(OP_WRITE) ] = {
	742	+ [ C(RESULT_ACCESS) ] = -1,
	743	+ [ C(RESULT_MISS) ] = -1,
	744	+ },
	745	+ },
	746	+ [ C(LL ) ] = {
	747	+ [ C(OP_READ) ] = {
	748	+ [ C(RESULT_ACCESS) ] = 0x12a,
	749	+ [ C(RESULT_MISS) ] = 0x12a,
	750	+ },
	751	+ [ C(OP_WRITE) ] = {
	752	+ [ C(RESULT_ACCESS) ] = 0x12a,
	753	+ [ C(RESULT_MISS) ] = 0x12a,
	754	+ },
	755	+ },
	756	+ [ C(DTLB) ] = {
	757	+ [ C(OP_READ) ] = {
	758	+ [ C(RESULT_ACCESS) ] = 0x81d0,
	759	+ [ C(RESULT_MISS) ] = 0xe12,
	760	+ },
	761	+ [ C(OP_WRITE) ] = {
	762	+ [ C(RESULT_ACCESS) ] = 0x82d0,
	763	+ [ C(RESULT_MISS) ] = 0xe13,
	764	+ },
	765	+ },
	766	+ [ C(ITLB) ] = {
	767	+ [ C(OP_READ) ] = {
	768	+ [ C(RESULT_ACCESS) ] = -1,
	769	+ [ C(RESULT_MISS) ] = 0xe11,
	770	+ },
	771	+ [ C(OP_WRITE) ] = {
	772	+ [ C(RESULT_ACCESS) ] = -1,
	773	+ [ C(RESULT_MISS) ] = -1,
	774	+ },
	775	+ [ C(OP_PREFETCH) ] = {
	776	+ [ C(RESULT_ACCESS) ] = -1,
	777	+ [ C(RESULT_MISS) ] = -1,
	778	+ },
	779	+ },
	780	+ [ C(BPU ) ] = {
	781	+ [ C(OP_READ) ] = {
	782	+ [ C(RESULT_ACCESS) ] = 0x4c4,
	783	+ [ C(RESULT_MISS) ] = 0x4c5,
	784	+ },
	785	+ [ C(OP_WRITE) ] = {
	786	+ [ C(RESULT_ACCESS) ] = -1,
	787	+ [ C(RESULT_MISS) ] = -1,
	788	+ },
	789	+ [ C(OP_PREFETCH) ] = {
	790	+ [ C(RESULT_ACCESS) ] = -1,
	791	+ [ C(RESULT_MISS) ] = -1,
	792	+ },
	793	+ },
	794	+};
	795	+
709	796	static __initconst const u64 glc_hw_cache_extra_regs
710	797	[PERF_COUNT_HW_CACHE_MAX]
711	798	[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -713,18 +800,71 @@ static __initconst const u64 glc_hw_cache_extra_regs · 1 unmodified line
713	800	{
714	801	[ C(LL ) ] = {
715	802	[ C(OP_READ) ] = {
716		− [ C(RESULT_ACCESS) ] = 0x10001,
717		− [ C(RESULT_MISS) ] = 0x3fbfc00001,
	803	+ [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	804	+ [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
718	805	},
719	806	[ C(OP_WRITE) ] = {
720		− [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
721		− [ C(RESULT_MISS) ] = 0x3f3fc00002,
	807	+ [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	808	+ [ C(RESULT_MISS) ] = 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */
722	809	},
723	810	},
724	811	[ C(NODE) ] = {
725	812	[ C(OP_READ) ] = {
726		− [ C(RESULT_ACCESS) ] = 0x10c000001,
727		− [ C(RESULT_MISS) ] = 0x3fb3000001,
	813	+ [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
	814	+ [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
	815	+ },
	816	+ },
	817	+};
	818	+
	819	+/* ADL P-core (Golden cove) specific extra regs value. */
	820	+static __initconst const u64 adl_glc_hw_cache_extra_regs
	821	+ [PERF_COUNT_HW_CACHE_MAX]
	822	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	823	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
	824	+{
	825	+ [ C(LL ) ] = {
	826	+ [ C(OP_READ) ] = {
	827	+ [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	828	+ [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	829	+ },
	830	+ [ C(OP_WRITE) ] = {
	831	+ [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	832	+ [ C(RESULT_MISS) ] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
	833	+ },
	834	+ },
	835	+};
	836	+
	837	+static __initconst const u64 lnc_hw_cache_extra_regs
	838	+ [PERF_COUNT_HW_CACHE_MAX]
	839	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	840	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
	841	+{
	842	+ [ C(LL ) ] = {
	843	+ [ C(OP_READ) ] = {
	844	+ [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	845	+ [ C(RESULT_MISS) ] = 0x9E7FA000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	846	+ },
	847	+ [ C(OP_WRITE) ] = {
	848	+ [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	849	+ [ C(RESULT_MISS) ] = 0x9E7FA000002, /* OCR.DEMAND_RFO.L3_MISS */
	850	+ },
	851	+ },
	852	+};
	853	+
	854	+/* ARL specific lioncove hw_cache_extra_regs[] variant. */
	855	+static __initconst const u64 arl_lnc_hw_cache_extra_regs
	856	+ [PERF_COUNT_HW_CACHE_MAX]
	857	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	858	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
	859	+{
	860	+ [ C(LL ) ] = {
	861	+ [ C(OP_READ) ] = {
	862	+ [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	863	+ [ C(RESULT_MISS) ] = 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	864	+ },
	865	+ [ C(OP_WRITE) ] = {
	866	+ [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	867	+ [ C(RESULT_MISS) ] = 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */
728	868	},
729	869	},
730	870	};
@@ -815,12 +955,29 @@ static __initconst const u64 pnc_hw_cache_extra_regs · 84 unmodified lines
815	955	{
816	956	[ C(LL ) ] = {
817	957	[ C(OP_READ) ] = {
818		− [ C(RESULT_ACCESS) ] = 0x4000000000000001,
819		− [ C(RESULT_MISS) ] = 0xFFFFF000000001,
	958	+ [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
	959	+ [ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
820	960	},
821	961	[ C(OP_WRITE) ] = {
822		− [ C(RESULT_ACCESS) ] = 0x4000000000000002,
823		− [ C(RESULT_MISS) ] = 0xFFFFF000000002,
	962	+ [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
	963	+ [ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */
	964	+ },
	965	+ },
	966	+};
	967	+
	968	+static __initconst const u64 cyc_hw_cache_extra_regs
	969	+ [PERF_COUNT_HW_CACHE_MAX]
	970	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	971	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
	972	+{
	973	+ [ C(LL ) ] = {
	974	+ [ C(OP_READ) ] = {
	975	+ [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
	976	+ [ C(RESULT_MISS) ] = 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
	977	+ },
	978	+ [ C(OP_WRITE) ] = {
	979	+ [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
	980	+ [ C(RESULT_MISS) ] = 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */
824	981	},
825	982	},
826	983	};
@@ -1019,6 +1176,41 @@ static __initconst const u64 skl_hw_cache_extra_regs · 192 unmodified lines
1019	1176	},
1020	1177	};
1021	1178
	1179	+static __initconst const u64 snc_hw_cache_extra_regs
	1180	+ [PERF_COUNT_HW_CACHE_MAX]
	1181	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	1182	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
	1183	+{
	1184	+ [ C(LL ) ] = {
	1185	+ [ C(OP_READ) ] = {
	1186	+ [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	1187	+ [ C(RESULT_MISS) ] = 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	1188	+ },
	1189	+ [ C(OP_WRITE) ] = {
	1190	+ [ C(RESULT_ACCESS) ] = 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	1191	+ [ C(RESULT_MISS) ] = 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */
	1192	+ },
	1193	+ [ C(OP_PREFETCH) ] = {
	1194	+ [ C(RESULT_ACCESS) ] = 0x0,
	1195	+ [ C(RESULT_MISS) ] = 0x0,
	1196	+ },
	1197	+ },
	1198	+ [ C(NODE) ] = {
	1199	+ [ C(OP_READ) ] = {
	1200	+ [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
	1201	+ [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
	1202	+ },
	1203	+ [ C(OP_WRITE) ] = {
	1204	+ [ C(RESULT_ACCESS) ] = 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */
	1205	+ [ C(RESULT_MISS) ] = 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */
	1206	+ },
	1207	+ [ C(OP_PREFETCH) ] = {
	1208	+ [ C(RESULT_ACCESS) ] = 0x0,
	1209	+ [ C(RESULT_MISS) ] = 0x0,
	1210	+ },
	1211	+ },
	1212	+};
	1213	+
1022	1214	#define SNB_DMND_DATA_RD (1ULL << 0)
1023	1215	#define SNB_DMND_RFO (1ULL << 1)
1024	1216	#define SNB_DMND_IFETCH (1ULL << 2)
@@ -2342,22 +2534,82 @@ static __initconst const u64 tnt_hw_cache_extra_regs · 1317 unmodified lines
2342	2534	},
2343	2535	};
2344	2536
2345		−static __initconst const u64 arw_hw_cache_extra_regs
	2537	+static __initconst const u64 grt_hw_cache_extra_regs
2346	2538	[PERF_COUNT_HW_CACHE_MAX]
2347	2539	[PERF_COUNT_HW_CACHE_OP_MAX]
2348	2540	[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2349	2541	[C(LL)] = {
2350	2542	[C(OP_READ)] = {
2351		− [C(RESULT_ACCESS)] = 0x4000000000000001,
2352		− [C(RESULT_MISS)] = 0xFFFFF000000001,
	2543	+ [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	2544	+ [C(RESULT_MISS)] = 0x3F84400001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2353	2545	},
2354	2546	[C(OP_WRITE)] = {
2355		− [C(RESULT_ACCESS)] = 0x4000000000000002,
2356		− [C(RESULT_MISS)] = 0xFFFFF000000002,
	2547	+ [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	2548	+ [C(RESULT_MISS)] = 0x3F84400002, /* OCR.DEMAND_RFO.L3_MISS */
2357	2549	},
2358		− [C(OP_PREFETCH)] = {
2359		− [C(RESULT_ACCESS)] = 0x0,
2360		− [C(RESULT_MISS)] = 0x0,
	2550	+ },
	2551	+};
	2552	+
	2553	+static __initconst const u64 cmt_hw_cache_extra_regs
	2554	+ [PERF_COUNT_HW_CACHE_MAX]
	2555	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	2556	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
	2557	+ [C(LL)] = {
	2558	+ [C(OP_READ)] = {
	2559	+ [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	2560	+ [C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	2561	+ },
	2562	+ [C(OP_WRITE)] = {
	2563	+ [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	2564	+ [C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
	2565	+ },
	2566	+ },
	2567	+};
	2568	+
	2569	+static __initconst const u64 skt_hw_cache_extra_regs
	2570	+ [PERF_COUNT_HW_CACHE_MAX]
	2571	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	2572	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
	2573	+ [C(LL)] = {
	2574	+ [C(OP_READ)] = {
	2575	+ [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	2576	+ [C(RESULT_MISS)] = 0x13FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	2577	+ },
	2578	+ [C(OP_WRITE)] = {
	2579	+ [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	2580	+ [C(RESULT_MISS)] = 0x13FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
	2581	+ },
	2582	+ },
	2583	+};
	2584	+
	2585	+static __initconst const u64 dkt_hw_cache_extra_regs
	2586	+ [PERF_COUNT_HW_CACHE_MAX]
	2587	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	2588	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
	2589	+ [C(LL)] = {
	2590	+ [C(OP_READ)] = {
	2591	+ [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
	2592	+ [C(RESULT_MISS)] = 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
	2593	+ },
	2594	+ [C(OP_WRITE)] = {
	2595	+ [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
	2596	+ [C(RESULT_MISS)] = 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
	2597	+ },
	2598	+ },
	2599	+};
	2600	+
	2601	+static __initconst const u64 arw_hw_cache_extra_regs
	2602	+ [PERF_COUNT_HW_CACHE_MAX]
	2603	+ [PERF_COUNT_HW_CACHE_OP_MAX]
	2604	+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
	2605	+ [C(LL)] = {
	2606	+ [C(OP_READ)] = {
	2607	+ [C(RESULT_ACCESS)] = 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
	2608	+ [C(RESULT_MISS)] = 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */
	2609	+ },
	2610	+ [C(OP_WRITE)] = {
	2611	+ [C(RESULT_ACCESS)] = 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPONSE */
	2612	+ [C(RESULT_MISS)] = 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */
2361	2613	},
2362	2614	},
2363	2615	};
@@ -2392,9 +2644,12 @@ static struct attribute *grt_mem_attrs[] = { · 28 unmodified lines
2392	2644	};
2393	2645
2394	2646	static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2395		− /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2396		− INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
2397		− INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
	2647	+ /*
	2648	+ * Must define OFFCORE_RSP_X first, see intel_fixup_er().
	2649	+ * Bit 63 only valid on OFFCORE_RSP_0 MSR.
	2650	+ */
	2651	+ INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x8003f03fffffffffull, RSP_0),
	2652	+ INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3f03fffffffffull, RSP_1),
2398	2653	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2399	2654	EVENT_EXTRA_END
2400	2655	};
@@ -2426,10 +2681,6 @@ static struct extra_reg intel_arw_extra_regs[] __read_mostly = { · 25 unmodified lines
2426	2681	INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2427	2682	INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2428	2683	INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2429		− INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2430		− INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2431		− INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2432		− INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2433	2684	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2434	2685	INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2435	2686	INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
@@ -3169,10 +3420,10 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) · 733 unmodified lines
3169	3420	wrmsrl(msr_b + msr_offset, mask);
3170	3421	cpuc->acr_cfg_b[idx] = mask;
3171	3422	}
3172		− /* Only need to update the reload value when there is a valid config value. */
3173		− if (mask && cpuc->acr_cfg_c[idx] != reload) {
	3423	+ /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */
	3424	+ if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) {
3174	3425	wrmsrl(msr_c + msr_offset, reload);
3175		− cpuc->acr_cfg_c[idx] = reload;
	3426	+ cpuc->cfg_c_val[idx] = reload;
3176	3427	}
3177	3428	}
3178	3429
@@ -3198,14 +3449,15 @@ static void intel_pmu_enable_event_ext(struct perf_event *event) · 19 unmodified lines
3198	3449	{
3199	3450	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3200	3451	struct hw_perf_event *hwc = &event->hw;
3201		− union arch_pebs_index old, new;
3202		− struct arch_pebs_cap cap;
3203	3452	u64 ext = 0;
3204	3453
3205		− cap = hybrid(cpuc->pmu, arch_pebs_cap);
	3454	+ if (is_acr_event_group(event))
	3455	+ ext \|= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3206	3456
3207	3457	if (event->attr.precise_ip) {
3208	3458	u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
	3459	+ struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);
	3460	+ union arch_pebs_index old, new;
3209	3461
3210	3462	ext \|= ARCH_PEBS_EN;
3211	3463	if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
@@ -7490,6 +7742,15 @@ static __always_inline void intel_pmu_init_glc(struct pmu *pmu) · 4278 unmodified lines
7490	7742	intel_pmu_ref_cycles_ext();
7491	7743	}
7492	7744
	7745	+static __always_inline void intel_pmu_init_glc_hybrid(struct pmu *pmu)
	7746	+{
	7747	+ intel_pmu_init_glc(pmu);
	7748	+
	7749	+ /* ADL has different extra MSR values from Server for the L3 or node OCR/OMR events. */
	7750	+ memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
	7751	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs), adl_glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	7752	+}
	7753	+
7493	7754	static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
7494	7755	{
7495	7756	x86_pmu.mid_ack = true;
@@ -7502,7 +7763,7 @@ static __always_inline void intel_pmu_init_grt(struct pmu *pmu) · 6 unmodified lines
7502	7763	x86_pmu.flags \|= PMU_FL_INSTR_LATENCY;
7503	7764
7504	7765	memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7505		− memcpy(hybrid_var(pmu, hw_cache_extra_regs), tnt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	7766	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs), grt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7506	7767	hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7507	7768	hybrid(pmu, event_constraints) = intel_grt_event_constraints;
7508	7769	hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
@@ -7511,12 +7772,24 @@ static __always_inline void intel_pmu_init_grt(struct pmu *pmu) · 2 unmodified lines
7511	7772	intel_pmu_ref_cycles_ext();
7512	7773	}
7513	7774
	7775	+static __always_inline void intel_pmu_init_cmt(struct pmu *pmu)
	7776	+{
	7777	+ intel_pmu_init_grt(pmu);
	7778	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs),
	7779	+ cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	7780	+ hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;
	7781	+ hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
	7782	+}
	7783	+
7514	7784	static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
7515	7785	{
7516	7786	intel_pmu_init_glc(pmu);
7517	7787	hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
7518	7788	hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
7519	7789	hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
	7790	+
	7791	+ memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
	7792	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7520	7793	}
7521	7794
7522	7795	static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
@@ -7534,14 +7807,41 @@ static __always_inline void intel_pmu_init_pnc(struct pmu *pmu) · 11 unmodified lines
7534	7807	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7535	7808	}
7536	7809
	7810	+static __always_inline void intel_pmu_init_cyc(struct pmu *pmu)
	7811	+{
	7812	+ intel_pmu_init_pnc(pmu);
	7813	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs),
	7814	+ cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	7815	+}
	7816	+
7537	7817	static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
7538	7818	{
7539		− intel_pmu_init_grt(pmu);
	7819	+ intel_pmu_init_cmt(pmu);
7540	7820	hybrid(pmu, event_constraints) = intel_skt_event_constraints;
7541		− hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
	7821	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs),
	7822	+ skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7542	7823	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7543	7824	}
7544	7825
	7826	+/* Hybrid client variant. */
	7827	+static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
	7828	+{
	7829	+ intel_pmu_init_skt(pmu);
	7830	+ hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
	7831	+}
	7832	+
	7833	+/*
	7834	+ * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR
	7835	+ * events require different extra MSR values. Keep a separate init
	7836	+ * function for the non-hybrid server variant.
	7837	+ */
	7838	+static __always_inline void intel_pmu_init_dkt(struct pmu *pmu)
	7839	+{
	7840	+ intel_pmu_init_dkt_hybrid(pmu);
	7841	+ memcpy(hybrid_var(pmu, hw_cache_extra_regs),
	7842	+ dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	7843	+}
	7844	+
7545	7845	static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
7546	7846	{
7547	7847	intel_pmu_init_grt(pmu);
@@ -7550,7 +7850,7 @@ static __always_inline void intel_pmu_init_arw(struct pmu *pmu) · 2 unmodified lines
7550	7850	memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7551	7851	arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7552	7852	hybrid(pmu, event_constraints) = intel_arw_event_constraints;
7553		− hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints;
	7853	+ hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
7554	7854	hybrid(pmu, extra_regs) = intel_arw_extra_regs;
7555	7855	static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7556	7856	}
@@ -7864,8 +8164,7 @@ __init int intel_pmu_init(void) · 307 unmodified lines
7864	8164
7865	8165	case INTEL_ATOM_CRESTMONT:
7866	8166	case INTEL_ATOM_CRESTMONT_X:
7867		− intel_pmu_init_grt(NULL);
7868		− x86_pmu.extra_regs = intel_cmt_extra_regs;
	8167	+ intel_pmu_init_cmt(NULL);
7869	8168	intel_pmu_pebs_data_source_cmt();
7870	8169	x86_pmu.pebs_latency_data = cmt_latency_data;
7871	8170	x86_pmu.get_event_constraints = cmt_get_event_constraints;
@@ -7877,7 +8176,7 @@ __init int intel_pmu_init(void) · 5 unmodified lines
7877	8176	break;
7878	8177
7879	8178	case INTEL_ATOM_DARKMONT_X:
7880		− intel_pmu_init_skt(NULL);
	8179	+ intel_pmu_init_dkt(NULL);
7881	8180	intel_pmu_pebs_data_source_cmt();
7882	8181	x86_pmu.pebs_latency_data = cmt_latency_data;
7883	8182	x86_pmu.get_event_constraints = cmt_get_event_constraints;
@@ -8153,17 +8452,19 @@ __init int intel_pmu_init(void) · 269 unmodified lines
8153	8452
8154	8453	case INTEL_ICELAKE_X:
8155	8454	case INTEL_ICELAKE_D:
	8455	+ memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8156	8456	x86_pmu.pebs_ept = 1;
8157	8457	pmem = true;
8158		− fallthrough;
	8458	+ goto snc_common;
8159	8459	case INTEL_ICELAKE_L:
8160	8460	case INTEL_ICELAKE:
8161	8461	case INTEL_TIGERLAKE_L:
8162	8462	case INTEL_TIGERLAKE:
8163	8463	case INTEL_ROCKETLAKE:
	8464	+ memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	8465	+ snc_common:
8164	8466	x86_pmu.late_ack = true;
8165	8467	memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8166		− memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8167	8468	hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8168	8469	intel_pmu_lbr_init_skl();
8169	8470
@@ -8259,7 +8560,7 @@ __init int intel_pmu_init(void) · 89 unmodified lines
8259	8560
8260	8561	/* Initialize big core specific PerfMon capabilities.*/
8261	8562	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8262		− intel_pmu_init_glc(&pmu->pmu);
	8563	+ intel_pmu_init_glc_hybrid(&pmu->pmu);
8263	8564	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
8264	8565	pmu->cntr_mask64 <<= 2;
8265	8566	pmu->cntr_mask64 \|= 0x3;
@@ -8316,13 +8617,12 @@ __init int intel_pmu_init(void) · 50 unmodified lines
8316	8617
8317	8618	/* Initialize big core specific PerfMon capabilities.*/
8318	8619	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8319		− intel_pmu_init_glc(&pmu->pmu);
	8620	+ intel_pmu_init_glc_hybrid(&pmu->pmu);
8320	8621	pmu->extra_regs = intel_rwc_extra_regs;
8321	8622
8322	8623	/* Initialize Atom core specific PerfMon capabilities.*/
8323	8624	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8324		− intel_pmu_init_grt(&pmu->pmu);
8325		− pmu->extra_regs = intel_cmt_extra_regs;
	8625	+ intel_pmu_init_cmt(&pmu->pmu);
8326	8626
8327	8627	intel_pmu_pebs_data_source_mtl();
8328	8628	pr_cont("Meteorlake Hybrid events, ");
@@ -8333,16 +8633,50 @@ __init int intel_pmu_init(void) · 4 unmodified lines
8333	8633	case INTEL_WILDCATLAKE_L:
8334	8634	pr_cont("Pantherlake Hybrid events, ");
8335	8635	name = "pantherlake_hybrid";
	8636	+
	8637	+ intel_pmu_init_hybrid(hybrid_big_small);
	8638	+
	8639	+ /* Initialize big core specific PerfMon capabilities.*/
	8640	+ pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
	8641	+ intel_pmu_init_lnc(&pmu->pmu);
	8642	+ /* Initialize Atom core specific PerfMon capabilities.*/
	8643	+ pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
	8644	+ intel_pmu_init_dkt_hybrid(&pmu->pmu);
	8645	+
8336	8646	goto lnl_common;
8337	8647
8338		− case INTEL_LUNARLAKE_M:
8339	8648	case INTEL_ARROWLAKE:
	8649	+ pr_cont("Arrowlake Hybrid events, ");
	8650	+ name = "arrowlake_hybrid";
	8651	+
	8652	+ intel_pmu_init_hybrid(hybrid_big_small);
	8653	+
	8654	+ /* Initialize big core specific PerfMon capabilities.*/
	8655	+ pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
	8656	+ intel_pmu_init_lnc(&pmu->pmu);
	8657	+ memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
	8658	+ arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
	8659	+ /* Initialize Atom core specific PerfMon capabilities.*/
	8660	+ pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
	8661	+ intel_pmu_init_skt(&pmu->pmu);
	8662	+
	8663	+ goto lnl_common;
	8664	+
	8665	+ case INTEL_LUNARLAKE_M:
8340	8666	pr_cont("Lunarlake Hybrid events, ");
8341	8667	name = "lunarlake_hybrid";
8342	8668
8343		− lnl_common:
8344	8669	intel_pmu_init_hybrid(hybrid_big_small);
8345	8670
	8671	+ /* Initialize big core specific PerfMon capabilities.*/
	8672	+ pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
	8673	+ intel_pmu_init_lnc(&pmu->pmu);
	8674	+ /* Initialize Atom core specific PerfMon capabilities.*/
	8675	+ pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
	8676	+ intel_pmu_init_skt(&pmu->pmu);
	8677	+
	8678	+ lnl_common:
	8679	+
8346	8680	x86_pmu.pebs_latency_data = lnl_latency_data;
8347	8681	x86_pmu.get_event_constraints = mtl_get_event_constraints;
8348	8682	x86_pmu.hw_config = adl_hw_config;
@@ -8353,14 +8687,6 @@ __init int intel_pmu_init(void) · 4 unmodified lines
8353	8687	extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8354	8688	mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8355	8689
8356		− /* Initialize big core specific PerfMon capabilities.*/
8357		− pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8358		− intel_pmu_init_lnc(&pmu->pmu);
8359		−
8360		− /* Initialize Atom core specific PerfMon capabilities.*/
8361		− pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8362		− intel_pmu_init_skt(&pmu->pmu);
8363		−
8364	8690	intel_pmu_pebs_data_source_lnl();
8365	8691	break;
8366	8692
@@ -8380,6 +8706,8 @@ __init int intel_pmu_init(void) · 13 unmodified lines
8380	8706	/* Initialize big core specific PerfMon capabilities. */
8381	8707	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8382	8708	intel_pmu_init_lnc(&pmu->pmu);
	8709	+ memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
	8710	+ arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8383	8711
8384	8712	/* Initialize Atom core specific PerfMon capabilities. */
8385	8713	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
@@ -8387,8 +8715,7 @@ __init int intel_pmu_init(void) · 1 unmodified line
8387	8715
8388	8716	/* Initialize Lower Power Atom specific PerfMon capabilities. */
8389	8717	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
8390		− intel_pmu_init_grt(&pmu->pmu);
8391		− pmu->extra_regs = intel_cmt_extra_regs;
	8718	+ intel_pmu_init_cmt(&pmu->pmu);
8392	8719
8393	8720	intel_pmu_pebs_data_source_arl_h();
8394	8721	pr_cont("ArrowLake-H Hybrid events, ");
@@ -8413,7 +8740,7 @@ __init int intel_pmu_init(void) · 18 unmodified lines
8413	8740
8414	8741	/* Initialize big core specific PerfMon capabilities.*/
8415	8742	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8416		− intel_pmu_init_pnc(&pmu->pmu);
	8743	+ intel_pmu_init_cyc(&pmu->pmu);
8417	8744
8418	8745	/* Initialize Atom core specific PerfMon capabilities.*/
8419	8746	pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];

arch/x86/events/intel/ds.c+17−6

@@ -1292,18 +1292,21 @@ struct event_constraint intel_glm_pebs_event_constraints[] = { · 1291 unmodified lines
1292	1292	struct event_constraint intel_grt_pebs_event_constraints[] = {
1293	1293	/* Allow all events as PEBS with no flags */
1294	1294	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
1295		− INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
	1295	+ INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0x3f),
1296	1296	EVENT_CONSTRAINT_END
1297	1297	};
1298	1298
1299		−struct event_constraint intel_arw_pebs_event_constraints[] = {
	1299	+struct event_constraint intel_cmt_pebs_event_constraints[] = {
	1300	+ /* Allow all events as PEBS with no flags */
	1301	+ INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
	1302	+ INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
	1303	+ EVENT_CONSTRAINT_END
	1304	+};
	1305	+
	1306	+struct event_constraint intel_dkt_pebs_event_constraints[] = {
1300	1307	/* Allow all events as PEBS with no flags */
1301	1308	INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
1302	1309	INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
1303		− INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1),
1304		− INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2),
1305		− INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4),
1306		− INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8),
1307	1310	EVENT_CONSTRAINT_END
1308	1311	};
1309	1312
@@ -1500,6 +1503,13 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = { · 190 unmodified lines
1500	1503	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
1501	1504	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1502	1505
	1506	+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x012a, 0x1), /* OCR.* events */
	1507	+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x012b, 0x1), /* OCR.* events */
	1508	+
	1509	+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x04a4, 0x1), /* TOPDOWN.BAD_SPEC_SLOTS */
	1510	+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x08a4, 0x1), /* TOPDOWN.BR_MISPREDICT_SLOTS */
	1511	+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x10a4, 0x8), /* TOPDOWN.MEMORY_BOUND_SLOTS */
	1512	+
1503	1513	INTEL_HYBRID_LDLAT_CONSTRAINT(0x1cd, 0x3fc),
1504	1514	INTEL_HYBRID_STLAT_CONSTRAINT(0x2cd, 0x3),
1505	1515	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
@@ -1509,6 +1519,7 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = { · 3 unmodified lines
1509	1519	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1510	1520	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1511	1521	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
	1522	+ INTEL_FLAGS_UEVENT_CONSTRAINT(0x87d0, 0x3ff), /* MEM_INST_RETIRED.ANY */
1512	1523
1513	1524	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1514	1525

arch/x86/events/intel/uncore.c+31−1

@@ -83,6 +83,25 @@ int uncore_device_to_die(struct pci_dev *dev) · 82 unmodified lines
83	83	return -1;
84	84	}
85	85
	86	+/*
	87	+ * Using cpus_read_lock() to ensure cpu is not going down between
	88	+ * looking at cpu_online_mask.
	89	+ *
	90	+ * The lock must be held by the caller.
	91	+ */
	92	+int uncore_die_to_cpu(int die)
	93	+{
	94	+ int res = -1, cpu;
	95	+
	96	+ for_each_online_cpu(cpu) {
	97	+ if (topology_logical_die_id(cpu) == die) {
	98	+ res = cpu;
	99	+ break;
	100	+ }
	101	+ }
	102	+ return res;
	103	+}
	104	+
86	105	static void uncore_free_pcibus_map(void)
87	106	{
88	107	struct pci2phy_map map, tmp;
@@ -1697,7 +1716,7 @@ err: · 1608 unmodified lines
1697	1716	return ret;
1698	1717	}
1699	1718
1700		−static int uncore_mmio_global_init(u64 ctl)
	1719	+static int uncore_mmio_global_init(int die, u64 ctl)
1701	1720	{
1702	1721	void __iomem *io_addr;
1703	1722
@@ -1712,6 +1731,16 @@ static int uncore_mmio_global_init(u64 ctl) · 8 unmodified lines
1712	1731	return 0;
1713	1732	}
1714	1733
	1734	+static int uncore_msr_global_init(int die, u64 msr)
	1735	+{
	1736	+ int cpu = uncore_die_to_cpu(die);
	1737	+
	1738	+ if (cpu == -1)
	1739	+ return -ENODEV;
	1740	+
	1741	+ return wrmsrq_on_cpu(cpu, msr, 0);
	1742	+}
	1743	+
1715	1744	static const struct uncore_plat_init nhm_uncore_init __initconst = {
1716	1745	.cpu_init = nhm_uncore_cpu_init,
1717	1746	};
@@ -1852,6 +1881,7 @@ static const struct uncore_plat_init gnr_uncore_init __initconst = { · 134 unmodified lines
1852	1881	.domain[0].base_is_pci = true,
1853	1882	.domain[0].discovery_base = UNCORE_DISCOVERY_TABLE_DEVICE,
1854	1883	.domain[0].units_ignore = gnr_uncore_units_ignore,
	1884	+ .domain[0].global_init = uncore_msr_global_init,
1855	1885	};
1856	1886
1857	1887	static const struct uncore_plat_init dmr_uncore_init __initconst = {

arch/x86/events/intel/uncore.h+2−1

@@ -53,7 +53,7 @@ struct uncore_discovery_domain { · 52 unmodified lines
53	53	/* MSR address or PCI device used as the discovery base */
54	54	u32 discovery_base;
55	55	bool base_is_pci;
56		− int (*global_init)(u64 ctl);
	56	+ int (*global_init)(int die, u64 ctl);
57	57
58	58	/* The units in the discovery table should be ignored. */
59	59	int *units_ignore;
@@ -235,6 +235,7 @@ struct pci2phy_map *__find_pci2phy_map(int segment); · 175 unmodified lines
235	235	int uncore_pcibus_to_dieid(struct pci_bus *bus);
236	236	int uncore_die_to_segment(int die);
237	237	int uncore_device_to_die(struct pci_dev *dev);
	238	+int uncore_die_to_cpu(int die);
238	239
239	240	ssize_t uncore_event_show(struct device *dev,
240	241	struct device_attribute attr, char buf);

arch/x86/events/intel/uncore_discovery.c+31−15

@@ -287,7 +287,7 @@ static int __parse_discovery_table(struct uncore_discovery_domain *domain, · 286 unmodified lines
287	287	if (!io_addr)
288	288	return -ENOMEM;
289	289
290		− if (domain->global_init && domain->global_init(global.ctl)) {
	290	+ if (domain->global_init && domain->global_init(die, global.ctl)) {
291	291	ret = -ENODEV;
292	292	goto out;
293	293	}
@@ -399,7 +399,6 @@ static bool uncore_discovery_msr(struct uncore_discovery_domain *domain) · 105 unmodified lines
399	399	if (!die_mask)
400	400	return false;
401	401
402		− cpus_read_lock();
403	402	for_each_online_cpu(cpu) {
404	403	die = topology_logical_die_id(cpu);
405	404	if (__test_and_set_bit(die, die_mask))
@@ -414,8 +413,6 @@ static bool uncore_discovery_msr(struct uncore_discovery_domain *domain) · 8 unmodified lines
414	413	__parse_discovery_table(domain, base, die, &parsed);
415	414	}
416	415
417		− cpus_read_unlock();
418		−
419	416	kfree(die_mask);
420	417	return parsed;
421	418	}
@@ -429,10 +426,14 @@ bool uncore_discovery(struct uncore_plat_init *init) · 7 unmodified lines
429	426	for (i = 0; i < UNCORE_DISCOVERY_DOMAINS; i++) {
430	427	domain = &init->domain[i];
431	428	if (domain->discovery_base) {
	429	+ cpus_read_lock();
	430	+
432	431	if (!domain->base_is_pci)
433	432	ret \|= uncore_discovery_msr(domain);
434	433	else
435	434	ret \|= uncore_discovery_pci(domain);
	435	+
	436	+ cpus_read_unlock();
436	437	}
437	438	}
438	439
@@ -481,8 +482,8 @@ static u64 intel_generic_uncore_box_ctl(struct intel_uncore_box *box) · 42 unmodified lines
481	482	struct intel_uncore_discovery_unit *unit;
482	483
483	484	unit = intel_uncore_find_discovery_unit(box->pmu->type->boxes,
484		− -1, box->pmu->pmu_idx);
485		− if (WARN_ON_ONCE(!unit))
	485	+ box->dieid, box->pmu->pmu_idx);
	486	+ if (!unit)
486	487	return 0;
487	488
488	489	return unit->addr;
@@ -490,17 +491,28 @@ static u64 intel_generic_uncore_box_ctl(struct intel_uncore_box *box) · 1 unmodified line
490	491
491	492	void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box)
492	493	{
493		− wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_INT);
	494	+ u64 box_ctl = intel_generic_uncore_box_ctl(box);
	495	+
	496	+ if (!box_ctl)
	497	+ return;
	498	+
	499	+ wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_INT);
494	500	}
495	501
496	502	void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box)
497	503	{
498		− wrmsrq(intel_generic_uncore_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ);
	504	+ u64 box_ctl = intel_generic_uncore_box_ctl(box);
	505	+
	506	+ if (box_ctl)
	507	+ wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
499	508	}
500	509
501	510	void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box)
502	511	{
503		− wrmsrq(intel_generic_uncore_box_ctl(box), 0);
	512	+ u64 box_ctl = intel_generic_uncore_box_ctl(box);
	513	+
	514	+ if (box_ctl)
	515	+ wrmsrq(box_ctl, 0);
504	516	}
505	517
506	518	static void intel_generic_uncore_msr_enable_event(struct intel_uncore_box *box,
@@ -549,6 +561,7 @@ bool intel_generic_uncore_assign_hw_event(struct perf_event *event, · 42 unmodified lines
549	561
550	562	if (box->pci_dev) {
551	563	box_ctl = UNCORE_DISCOVERY_PCI_BOX_CTRL(box_ctl);
	564	+
552	565	hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx);
553	566	hwc->event_base = box_ctl + uncore_pci_perf_ctr(box, hwc->idx);
554	567	return true;
@@ -567,27 +580,30 @@ static inline int intel_pci_uncore_box_ctl(struct intel_uncore_box *box) · 12 unmodified lines
567	580
568	581	void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)
569	582	{
570		− struct pci_dev *pdev = box->pci_dev;
571	583	int box_ctl = intel_pci_uncore_box_ctl(box);
572	584
	585	+ if (!box_ctl)
	586	+ return;
	587	+
573	588	__set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags);
574		− pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
	589	+ pci_write_config_dword(box->pci_dev, box_ctl, GENERIC_PMON_BOX_CTL_INT);
575	590	}
576	591
577	592	void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)
578	593	{
579		− struct pci_dev *pdev = box->pci_dev;
580	594	int box_ctl = intel_pci_uncore_box_ctl(box);
581	595
582		− pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);
	596	+ if (box_ctl)
	597	+ pci_write_config_dword(box->pci_dev, box_ctl,
	598	+ GENERIC_PMON_BOX_CTL_FRZ);
583	599	}
584	600
585	601	void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)
586	602	{
587		− struct pci_dev *pdev = box->pci_dev;
588	603	int box_ctl = intel_pci_uncore_box_ctl(box);
589	604
590		− pci_write_config_dword(pdev, box_ctl, 0);
	605	+ if (box_ctl)
	606	+ pci_write_config_dword(box->pci_dev, box_ctl, 0);
591	607	}
592	608
593	609	static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box,

arch/x86/events/intel/uncore_snb.c+0−7

@@ -563,12 +563,6 @@ void tgl_uncore_cpu_init(void) · 562 unmodified lines
563	563	skl_uncore_msr_ops.init_box = rkl_uncore_msr_init_box;
564	564	}
565	565
566		−static void adl_uncore_msr_init_box(struct intel_uncore_box *box)
567		−{
568		− if (box->pmu->pmu_idx == 0)
569		− wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
570		−}
571		−
572	566	static void adl_uncore_msr_enable_box(struct intel_uncore_box *box)
573	567	{
574	568	wrmsrq(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
@@ -587,7 +581,6 @@ static void adl_uncore_msr_exit_box(struct intel_uncore_box *box) · 12 unmodified lines
587	581	}
588	582
589	583	static struct intel_uncore_ops adl_uncore_msr_ops = {
590		− .init_box = adl_uncore_msr_init_box,
591	584	.enable_box = adl_uncore_msr_enable_box,
592	585	.disable_box = adl_uncore_msr_disable_box,
593	586	.exit_box = adl_uncore_msr_exit_box,

arch/x86/events/intel/uncore_snbep.c+12−24

@@ -3704,25 +3704,6 @@ static int skx_msr_cpu_bus_read(int cpu, u64 *topology) · 3703 unmodified lines
3704	3704	return 0;
3705	3705	}
3706	3706
3707		−static int die_to_cpu(int die)
3708		−{
3709		− int res = 0, cpu, current_die;
3710		− /*
3711		− * Using cpus_read_lock() to ensure cpu is not going down between
3712		− * looking at cpu_online_mask.
3713		− */
3714		− cpus_read_lock();
3715		− for_each_online_cpu(cpu) {
3716		− current_die = topology_logical_die_id(cpu);
3717		− if (current_die == die) {
3718		− res = cpu;
3719		− break;
3720		− }
3721		− }
3722		− cpus_read_unlock();
3723		− return res;
3724		−}
3725		−
3726	3707	enum {
3727	3708	IIO_TOPOLOGY_TYPE,
3728	3709	UPI_TOPOLOGY_TYPE,
@@ -3791,11 +3772,17 @@ static void pmu_free_topology(struct intel_uncore_type *type) · 62 unmodified lines
3791	3772	static int skx_pmu_get_topology(struct intel_uncore_type *type,
3792	3773	int (topology_cb)(struct intel_uncore_type, int, int, u64))
3793	3774	{
3794		− int die, ret = -EPERM;
	3775	+ int die, ret = -ENODEV;
3795	3776	u64 cpu_bus_msr;
	3777	+ int cpu;
3796	3778
	3779	+ cpus_read_lock();
3797	3780	for (die = 0; die < uncore_max_dies(); die++) {
3798		− ret = skx_msr_cpu_bus_read(die_to_cpu(die), &cpu_bus_msr);
	3781	+ cpu = uncore_die_to_cpu(die);
	3782	+ if (cpu == -1)
	3783	+ continue;
	3784	+
	3785	+ ret = skx_msr_cpu_bus_read(cpu, &cpu_bus_msr);
3799	3786	if (ret)
3800	3787	break;
3801	3788
@@ -3807,6 +3794,7 @@ static int skx_pmu_get_topology(struct intel_uncore_type *type, · 5 unmodified lines
3807	3794	if (ret)
3808	3795	break;
3809	3796	}
	3797	+ cpus_read_unlock();
3810	3798
3811	3799	return ret;
3812	3800	}
@@ -4261,7 +4249,7 @@ err: · 448 unmodified lines
4261	4249	static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment,
4262	4250	int die, u64 cpu_bus_msr)
4263	4251	{
4264		− int idx, ret;
	4252	+ int idx, ret = 0;
4265	4253	struct intel_uncore_topology *upi;
4266	4254	unsigned int devfn;
4267	4255	struct pci_dev *dev = NULL;
@@ -4274,12 +4262,12 @@ static int skx_upi_topology_cb(struct intel_uncore_type *type, int segment, · 6 unmodified lines
4274	4262	dev = pci_get_domain_bus_and_slot(segment, bus, devfn);
4275	4263	if (dev) {
4276	4264	ret = upi_fill_topology(dev, upi, idx);
	4265	+ pci_dev_put(dev);
4277	4266	if (ret)
4278	4267	break;
4279	4268	}
4280	4269	}
4281	4270
4282		− pci_dev_put(dev);
4283	4271	return ret;
4284	4272	}
4285	4273
@@ -5499,6 +5487,7 @@ static int discover_upi_topology(struct intel_uncore_type *type, int ubox_did, i · 1213 unmodified lines
5499	5487	devfn);
5500	5488	if (dev) {
5501	5489	ret = upi_fill_topology(dev, upi, idx);
	5490	+ pci_dev_put(dev);
5502	5491	if (ret)
5503	5492	goto err;
5504	5493	}
@@ -5506,7 +5495,6 @@ static int discover_upi_topology(struct intel_uncore_type *type, int ubox_did, i · 1 unmodified line
5506	5495	}
5507	5496	err:
5508	5497	pci_dev_put(ubox);
5509		− pci_dev_put(dev);
5510	5498	return ret;
5511	5499	}
5512	5500

arch/x86/events/perf_event.h+4−4

@@ -322,10 +322,8 @@ struct cpu_hw_events { · 321 unmodified lines
322	322	u64 fixed_ctrl_val;
323	323	u64 active_fixed_ctrl_val;
324	324
325		− /* Intel ACR configuration */
	325	+ /* Intel ACR/arch-PEBS configuration */
326	326	u64 acr_cfg_b[X86_PMC_IDX_MAX];
327		− u64 acr_cfg_c[X86_PMC_IDX_MAX];
328		− /* Cached CFG_C values */
329	327	u64 cfg_c_val[X86_PMC_IDX_MAX];
330	328
331	329	/*
@@ -1712,7 +1710,9 @@ extern struct event_constraint intel_glp_pebs_event_constraints[]; · 1380 unmodified lines
1712	1710
1713	1711	extern struct event_constraint intel_grt_pebs_event_constraints[];
1714	1712
1715		−extern struct event_constraint intel_arw_pebs_event_constraints[];
	1713	+extern struct event_constraint intel_cmt_pebs_event_constraints[];
	1714	+
	1715	+extern struct event_constraint intel_dkt_pebs_event_constraints[];
1716	1716
1717	1717	extern struct event_constraint intel_nehalem_pebs_event_constraints[];
1718	1718

kernel/events/core.c+29−0

@@ -58,6 +58,7 @@ · 57 unmodified lines
58	58	#include <linux/percpu-rwsem.h>
59	59	#include <linux/unwind_deferred.h>
60	60	#include <linux/kvm_types.h>
	61	+#include <linux/seq_file.h>
61	62
62	63	#include "internal.h"
63	64
@@ -7546,6 +7547,33 @@ static int perf_fasync(int fd, struct file *filp, int on) · 7482 unmodified lines
7546	7547	return 0;
7547	7548	}
7548	7549
	7550	+static void perf_show_fdinfo(struct seq_file m, struct file f)
	7551	+{
	7552	+ struct perf_event *event = f->private_data;
	7553	+ struct perf_event_context *ctx;
	7554	+ struct mutex *child_mutex;
	7555	+
	7556	+ ctx = perf_event_ctx_lock(event);
	7557	+ child_mutex = event->parent ? &event->parent->child_mutex : &event->child_mutex;
	7558	+ mutex_lock(child_mutex);
	7559	+
	7560	+ seq_printf(m, "perf_event_attr.type:\t%u\n", event->orig_type);
	7561	+ if (event->pmu)
	7562	+ seq_printf(m, "pmu_type:\t%u\n", event->pmu->type);
	7563	+ seq_printf(m, "perf_event_attr.config:\t0x%llx\n", (unsigned long long)event->attr.config);
	7564	+ seq_printf(m, "perf_event_attr.config1:\t0x%llx\n",
	7565	+ (unsigned long long)event->attr.config1);
	7566	+ seq_printf(m, "perf_event_attr.config2:\t0x%llx\n",
	7567	+ (unsigned long long)event->attr.config2);
	7568	+ seq_printf(m, "perf_event_attr.config3:\t0x%llx\n",
	7569	+ (unsigned long long)event->attr.config3);
	7570	+ seq_printf(m, "perf_event_attr.config4:\t0x%llx\n",
	7571	+ (unsigned long long)event->attr.config4);
	7572	+
	7573	+ mutex_unlock(child_mutex);
	7574	+ perf_event_ctx_unlock(event, ctx);
	7575	+}
	7576	+
7549	7577	static const struct file_operations perf_fops = {
7550	7578	.release = perf_release,
7551	7579	.read = perf_read,
@@ -7554,6 +7582,7 @@ static const struct file_operations perf_fops = { · 2 unmodified lines
7554	7582	.compat_ioctl = perf_compat_ioctl,
7555	7583	.mmap = perf_mmap,
7556	7584	.fasync = perf_fasync,
	7585	+ .show_fdinfo = perf_show_fdinfo,
7557	7586	};
7558	7587
7559	7588	/*

Merge tag 'perf-core-2026-06-14' of gitolite.kernel.org:pub/scm/linux/kernel/git/tip/tip

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