RAPL MSR interface supports 2 power limits for package domain, and 1 power limit for other domains, while RAPL MMIO interface supports 2 power limits for both package and dram domains. And when 2 power limits are supported, the FW_LOCK bit is in bit 63 of the register, instead of bit 31. Remove the assumption that only pakcage domain supports 2 power limits. And allow the RAPL interface driver to specify the number of power limits supported, for every single RAPL domain it owns..
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| @@ -104,6 +104,7 @@ struct reg_action { · 103 unmodified lines | ||
| 104 | 104 | * @pcap_rapl_online: CPU hotplug state for each RAPL interface. |
| 105 | 105 | * @reg_unit: Register for getting energy/power/time unit. |
| 106 | 106 | * @regs: Register sets for different RAPL Domains. |
| 107 | + * @limits: Number of power limits supported by each domain. | |
| 107 | 108 | * @read_raw: Callback for reading RAPL interface specific |
| 108 | 109 | * registers. |
| 109 | 110 | * @write_raw: Callback for writing RAPL interface specific |
| @@ -115,6 +116,7 @@ struct rapl_if_priv { · 5 unmodified lines | ||
| 115 | 116 | enum cpuhp_state pcap_rapl_online; |
| 116 | 117 | u64 reg_unit; |
| 117 | 118 | u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX]; |
| 119 | + int limits[RAPL_DOMAIN_MAX]; | |
| 118 | 120 | int (*read_raw)(int cpu, struct reg_action *ra); |
| 119 | 121 | int (*write_raw)(int cpu, struct reg_action *ra); |
| 120 | 122 | }; |