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net: phy: mscc: fix initialization of the MACsec protocol mode

At the very end of the MACsec block initialization in the MSCC PHY driver, the MACsec "protocol mode" is set. This setting should be set based on the PHY id within the package, as the bank used to access the register used depends on this. This was not done correctly, and only the first bank was used leading to the two upper PHYs being unstable when using the VSC8584. This patch fixes it.

Antoine Tenart committed 6 years ago

Commit 0ddfee11 parent 31096c35 files · +21 −10Browse files

Unified · Split

5 files
  1. drivers/net/phy/mscc/mscc.h +2 −0
  2. drivers/net/phy/mscc/mscc_mac.h +3 −3
  3. drivers/net/phy/mscc/mscc_macsec.c +10 −6
  4. drivers/net/phy/mscc/mscc_macsec.h +2 −1
  5. drivers/net/phy/mscc/mscc_main.c +4 −0
drivers/net/phy/mscc/mscc.h+2−0
@@ -354,6 +354,8 @@ struct vsc8531_private { · 353 unmodified lines
354354 u64 *stats;
355355 int nstats;
356356 bool pkg_init;
357+ /* PHY address within the package. */
358+ u8 addr;
357359 /* For multiple port PHYs; the MDIO address of the base PHY in the
358360 * package.
359361 */
drivers/net/phy/mscc/mscc_mac.h+3−3
@@ -152,8 +152,8 @@ · 151 unmodified lines
152152 #define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE BIT(0)
153153 #define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN BIT(4)
154154
155−#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2
156−#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)
157−#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)
155+#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL 0x2
156+#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x) (x)
157+#define MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M GENMASK(2, 0)
158158
159159 #endif /* _MSCC_PHY_LINE_MAC_H_ */
drivers/net/phy/mscc/mscc_macsec.c+10−6
@@ -316,6 +316,8 @@ static void vsc8584_macsec_mac_init(struct phy_device *phydev, · 315 unmodified lines
316316 /* Must be called with mdio_lock taken */
317317 static int __vsc8584_macsec_init(struct phy_device *phydev)
318318 {
319+ struct vsc8531_private *priv = phydev->priv;
320+ enum macsec_bank proc_bank;
319321 u32 val;
320322
321323 vsc8584_macsec_block_init(phydev, MACSEC_INGR);
@@ -351,12 +353,14 @@ static int __vsc8584_macsec_init(struct phy_device *phydev) · 29 unmodified lines
351353 val |= MSCC_FCBUF_ENA_CFG_TX_ENA | MSCC_FCBUF_ENA_CFG_RX_ENA;
352354 vsc8584_macsec_phy_write(phydev, FC_BUFFER, MSCC_FCBUF_ENA_CFG, val);
353355
354− val = vsc8584_macsec_phy_read(phydev, IP_1588,
355− MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL);
356− val &= ~MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
357− val |= MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
358− vsc8584_macsec_phy_write(phydev, IP_1588,
359− MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
356+ proc_bank = (priv->addr < 2) ? PROC_0 : PROC_2;
357+
358+ val = vsc8584_macsec_phy_read(phydev, proc_bank,
359+ MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL);
360+ val &= ~MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M;
361+ val |= MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(4);
362+ vsc8584_macsec_phy_write(phydev, proc_bank,
363+ MSCC_PROC_IP_1588_TOP_CFG_STAT_MODE_CTL, val);
360364
361365 return 0;
362366 }
drivers/net/phy/mscc/mscc_macsec.h+2−1
@@ -64,7 +64,8 @@ enum macsec_bank { · 63 unmodified lines
6464 FC_BUFFER = 0x04,
6565 HOST_MAC = 0x05,
6666 LINE_MAC = 0x06,
67− IP_1588 = 0x0e,
67+ PROC_0 = 0x0e,
68+ PROC_2 = 0x0f,
6869 MACSEC_INGR = 0x38,
6970 MACSEC_EGR = 0x3c,
7071 };
drivers/net/phy/mscc/mscc_main.c+4−0
@@ -1347,6 +1347,8 @@ static int vsc8584_config_init(struct phy_device *phydev) · 1346 unmodified lines
13471347 else
13481348 vsc8531->base_addr = phydev->mdio.addr - addr;
13491349
1350+ vsc8531->addr = addr;
1351+
13501352 /* Some parts of the init sequence are identical for every PHY in the
13511353 * package. Some parts are modifying the GPIO register bank which is a
13521354 * set of registers that are affecting all PHYs, a few resetting the
@@ -1771,6 +1773,8 @@ static int vsc8514_config_init(struct phy_device *phydev) · 418 unmodified lines
17711773 else
17721774 vsc8531->base_addr = phydev->mdio.addr - addr;
17731775
1776+ vsc8531->addr = addr;
1777+
17741778 /* Some parts of the init sequence are identical for every PHY in the
17751779 * package. Some parts are modifying the GPIO register bank which is a
17761780 * set of registers that are affecting all PHYs, a few resetting the