Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux

Pull clock subsystem fixes from Mike Turquette: "A mix of small fixes affecting mostly ARM platforms as well as a discrete clock expander chip. Most fixes are corrections to lousy clock data of one form or another." * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux: clk: mxs: Include clk mxs header file clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate() clk: si5351: Set initial clkout rate when defined in platform data. clk: si5351: Fix clkout rate computation. clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks clk: ux500: clk-sysctrl: handle clocks with no parents clk: ux500: Provide device enumeration number suffix for SMSC911x

Linus Torvalds committed 13 years ago

Commit 0f7dafd2 parents c361cb5 d68c3806 files · +25 −6Browse files

Unified · Split

6 files

drivers/clk/clk-si5351.c +11 −1
drivers/clk/clk-vt8500.c +1 −1
drivers/clk/mxs/clk-imx28.c +1 −0
drivers/clk/samsung/clk-exynos4.c +4 −2
drivers/clk/ux500/clk-sysctrl.c +7 −1
drivers/clk/ux500/u8500_clk.c +1 −1

drivers/clk/clk-si5351.c+11−1

@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, · 931 unmodified lines
932	932	unsigned char reg;
933	933	unsigned char rdiv;
934	934
935		− if (hwdata->num > 5)
	935	+ if (hwdata->num <= 5)
936	936	reg = si5351_msynth_params_address(hwdata->num) + 2;
937	937	else
938	938	reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client, · 538 unmodified lines
1477	1477	return -EINVAL;
1478	1478	}
1479	1479	drvdata->onecell.clks[n] = clk;
	1480	+
	1481	+ /* set initial clkout rate */
	1482	+ if (pdata->clkout[n].rate != 0) {
	1483	+ int ret;
	1484	+ ret = clk_set_rate(clk, pdata->clkout[n].rate);
	1485	+ if (ret != 0) {
	1486	+ dev_err(&client->dev, "Cannot set rate : %d\n",
	1487	+ ret);
	1488	+ }
	1489	+ }
1480	1490	}
1481	1491
1482	1492	ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,

drivers/clk/clk-vt8500.c+1−1

@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, · 182 unmodified lines
183	183	writel(divisor, cdev->div_reg);
184	184	vt8500_pmc_wait_busy();
185	185
186		− spin_lock_irqsave(cdev->lock, flags);
	186	+ spin_unlock_irqrestore(cdev->lock, flags);
187	187
188	188	return 0;
189	189	}

drivers/clk/mxs/clk-imx28.c+1−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	10	*/
11	11
12	12	#include <linux/clk.h>
	13	+#include <linux/clk/mxs.h>
13	14	#include <linux/clkdev.h>
14	15	#include <linux/err.h>
15	16	#include <linux/init.h>

drivers/clk/samsung/clk-exynos4.c+4−2

@@ -791,7 +791,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { · 790 unmodified lines
791	791	GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
792	792	GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
793	793	GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
794		− GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
	794	+ GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
	795	+ CLK_IGNORE_UNUSED, 0),
795	796	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
796	797	GATE(smmu_rotator, "smmu_rotator", "aclk200",
797	798	E4210_GATE_IP_IMAGE, 4, 0, 0),
@@ -819,7 +820,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { · 21 unmodified lines
819	820	GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
820	821	GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
821	822	GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
822		− GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
	823	+ GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
	824	+ CLK_IGNORE_UNUSED, 0),
823	825	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
824	826	GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
825	827	SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),

drivers/clk/ux500/clk-sysctrl.c+7−1

@@ -145,7 +145,13 @@ static struct clk clk_reg_sysctrl(struct device dev, · 144 unmodified lines
145	145	return ERR_PTR(-ENOMEM);
146	146	}
147	147
148		− for (i = 0; i < num_parents; i++) {
	148	+ /* set main clock registers */
	149	+ clk->reg_sel[0] = reg_sel[0];
	150	+ clk->reg_bits[0] = reg_bits[0];
	151	+ clk->reg_mask[0] = reg_mask[0];
	152	+
	153	+ /* handle clocks with more than one parent */
	154	+ for (i = 1; i < num_parents; i++) {
149	155	clk->reg_sel[i] = reg_sel[i];
150	156	clk->reg_bits[i] = reg_bits[i];
151	157	clk->reg_mask[i] = reg_mask[i];

drivers/clk/ux500/u8500_clk.c+1−1

@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, · 324 unmodified lines
325	325	clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
326	326	BIT(0), 0);
327	327	clk_register_clkdev(clk, "fsmc", NULL);
328		− clk_register_clkdev(clk, NULL, "smsc911x");
	328	+ clk_register_clkdev(clk, NULL, "smsc911x.0");
329	329
330	330	clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
331	331	BIT(1), 0);