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Merge tag 'amd-drm-next-5.18-2022-02-11-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.18-2022-02-11-1: amdgpu: - Clean up of power management code - Enable freesync video mode by default - Clean up of RAS code - Improve VRAM access for debug using SDMA - Coding style cleanups - SR-IOV fixes - More display FP reorg - TLB flush fixes for Arcuturus, Vega20 - Misc display fixes - Rework special register access methods for SR-IOV - DP2 fixes - DP tunneling fixes - DSC fixes - More IP discovery cleanups - Misc RAS fixes - Enable both SMU i2c buses where applicable - s2idle improvements - DPCS header cleanup - Add new CAP firmware support for SR-IOV amdkfd: - Misc cleanups - SVM fixes - CRIU support - Clean up MQD manager UAPI: - Add interface to amdgpu CTX ioctl to request a stable power state for profiling https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/207 - Add amdkfd support for CRIU https://github.com/checkpoint-restore/criu/pull/1709 - Remove old unused amdkfd debugger interface Was only implemented for Kaveri and was only ever used by an old HSA tool that was never open sourced radeon: - Fix error handling in radeon_driver_open_kms - UVD suspend fix - Misc fixes

Dave Airlie committed 4 years ago

Commit 123db172 parents e7a09ce 7f161df394 files · +13673 −10912Browse files

Showing the changes to include/uapi (2 of 394 files). Show all

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2 files
  1. include/uapi/drm/amdgpu_drm.h +18 −1
  2. include/uapi/linux/kfd_ioctl.h +86 −6
include/uapi/drm/amdgpu_drm.h+18−1
@@ -206,6 +206,8 @@ union drm_amdgpu_bo_list { · 205 unmodified lines
206#define AMDGPU_CTX_OP_FREE_CTX 2206#define AMDGPU_CTX_OP_FREE_CTX 2
207#define AMDGPU_CTX_OP_QUERY_STATE 3207#define AMDGPU_CTX_OP_QUERY_STATE 3
208#define AMDGPU_CTX_OP_QUERY_STATE2 4208#define AMDGPU_CTX_OP_QUERY_STATE2 4
209#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
210#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
209 211
210/* GPU reset status */212/* GPU reset status */
211#define AMDGPU_CTX_NO_RESET 0213#define AMDGPU_CTX_NO_RESET 0
@@ -238,10 +240,18 @@ union drm_amdgpu_bo_list { · 26 unmodified lines
238#define AMDGPU_CTX_PRIORITY_HIGH 512240#define AMDGPU_CTX_PRIORITY_HIGH 512
239#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023241#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
240 242
243/* select a stable profiling pstate for perfmon tools */
244#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
245#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
246#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
247#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
248#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
249#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
250
241struct drm_amdgpu_ctx_in {251struct drm_amdgpu_ctx_in {
242 /** AMDGPU_CTX_OP_* */252 /** AMDGPU_CTX_OP_* */
243 __u32 op;253 __u32 op;
244 /** For future use, no flags defined so far */254 /** Flags */
245 __u32 flags;255 __u32 flags;
246 __u32 ctx_id;256 __u32 ctx_id;
247 /** AMDGPU_CTX_PRIORITY_* */257 /** AMDGPU_CTX_PRIORITY_* */
@@ -262,6 +272,11 @@ union drm_amdgpu_ctx_out { · 14 unmodified lines
262 /** Reset status since the last call of the ioctl. */272 /** Reset status since the last call of the ioctl. */
263 __u32 reset_status;273 __u32 reset_status;
264 } state;274 } state;
275
276 struct {
277 __u32 flags;
278 __u32 _pad;
279 } pstate;
265};280};
266 281
267union drm_amdgpu_ctx {282union drm_amdgpu_ctx {
@@ -728,6 +743,8 @@ struct drm_amdgpu_cs_chunk_data { · 460 unmodified lines
728 #define AMDGPU_INFO_FW_DMCUB 0x14743 #define AMDGPU_INFO_FW_DMCUB 0x14
729 /* Subquery id: Query TOC firmware version */744 /* Subquery id: Query TOC firmware version */
730 #define AMDGPU_INFO_FW_TOC 0x15745 #define AMDGPU_INFO_FW_TOC 0x15
746 /* Subquery id: Query CAP firmware version */
747 #define AMDGPU_INFO_FW_CAP 0x16
731 748
732/* number of bytes moved for TTM migration */749/* number of bytes moved for TTM migration */
733#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f750#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
include/uapi/linux/kfd_ioctl.h+86−6
@@ -32,9 +32,10 @@ · 31 unmodified lines
32 * - 1.4 - Indicate new SRAM EDC bit in device properties32 * - 1.4 - Indicate new SRAM EDC bit in device properties
33 * - 1.5 - Add SVM API33 * - 1.5 - Add SVM API
34 * - 1.6 - Query clear flags in SVM get_attr API34 * - 1.6 - Query clear flags in SVM get_attr API
35 * - 1.7 - Checkpoint Restore (CRIU) API
35 */36 */
36#define KFD_IOCTL_MAJOR_VERSION 137#define KFD_IOCTL_MAJOR_VERSION 1
37#define KFD_IOCTL_MINOR_VERSION 638#define KFD_IOCTL_MINOR_VERSION 7
38 39
39struct kfd_ioctl_get_version_args {40struct kfd_ioctl_get_version_args {
40 __u32 major_version; /* from KFD */41 __u32 major_version; /* from KFD */
@@ -468,6 +469,82 @@ struct kfd_ioctl_smi_events_args { · 427 unmodified lines
468 __u32 anon_fd; /* from KFD */469 __u32 anon_fd; /* from KFD */
469};470};
470 471
472/**************************************************************************************************
473 * CRIU IOCTLs (Checkpoint Restore In Userspace)
474 *
475 * When checkpointing a process, the userspace application will perform:
476 * 1. PROCESS_INFO op to determine current process information. This pauses execution and evicts
477 * all the queues.
478 * 2. CHECKPOINT op to checkpoint process contents (BOs, queues, events, svm-ranges)
479 * 3. UNPAUSE op to un-evict all the queues
480 *
481 * When restoring a process, the CRIU userspace application will perform:
482 *
483 * 1. RESTORE op to restore process contents
484 * 2. RESUME op to start the process
485 *
486 * Note: Queues are forced into an evicted state after a successful PROCESS_INFO. User
487 * application needs to perform an UNPAUSE operation after calling PROCESS_INFO.
488 */
489
490enum kfd_criu_op {
491 KFD_CRIU_OP_PROCESS_INFO,
492 KFD_CRIU_OP_CHECKPOINT,
493 KFD_CRIU_OP_UNPAUSE,
494 KFD_CRIU_OP_RESTORE,
495 KFD_CRIU_OP_RESUME,
496};
497
498/**
499 * kfd_ioctl_criu_args - Arguments perform CRIU operation
500 * @devices: [in/out] User pointer to memory location for devices information.
501 * This is an array of type kfd_criu_device_bucket.
502 * @bos: [in/out] User pointer to memory location for BOs information
503 * This is an array of type kfd_criu_bo_bucket.
504 * @priv_data: [in/out] User pointer to memory location for private data
505 * @priv_data_size: [in/out] Size of priv_data in bytes
506 * @num_devices: [in/out] Number of GPUs used by process. Size of @devices array.
507 * @num_bos [in/out] Number of BOs used by process. Size of @bos array.
508 * @num_objects: [in/out] Number of objects used by process. Objects are opaque to
509 * user application.
510 * @pid: [in/out] PID of the process being checkpointed
511 * @op [in] Type of operation (kfd_criu_op)
512 *
513 * Return: 0 on success, -errno on failure
514 */
515struct kfd_ioctl_criu_args {
516 __u64 devices; /* Used during ops: CHECKPOINT, RESTORE */
517 __u64 bos; /* Used during ops: CHECKPOINT, RESTORE */
518 __u64 priv_data; /* Used during ops: CHECKPOINT, RESTORE */
519 __u64 priv_data_size; /* Used during ops: PROCESS_INFO, RESTORE */
520 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */
521 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */
522 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */
523 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */
524 __u32 op;
525};
526
527struct kfd_criu_device_bucket {
528 __u32 user_gpu_id;
529 __u32 actual_gpu_id;
530 __u32 drm_fd;
531 __u32 pad;
532};
533
534struct kfd_criu_bo_bucket {
535 __u64 addr;
536 __u64 size;
537 __u64 offset;
538 __u64 restored_offset; /* During restore, updated offset for BO */
539 __u32 gpu_id; /* This is the user_gpu_id */
540 __u32 alloc_flags;
541 __u32 dmabuf_fd;
542 __u32 pad;
543};
544
545/* CRIU IOCTLs - END */
546/**************************************************************************************************/
547
471/* Register offset inside the remapped mmio page548/* Register offset inside the remapped mmio page
472 */549 */
473enum kfd_mmio_remap {550enum kfd_mmio_remap {
@@ -679,16 +756,16 @@ struct kfd_ioctl_set_xnack_mode_args { · 205 unmodified lines
679#define AMDKFD_IOC_WAIT_EVENTS \756#define AMDKFD_IOC_WAIT_EVENTS \
680 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)757 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
681 758
682#define AMDKFD_IOC_DBG_REGISTER \759#define AMDKFD_IOC_DBG_REGISTER_DEPRECATED \
683 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)760 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
684 761
685#define AMDKFD_IOC_DBG_UNREGISTER \762#define AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED \
686 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)763 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
687 764
688#define AMDKFD_IOC_DBG_ADDRESS_WATCH \765#define AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED \
689 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)766 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
690 767
691#define AMDKFD_IOC_DBG_WAVE_CONTROL \768#define AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED \
692 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)769 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
693 770
694#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \771#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
@@ -742,7 +819,10 @@ struct kfd_ioctl_set_xnack_mode_args { · 47 unmodified lines
742#define AMDKFD_IOC_SET_XNACK_MODE \819#define AMDKFD_IOC_SET_XNACK_MODE \
743 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args)820 AMDKFD_IOWR(0x21, struct kfd_ioctl_set_xnack_mode_args)
744 821
822#define AMDKFD_IOC_CRIU_OP \
823 AMDKFD_IOWR(0x22, struct kfd_ioctl_criu_args)
824
745#define AMDKFD_COMMAND_START 0x01825#define AMDKFD_COMMAND_START 0x01
746#define AMDKFD_COMMAND_END 0x22826#define AMDKFD_COMMAND_END 0x23
747 827
748#endif828#endif

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